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Messages from 41200

Article: 41200
Subject: Re: Possibility of RTL and Gate-level simulation dont match?
From: spam_hater_7@email.com (Spam Hater)
Date: Fri, 22 Mar 2002 15:47:33 GMT
Links: << >>  << T >>  << A >>

Now you have some experience.

I have found errors in chips that gate-level simulation did not catch.

I have found errors in gate-level simulation that the simulator did
not catch.

That's why all these tools exist!



On Fri, 22 Mar 2002 08:39:51 +0800, "Kelvin Hsu" <qijun@okigrp.com.sg>
wrote:

>huh...
>well...my experience was that everytime RTL and gatelevel simulation match,
>thus
>later i overlook gate level simulation and skipped them anyway.
>


Article: 41201
Subject: Re: simple Free FPGA tool
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Fri, 22 Mar 2002 16:41:46 -0000
Links: << >>  << T >>  << A >>
sunny wrote
> Could it be that you have a big mouth but not the brains to be
> succsessfull enough to spend some money on the right tools?

I think you sent this by mistake...

We all have champagne tastes and beer budgets.  It is a
requirement for being an engineer.





Article: 41202
Subject: Evaluation board for Virtex-II pro
From: Christian Plessl <plessl@remove.tik.ee.ethz.ch>
Date: Fri, 22 Mar 2002 17:45:54 +0100
Links: << >>  << T >>  << A >>
Does anybody know whether there are already evalution boards for Xilinx 
Virtex-II pro available? Searching the web didnt reveal anything.

TIA,
 Chris

Article: 41203
Subject: Re: Poor availability problems on Coolrunner
From: mikeandmax@aol.com (Mikeandmax)
Date: 22 Mar 2002 16:48:08 GMT
Links: << >>  << T >>  << A >>
Rick asks-
>I was planning on using a Coolrunner part, the XCR3256XL in the FT256
>package on a new design that we want to prototype the end of April. 

>and they are telling me they aren't making parts until MAY/JUNE with a 6
>week lead time.  I expected this meant I needed to order them 6 weeks
>
>Obviouly I need to find a different part.  
>
>The coolrunner was pretty much perfect for the job.  It had 256
>Macrocells and 164 IOs along with 20 mA power consumption that dropped
>to nearly zero when it was not needed.  Of course, it ran from 3.3volts
>and was fully 5 volt tolerant.  Finally it supported JTAG boundary
>scan.  
>
>Is there any chance of finding a part like this elsewhere?  How about if
>I drop the zero power?  I can live with a bit higher power consumption,
>but all of the parts I have found use 100 mA or more when idling!  That
>is more than the MCU!
Hi Rick - 
first - APOLOGY to all for BLATANT PITCH -

have you seen any info regarding LATTICE ispMACH4000 - a new device family -
1.8v core, very highperformance, 4256 and 4512 released in december- readily
available, other devices sampling now with release early Q2 -
1.8 and 2.5v devices avail now - 3.3 in Q2 - all use a 1.8V core - 2.5 and 3.3
have onboard power converters -add 10ma of quiescent - device in 1.8v is <2ma
quiescent - speeds up to 350MHZ in family
check the website -
www.latticesemi.com -
look for ispMACH4000

Michael Thomas
LSC SFAE
New York/New Jersey
631-874-4968 fax 631-874-4977
michael.thomas@latticesemi.com
for the latest info on Lattice products - http://www.latticesemi.com



Article: 41204
Subject: Re: Clock termination affecting JTAG interface
From: nospam@newsguy.com
Date: Fri, 22 Mar 2002 16:48:38 +0000
Links: << >>  << T >>  << A >>
Dean Armstrong <daa1@cs.waikato.ac.nz> wrote:

>Using information from the manufacturer I have established that the 
>impedance of the clock trace is around 90 Ohms, so I terminated it to 5V 
>and to ground, each with 180 Ohm resistors.

>When I do this, however, the JTAG test access port on the Spartan II 
>appears to become unreliable - I am not able to configure the Spartan II 
>via JTAG.

You are effectively terminating with 90R to 2.5v which I doubt is optimum.
You should terminate 'to' the mid point of the receiver logic level
thresholds which I'm guessing will be nearer 1.5v. 

Try 300R to +5v and 130R to 0v.  (270R and 120R is also close). 



Article: 41205
Subject: Re: Clock termination affecting JTAG interface
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Fri, 22 Mar 2002 08:51:35 -0800
Links: << >>  << T >>  << A >>


Paul Burke wrote:

> Can your clock source and sink 28mA? Try isolating the termination with
> a capacitor of negligible impedance at 20MHz, say 10nF. Or try a 91 ohm
> resistor in series with the clock close to the oscillator.
>

Series termination at the source is great for single-destination signals. But
here there are 4 destinations, and the 50% voltage step can cause a lot of
trouble.

But parallel termination at the far end with an RC combination ( 91 Ohm in
series with a few nF) to ground might be a good idea.

Peter Alfke



Article: 41206
Subject: Re: XPOWER accuracy? Commendations
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Fri, 22 Mar 2002 08:58:57 -0800
Links: << >>  << T >>  << A >>


Hal Murray wrote:

> [snip lots of good info]
> >4.
> >As a conscientious designer, you must assume that the data sheet guarantees are
> >valid. But you should also know that this particular leakage-current parameter is
> >usually much lower than the guaranteed spec.
>
> Is there any way to turn that "usually" into something solid
> I can use for worst-case designing?  (or something helpful
> like that)
>

I will not contradict the data sheet. 200 mA is what we screen for, and that's what
is guaranteed.
But I want to point out that this particular parameter ( different from most others)
is usually much, much better. My guess is that 90% ot your parts have less than 15%
of the specified leakage current ( i.e. 30 mA instead of 200 mA ).
But the worst-case guaranteed value is what it is, 200 mA.

Peter Alfke



Article: 41207
Subject: Any DDR SDRAM controller stories?
From: John_H <johnhandwork@mail.com>
Date: Fri, 22 Mar 2002 17:09:33 GMT
Links: << >>  << T >>  << A >>
I'm evaluating the Xilinx reference design for a DDR SDRAM
controller.  The code comes free of charge and reports
133MHz (PC2100) compliance in the VirtexE -7 speed grades
(I'll be using a Spartan-IIE -7).  There are some minor gaps
in the code (adding a refresh counter is simple but the
forced auto-precharge is annoying) which I should be able to
"firm up" to my needs.

Has anyone used this code with success/failure?  Has anyone
worked with other or better DDR controller cores that
they've had good experiences with?

I'm designing a memory bridge where most of our performance
will be targeted at this "local" DDR memory buffer so
keeping latencies down from the processor's perspective is
of great importance.

Thanks for the help!

- John_H


Article: 41208
Subject: Re: Can't program XC4010 with JTAG without BSCAN???
From: google@jfcl.com (Bob Armstrng)
Date: 22 Mar 2002 09:18:07 -0800
Links: << >>  << T >>  << A >>
Arthur <> wrote in message news:<ee75ab9.0@WebX.sUN8CHnE>...

> I believe if you hold INIT low upon powerup, this will stave off the FPGA 
>attempting to configure itself via serial mode. At this point,
interface with
>the device using JTAG and it will allow itself to be programmed with
your
>pattern. This way you can configure the part w/o using the BSCAN
component.
>However the downside to this is that you won't be able to perform
JTAG
>operations (such as erase or re-program) while the device is in
operation >unless you toggle PROG and hold INIT low again...

   I agree about holding INIT low and toggling /PROG to reprogram, and
that's what I'm doing.  Unfortunately neither of these has any effect
on the problem.
It looks like the XC4010E won't finish programming and the I/Os won't
go active unless you include the BSCAN component in your final design.

Thanks anyway,
Bob

Article: 41209
Subject: Pipelined sorting algorithms...
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Fri, 22 Mar 2002 09:45:34 -0800
Links: << >>  << T >>  << A >>

Hi,

I am looking to build a circuit for sorting small data sets,
and am hoping someone here might have some pointers for where
I should start looking for algorithms to do it.

My desire is to build a circuit to do the following:

Every cycle, 16 pieces of data are provided as input.
Some number of cycles later, the data set is provided
at the output, sorted...

The latency isn't a big issue, as long as it is constant,
and I can provide a new data set to the circuit every cycle.

Thanks,
Eric

Article: 41210
Subject: Re: Altera Stratix compared to Xilinx Virtex
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 22 Mar 2002 18:47:41 +0100
Links: << >>  << T >>  << A >>
"Mikeandmax" <mikeandmax@aol.com> schrieb im Newsbeitrag
news:20020322101727.14768.00003774@mb-ba.aol.com...

> >> Anybody using already the Stratix devices?
> >> Any Comments?
>
> but Ray, they are really high performance slides!

;-)))))

My sight of the this in life is, that all things are like complex numbers.
They all have a real and imaginary part. Those marketing slides sure belong
to the imaginary part . . .

--
MfG
Falk





Article: 41211
Subject: Call for Participation FCCM-2002
From: Philip Freidin <philip@fliptronics.com>
Date: Fri, 22 Mar 2002 18:52:36 GMT
Links: << >>  << T >>  << A >>


	    C A L L    F O R    P A R T I C I P A T I O N

			   THE TENTH ANNUAL
		 IEEE SYMPOSIUM ON FIELD PROGRAMMABLE
		      CUSTOM COMPUTING MACHINES
			   Napa, California
			April 21 - 24, 2002

			 http://www.fccm.org

Register now!  The FCCM pre-registration deadline is Monday, 1 April.

Advance registration will be accepted by mail, fax, or online
submission through 1 April 2002. After 1 April, you must pay on-site
registration fees and register at the conference.  That is, online,
mail, and fax registrations will not be accepted after 1 April 2002.

All no-show registrations will be billed in full. Students are
required to show current picture ID cards at the time of registration.

To register, please visit the FCCM home page at http://www.fccm.org.

The registration application accepts MasterCard, Visa, American
Express, and Diners Club cards. If you do not have one of these credit
cards, or if you prefer not to register online, please print out the
form and fax or mail with payment, to:

	IEEE Computer Society
	ATTN: FCCM '02 Registration
	Dept. 6006
	Washington, DC 20042-6006
	(202) 371-1013 Phone
	(202) 728-0884 FAX

Sorry, no phone registrations.
Please make checks payable to IEEE Computer Society.

Registrations received without payment will not be accepted.


		     FCCM'02 PRELIMINARY PROGRAM


----------------------------------------------------------------------
Sunday 21 April 2002 7:00pm - 9:00pm
Registration and reception
----------------------------------------------------------------------


----------------------------------------------------------------------
Monday 22 April 2002 8:30am - 10:00am
Session 1:  Applications I
Chair:  
----------------------------------------------------------------------

Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk, Jason Pelly
Imperial College and Sony Broadcast and Professinoal Research Lab
Image Registration of real-time video data using
the SONIC reconfigurable computer platform

K.H. Tsoi, K.H. Lee and P.H.W. Leong
Chinese University of Hong Kong
A Massively Parallel RC4 Encryption Engine

T. Mitra, T. Chiush
National University of Singapore and State University of New York
An FPGA Implementation of Triangle Mesh Decompression


----------------------------------------------------------------------
Monday 22 April 2002 11:00am - 12:00pm
Session 2:  Networking I
Chair:  Wayne Luk, Imperial College
----------------------------------------------------------------------

G. Brebner
University of Edinburgh
Single-chip Gigabit Mixed-version IP Router on Virtex-II Pro

T. Sproull, J. Lockwood, D. Taylor
Washington University
Control and Configuration Software for a Reconfigurable Networking
Hardware Platform


----------------------------------------------------------------------
Monday 22 April 2002 1:30pm - 3:00pm
Session 3: Tools I
Chair:  
----------------------------------------------------------------------

M. Mishra and S. Goldstein
Carnegie Mellon University
Peer-to-peer Hardware-software Interfaces for Reconfigurable Fabrics

O. Mencer
Lucent
PAM-Blox II: Design and Evaluation of C++ Module Generation for
Computing with FPGAs

Heidi Ziegler, Mary Hall, Joonseok Park, Pedro Diniz and Byoungro So
USC/ISI
Coarse-Grain Pipelining for Multiple FPGA Architectures


----------------------------------------------------------------------
Monday 22 April 2002 4:00pm - 5:00pm
Session 4:  Template Matching
Chair:  
----------------------------------------------------------------------

S. Hezel, A. Kugel, R. Manner and D. Gavrila
University of Mannheim and DaimlerChrysler
FPGA-based Template Matching using Distance Transforms

J. Gause, P.Y.K. Cheung, W. Luk
Imperial College
Reconfigurable Shape-Adaptive Template Matching Architectures


----------------------------------------------------------------------
Monday 22 April 2002 7:00pm - 10:00pm
Demo night
----------------------------------------------------------------------



----------------------------------------------------------------------
Tuesday 23 April 2002 8:30am - 10:00am
Session 5:  Networking II
Chair:  
----------------------------------------------------------------------

R. Franklin, D. Carver and B. Hutchings
Brigham Young University
Assisting Network Intrusion Detection with Reconfigurable Hardware

P. Bellos, J. Flidr, T. Lehman, B. Schott and K. Underwood
USC/ISI and Clemson University
GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate 
Packet Processing 

G. Memik, S. Memik and W. Mangione-Smith
University of Califonia, Los Angeles
Design and Analysis of a Layer Seven Network Processor
Accelerator Using Reconfigurable Logic


----------------------------------------------------------------------
Tuesday 23 April 2002 11:00am - 12:00pm
Session 6:  Architecture I
Chair:  Andre' DeHon, CALTECH
----------------------------------------------------------------------

G. Stitt, B. Grattan and F. Vahid
University of California, Riverside
Using On-Chip Configurable Logic to Reduce Embedded System
Software Energy

H. Schmit, B. Levine and B. Ylvisaker
Carnegie Mellon University
Queue Machines: Hardware Compilation in Hardware


----------------------------------------------------------------------
Tuesday 23 April 2002 1:30pm - 3:00pm
Session 7:  Applications II
Chair:  
----------------------------------------------------------------------

C. Plessl and M. Platzner
Swiss Federal Institute of Technology (ETH) Zurich
Custom Computing Machines for the Set Covering Problem

G. Lienhart, A. Kugel and R. Manner
University of Mannheim
Using Floating Point Arithmetic on FPGAs to Accelerate Scientific 
N-Body Simulations

B.C. Schaffer, S.F. Quigley and A.H.C. Chan
University of Birmingham
Analysis and Implementation of the Discrete Element Method using a
Dedicated Highly Parallel Architecture in Reconfigurable Computing


----------------------------------------------------------------------
Tuesday 23 April 2002 4:00pm - 5:00pm
Session 8:  Architecture II
Chair:  
----------------------------------------------------------------------

Rong Yan and Seth Goldstein
Carnegie Mellon University
Mobile Memory: Improving memory locality in very large reconfigurable
fabrics

A. DeHon, R. Huang, J. Wawrzynek
CALTECH and UC, Berkeley
Hardware-Assisted Fast Routing


----------------------------------------------------------------------
Wednesday 24 April 2002 8:30am - 10:00am
Session 9:  Tools II
Chair:  
----------------------------------------------------------------------

G. Constantinides, P.Y.K. Cheung, W. Luk
Imperial College
Optimum Wordlength Allocation

M. Chang and S. Hauck
University of Washington
Precis: A Design-Time Precision Analysis Tool

D. Kulkami, W. Najjar, R. Rinker and F. Kurdahi
Univ. of Calif, Riverside, Univ. of Idaho, and Univ. of Calif., Irvine
Fast Area Estimation to Support Compiler Optimizations in FPGA-based
Reconfigurable Systems


----------------------------------------------------------------------
Wednesday 24 April 2002 10:30am - 11:30am
Session 10:  Image Compression
Chair:  
----------------------------------------------------------------------

T. Fry, S. Hauck
University of Washington
Hyperspectral Image Compression on Reconfigurable Platforms

M. Sima, S. Cotofina, S. Vassiliadis, J. van Eijndhoven, K. Vissers
Delft University of Technology, Philips Research and TriMedia Technologies
MPEG-compliant Entropy Decoding on FPGA-augmented TriMedia/CPU64


----------------------------------------------------------------------
Monday 22 April 2002 10:00am - 11:00am
Poster Session 1
----------------------------------------------------------------------

F. Cardells-Tormo and J. Valls-Coquillat
Polytechnic University of Valencia
High Performance Quadrature Digital Mixers for FPGAs

S. Melnikoff, S. Quigley and M. Russel
University of Birmingham
Discrete and Continuous Speech Recognition on an FPGA

C. Grassmann, J. Anlauf
Infineon Technologies and University of Bonn
RACER - A Rapid Prototyping Accelerator for Pulsed Neural Networks

H. ElGindy and Y-L Shue
University of New South Wales
On sparse matrix vector multiplication with FPGA-based systems

N. Reis and J. de Sousa
Technical University of Lisbon
On Implementing a Configware/Software SAT Solver

M. Necker, D. Contis, D. Schimmel
Georgia Tech
TCP-Stream reassembly and State Tracking in Hardware

H. Styles and W. Luk
Imperial College
Accelerating Radiosity Algorithms using Reconfigurable Platforms

J. Scalera et. al.
Virginia Tech
Reconfigurable Object Detection in FLIR Image Sequences


----------------------------------------------------------------------
Monday 22 April 2002 3:00pm - 4:00pm
Poster Session 2
----------------------------------------------------------------------

Greg Nash
Centar
Automatic Latency Optimal Design of FPGA-based Systolic Arrays

Theerayod Wiangtong, Peter Cheung and Wayne Luk
Imperial College
Tabu Search with Intensification Strategy for Functional
Partitioning and Scheduling in Hardware-Software Codesign

Wim Bohm, et. al.
Colorado State University and University of California, Riverside
Compiling ATR Probing Codes for Execution on FPGA Hardware

N. Weaver and J. Wawrzynek
University of California, Berkeley
The Effects of Datapath Placement and C-Slow Retiming on Three
Computational Benchmarks

A. Koch and N. Kasprzyk
Technische Universit"at Braunschweig
Module Generator Driving the Compilation for Adaptive Computing
Systems

T. Rissa, M. Vasilko and J. Niittylahti
Tampere University of Technology and Bournmouth University
System-Level Modelling and Implementation
Technique for Run-Time Reconfigurable Systems

J. Ma and P. Athanas
Virginia Tech
Incremental Design Techniques for Million-Gate FPGAs

M. Ward and N.C. Audsley
University of York
Hardware Implementation of Programming Languages
for Real-Time

J.M.P. Cardoso and M. Weinhardt
PACT Informationstechnologie GmbH
Fast and Guaranteed C-Compilation onto the PACT-XPP
Reconfigurable Computing Platform


----------------------------------------------------------------------
Tuesday 23 April 2002 10:00am - 11:00am
Poster Session 3
----------------------------------------------------------------------

T. Yokota et. al.
Utsunomiya Univ, Nagoya Univ. and Univ. of Electro-Communications
A Scalable FPGA-based Custom Computing Machine for
a Medical Image Processing

Y. Cho, S. Navab and W. Mangione-Smith
University of California, Los Angeles
Specialized Hardware for Deep Packet Filtering

J. Tucker, R. Klenke and Q. Shams
Virginia Commonwealth University and NASA Langley Research Center
An Embedded Configurable Computer Module

S. Leon, P. Athanas and M. Jones
Virginia Tech
A Self-Reconfiguring Platform for Embedded Systems

K. Compton, A. Sharma, S. Phillips and S. Hauck
Northwestern University anad University of Washington
Flexible Routing Architecture Generation for Domain-Specific
Reconfigurable Subsystems

J. Cook, D. Gottlieb, J. Walstrom, S. Ferrera, C-W. Wang, N. Carter
University of Illinois
Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor

J. Walstrom, J. Cook, D. Gottlieb, S. Ferrera, C-W. Wang, N. Carter
University of Illinois
The Design of the Amalgam Reconfigurable Cluster

W. Landaker and M. Wirthlin
BYU
Multitasking Configurable Hardware


----------------------------------------------------------------------
Tuesday 23 April 2002 3:00pm - 4:00pm
Poster Session 4
----------------------------------------------------------------------

A. Elbirt and C. Paar
Worcester Polytechnic Institute
COBRA - A Reconfigurable Architecture for Symmetric-Key Algorithms

K.H. Tsoi, O.Y.H. Cheung and P.H.W. Leong
Chinese University of Hong Kong
A Variable-Radix Systolic Montgomery Multiplier

M.P. Leong and P.H.W. Leong
Chinese University of Hong Kong
A Variable-Radix Digit-Serial Architecture

M. Martina, G. Masera, G. Piccinini, F. Vacca, M. Zamboni
Politecnico di Torino
FPGA Superpipelined DSP Core for 3G Wireless Applications

Rama Sangireddy, Huesung Kim, and Arun K. Somani.
Iowa State University 
Timing Issues of Operating Mode Switch in Computing Cache Based
Reconfigurable Architectures

Altaf Abdul Gaffar, Wayne Luk, Peter Y.K. Cheung and Nabeel Shirazi
Imperial College and Xilinx
Automating Customisation of Number Representation

T. Courtney, R. Turner and R. Woods
Queens University Belfast
Mapping Multi-Polynomial parallel CRC circuits to Virtex FPGA
using embedded MUXes

E. Raman, L. Chakrapani, K. Sankaranarayanan and R. Parthasarathi
Indian Institute of Science, Georgia Tech, Univ. of Virginia and Anna Univ.
A Scalable Reconfigurable Architecture For Divisibility Testing Of 
Variable Long Precision Numbers


Philip Freidin
Fliptronics

Article: 41212
Subject: Re: Pipelined sorting algorithms...
From: John_H <johnhandwork@mail.com>
Date: Fri, 22 Mar 2002 19:26:43 GMT
Links: << >>  << T >>  << A >>
Sorts aren't easy.

Do a google search for sorting algorithms and you'll find all sorts of
sorts out there mostly optimized for computing.  The parallel algorithms
may be harder to find - I haven't gotten a good reference yet.

What's the design data set size and clock frequency?  For 16 data sets
in and 16 data sets out, that's a bunch of pins!  Then do you just want
the data output or the indicies to know what the channel order was?
It's a mess in the general sense.

A quick stab for me would be an insertion sort (easy to understand from
a quick google search) if your clock rate is too fast for multiplexing
the comparisons.  The insertion sort would need about 14 SRL sets,
(16*15)/2=120 comparators, 30 20-1 and 105 3-1 registered multiplexers.
Uuuuuhgly.  But it may be better than the bubble sort's 113 comparators
(est) and 113 2-1 swap registers (complementary 2-1 multiplex registers)
with 14 register sets mixed in the middle.

Have fun with this!



Eric Crabill wrote:

> Hi,
>
> I am looking to build a circuit for sorting small data sets,
> and am hoping someone here might have some pointers for where
> I should start looking for algorithms to do it.
>
> My desire is to build a circuit to do the following:
>
> Every cycle, 16 pieces of data are provided as input.
> Some number of cycles later, the data set is provided
> at the output, sorted...
>
> The latency isn't a big issue, as long as it is constant,
> and I can provide a new data set to the circuit every cycle.
>
> Thanks,
> Eric


Article: 41213
Subject: Re: Poor availability problems on Coolrunner
From: "MK" <m.a.k47@ntlworld.com>
Date: Fri, 22 Mar 2002 19:47:49 -0000
Links: << >>  << T >>  << A >>
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3C9B5088.C4ACCCBB@yahoo.com...
> I was planning on using a Coolrunner part, the XCR3256XL in the FT256
> package on a new design that we want to prototype the end of April.  I
> kept trying to get P&A (price and availability) from my disti and was
> not getting an answer for weeks, it was always left off of the message
> that had the P&A of the other parts.  I finally got an answer Wednesday
> and they are telling me they aren't making parts until MAY/JUNE with a 6
> week lead time.  I expected this meant I needed to order them 6 weeks
> ahead.  Now they are telling me that I won't be able to get them until 6
> weeks AFTER May/June.
>
> Obviouly I need to find a different part.
>
> The coolrunner was pretty much perfect for the job.  It had 256
> Macrocells and 164 IOs along with 20 mA power consumption that dropped
> to nearly zero when it was not needed.  Of course, it ran from 3.3volts
> and was fully 5 volt tolerant.  Finally it supported JTAG boundary
> scan.
>
> Is there any chance of finding a part like this elsewhere?  How about if
> I drop the zero power?  I can live with a bit higher power consumption,
> but all of the parts I have found use 100 mA or more when idling!  That
> is more than the MCU!
>
>
If you can use the CS280 package (0.8mm pitch "chip scale" but like a BGA)
they have them ex stock at Xilinx.

Michael Kellett



Article: 41214
Subject: Re: Pipelined sorting algorithms...
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Fri, 22 Mar 2002 12:01:17 -0800
Links: << >>  << T >>  << A >>

Hi,

Each data set consists of 16 pieces of data, each piece of data is
32-bits
(but I'm only sorting on a specific 4-bit field in the data, the rest of
the data just goes along for the ride...)

When I initially searched the web, I found all sorts of exotic methods,
I'm just looking for something simple to implement, and fast (~100 MHz),
and don't care too much about the latency or size of the resulting
design.

Thanks!
Eric

John_H wrote:
> 
> Sorts aren't easy.
> 
> Do a google search for sorting algorithms and you'll find all sorts of
> sorts out there mostly optimized for computing.  The parallel algorithms
> may be harder to find - I haven't gotten a good reference yet.
> 
> What's the design data set size and clock frequency?  For 16 data sets
> in and 16 data sets out, that's a bunch of pins!  Then do you just want
> the data output or the indicies to know what the channel order was?
> It's a mess in the general sense.
> 
> A quick stab for me would be an insertion sort (easy to understand from
> a quick google search) if your clock rate is too fast for multiplexing
> the comparisons.  The insertion sort would need about 14 SRL sets,
> (16*15)/2=120 comparators, 30 20-1 and 105 3-1 registered multiplexers.
> Uuuuuhgly.  But it may be better than the bubble sort's 113 comparators
> (est) and 113 2-1 swap registers (complementary 2-1 multiplex registers)
> with 14 register sets mixed in the middle.
> 
> Have fun with this!
> 
> Eric Crabill wrote:
> 
> > Hi,
> >
> > I am looking to build a circuit for sorting small data sets,
> > and am hoping someone here might have some pointers for where
> > I should start looking for algorithms to do it.
> >
> > My desire is to build a circuit to do the following:
> >
> > Every cycle, 16 pieces of data are provided as input.
> > Some number of cycles later, the data set is provided
> > at the output, sorted...
> >
> > The latency isn't a big issue, as long as it is constant,
> > and I can provide a new data set to the circuit every cycle.
> >
> > Thanks,
> > Eric

Article: 41215
Subject: Re: simple Free FPGA tool
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Fri, 22 Mar 2002 14:08:27 -0600
Links: << >>  << T >>  << A >>
sunny wrote:
> 
> Hi Kevin,
> 
> is there any specific reason why you do use a free and limited version of Xilinx > synthesis and P&R tools and the Modelsim simulator.
>  I assume the reason is that you are not in the positon to spend some money 
> on full versions and well sophisticated software like Synplify or Leonardo and 
> a full (and fast) versions of MTI or NC-Sim. What is the reason why you are not 
> in the position to afford that kind of tools? Could it be that you have a 
> big mouth but not the brains to be succsessfull enough to spend some money on 
> the right tools?
> 


        I guess I have to deal with another hysterical die-hard Altera
fan . . .
I use ISE WebPACK most of the time and sometimes (when I feel like it)
QII + LS-Altera.
I use the above software for personal fun projects, therefore, it
doesn't make much sense to spend several thousands of dollars on EDA
tools.
Would you want to spend thousands of dollars on EDA tools just for
personal use?
I don't think most people will do so, and I will guess that you will
never consider paying thousands of dollars out of your pocket unless you
run some kind of business.
Plus, I don't belong to a company, nor do I run a consulting business,
so I don't have access to any paid version tools.
Just because I don't work for a company that provides paid tools, or
because I only use free tools, I don't think I am a dumb person.
I believe such personal attacks by you is not really welcomed in this
newsgroups, and therefore calling you a "hysterical die-hard Altera fan"
in the beginning of this posting sounds appropriate.
Rather than criticizing me, why not you tell Altera to offer a better
simulator for free?
        My criticism of Altera free tools is not because I hate Altera
for no reason.
Simply, Altera's free tool offerings is buggier, runs fairly unreliably
on Windows 98 PCs (drains system resources very rapidly), and doesn't
let me use a decent simulator.
If they fix most of those problems (especially the simulator), I will
probably give more favorable opinions on Altera tools.
        Another reason why I am pretty much satisfied with ISE WebPACK,
and don't consider getting paid version of it (ISE Foundation) is, ISE
WebPACK has most of what I want (except FPGA Editor), and ModelSim
XE-Starter runs at acceptable speed for my application.
Also, maybe it is not the best, but XST's synthesis quality is good
enough for my projects.
However, if I am going to pay for tools, I probably won't consider
Altera tools since I got burned with them a lot of times.
I will probably go with Xilinx's offerings.




> I donīt know what your problem is.


        I know what the problem is.
All I am saying here is that I think Altera free tools are buggier than
Xilinx's offerings, and it doesn't give a free decent simulator which is
crucial in any kind of development.
I am merely expressing my own opinions, and I did expect some die-hard
Altera fans will not going to like that, but that's too bad.
Your problem is that you are making personal attacks against me
questioning my knowledge or intelligence.
If you disagree with my opinions, well, that is too bad, and you have
the right to disagree with my remarks, but I don't think it is
appropriate to make personal attacks against anyone.



> Thousands of users do take advantage of 
> Altera free tool offerings.

        Is that all the facts to back up your claim that I am wrong that
Xilinx's free offerings is better than Altera's?
I don't care how many people use Altera's free tools: I simply didn't
like Altera's free tools compared to Xilinx's offerings.
However, I still have them in my computer, and I still use them when I
feel like.
What I am doing is I am just recommending other newbies to consider
Xilinx's free offerings because I felt like it was better than Altera's
free offerings.
Those people are free to try out Altera free tools, and decide which one
is better for them.




>  Why dont you just shut up and get lost. 
> Your comments really suck. Iīve never read a comment or posting from you 
> which was of any help to any user.
> 
> sunny


        No, I won't stop expressing my opinion that Altera's offerings
is not as good as Xilinx's offerings even if you launch personal attacks
against me.
I believe my criticism of Altera free tools is a legitimate one since I
back it with my personal experience (fiasco) with them.
I believe the postings I made were helpful to some people. (Maybe 
not to a hysterical person like you who cannot tolerate criticisms.)
If Altera fixes the problems, I will change my opinion about them.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 41216
Subject: Re: Pipelined sorting algorithms...
From: Fabien Todescato <isabelle.todescato@libertysurf.fr>
Date: Fri, 22 Mar 2002 21:11:51 +0100
Links: << >>  << T >>  << A >>
The book "Introduction to Algorithms" has a special section devoted to
sorting networks. You may find the course based on the book on the MIT
web pages at http://web.mit.edu/is/courseweb/courses.html.

Best regards, Fabien

Eric Crabill wrote:

> Hi,
>
> I am looking to build a circuit for sorting small data sets,
> and am hoping someone here might have some pointers for where
> I should start looking for algorithms to do it.
>
> My desire is to build a circuit to do the following:
>
> Every cycle, 16 pieces of data are provided as input.
> Some number of cycles later, the data set is provided
> at the output, sorted...
>
> The latency isn't a big issue, as long as it is constant,
> and I can provide a new data set to the circuit every cycle.
>
> Thanks,
> Eric


Article: 41217
Subject: Re: Poor availability problems on Coolrunner
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 22 Mar 2002 15:16:21 -0500
Links: << >>  << T >>  << A >>
Mikeandmax wrote:
> 
> Rick asks-
> >I was planning on using a Coolrunner part, the XCR3256XL in the FT256
> >package on a new design that we want to prototype the end of April.
> 
> >and they are telling me they aren't making parts until MAY/JUNE with a 6
> >week lead time.  I expected this meant I needed to order them 6 weeks
> >
> >Obviouly I need to find a different part.
> >
> >The coolrunner was pretty much perfect for the job.  It had 256
> >Macrocells and 164 IOs along with 20 mA power consumption that dropped
> >to nearly zero when it was not needed.  Of course, it ran from 3.3volts
> >and was fully 5 volt tolerant.  Finally it supported JTAG boundary
> >scan.
> >
> >Is there any chance of finding a part like this elsewhere?  How about if
> >I drop the zero power?  I can live with a bit higher power consumption,
> >but all of the parts I have found use 100 mA or more when idling!  That
> >is more than the MCU!
> Hi Rick -
> first - APOLOGY to all for BLATANT PITCH -
> 
> have you seen any info regarding LATTICE ispMACH4000 - a new device family -
> 1.8v core, very highperformance, 4256 and 4512 released in december- readily
> available, other devices sampling now with release early Q2 -
> 1.8 and 2.5v devices avail now - 3.3 in Q2 - all use a 1.8V core - 2.5 and 3.3
> have onboard power converters -add 10ma of quiescent - device in 1.8v is <2ma
> quiescent - speeds up to 350MHZ in family
> check the website -
> www.latticesemi.com -
> look for ispMACH4000
> 
> Michael Thomas
> LSC SFAE
> New York/New Jersey
> 631-874-4968 fax 631-874-4977
> michael.thomas@latticesemi.com
> for the latest info on Lattice products - http://www.latticesemi.com

Thanks for the info.  I got a call from the local guy.  I HAVE to have 5
volt tolerance.  The main purpose of this chip is to interface to a
PC/104 bus which has low resistance pullups to 5volts and who knows what
else.  Unfortunately the combination of requirements; 5 volt tolerance,
low power, high pinout in a small package is hard to meet.  The
coolrunner is the only part I have found that does the job even
moderately well.  This part also has to be powered from 3.3 volts.  

BTW, when I ask for help on parts, I certainly don't mind self
promotion.  I only wish I could post my wish list for every part and
have the vendors do all the searching for me.  I am getting to hate the
reply, "check out our data sheet on the web" as if I had nothing better
to do than to download every 4 MB data sheet on every web site and sort
through them all myself.  It is amazing how useful a part or family
overview can be.  This is not aimed at you, so please don't take
offense.  I have spent a lot of time over the last month looking at some
pretty poor web sites.  I don't think Lattice is on my list of bad
sites.  I am just venting some steam over this problem.  

:)


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 41218
Subject: Re: Poor availability problems on Coolrunner
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 22 Mar 2002 21:18:56 +0100
Links: << >>  << T >>  << A >>
"MK" <m.a.k47@ntlworld.com> schrieb im Newsbeitrag
news:U_Lm8.4955$bh1.427859@news11-gui.server.ntli.net...

> If you can use the CS280 package (0.8mm pitch "chip scale" but like a BGA)
> they have them ex stock at Xilinx.

Uhh, but be prepared to have a good PCB manufacturer. We used a CS280
(instead of 256) and it wasnt smooth at all. It can be done, but be
prepared.

--
MfG
Falk





Article: 41219
Subject: Re: Poor availability problems on Coolrunner
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Sat, 23 Mar 2002 08:32:28 +1200
Links: << >>  << T >>  << A >>
rickman wrote:
> 
> I was planning on using a Coolrunner part, the XCR3256XL in the FT256
> package on a new design that we want to prototype the end of April.  I
> kept trying to get P&A (price and availability) from my disti and was
> not getting an answer for weeks, it was always left off of the message
> that had the P&A of the other parts.  I finally got an answer Wednesday
> and they are telling me they aren't making parts until MAY/JUNE with a 6
> week lead time.  I expected this meant I needed to order them 6 weeks
> ahead.  Now they are telling me that I won't be able to get them until 6
> weeks AFTER May/June.
> 
> Obviouly I need to find a different part.
> 
> The coolrunner was pretty much perfect for the job.  It had 256
> Macrocells and 164 IOs along with 20 mA power consumption that dropped
> to nearly zero when it was not needed.  Of course, it ran from 3.3volts
> and was fully 5 volt tolerant.  Finally it supported JTAG boundary
> scan.
> 
> Is there any chance of finding a part like this elsewhere?  How about if
> I drop the zero power?  I can live with a bit higher power consumption,
> but all of the parts I have found use 100 mA or more when idling!  That
> is more than the MCU!

There is no exact match, if you need all the pins and registers.
The Atmel ATF1508ASVL has 128MC, but can pack more into a macrocell.
It does have low static Icc.
Newest Lattice MAC devices are 1.8/2.5V so 5V io is out...
-jg

Article: 41220
Subject: Re: Poor availability problems on Coolrunner
From: mikeandmax@aol.com (Mikeandmax)
Date: 22 Mar 2002 20:45:56 GMT
Links: << >>  << T >>  << A >>
>
>Thanks for the info.  I got a call from the local guy.  I HAVE to have 5
>volt tolerance.  The main purpose of this chip is to interface to a
>PC/104 bus which has low resistance pullups to 5volts and who knows what
>else.  Unfortunately the combination of requirements; 5 volt tolerance,
>low power, high pinout in a small package is hard to meet.  The
>coolrunner is the only part I have found that does the job even
>moderately well.  This part also has to be powered from 3.3 volts.  
>
>BTW, when I ask for help on parts, I certainly don't mind self
>promotion.  I only wish I could post my wish list for every part and
>have the vendors do all the searching for me.  I am getting to hate the
>reply, "check out our data sheet on the web" as if I had nothing better
>to do than to download every 4 MB data sheet on every web site and sort
>through them all myself.  It is amazing how useful a part or family
>overview can be.  This is not aimed at you, so please don't take
>offense.  I have spent a lot of time over the last month looking at some
>pretty poor web sites.  I don't think Lattice is on my list of bad
>sites.  I am just venting some steam over this problem.  
>
>:)
>

Hi Rick-
none taken - I agre with you, sometimes you finish downloading all that stuff
just to find 'no fit' . With most of "our" products  - brand A, brand X and
Lattice included - a product brief is downloadable, <200k.  What is more useful
is to talk with someone, I hope your conversation with the 'local guy' - Stacy
Deming - helped you avoid some time spent. 

good luck with your project-

Michael Thomas
LSC SFAE
New York/New Jersey
631-874-4968 fax 631-874-4977
michael.thomas@latticesemi.com
for the latest info on Lattice products - http://www.latticesemi.com

Article: 41221
Subject: Re: Poor availability problems on Coolrunner
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 22 Mar 2002 16:10:56 -0500
Links: << >>  << T >>  << A >>
MK wrote:
> 
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:3C9B5088.C4ACCCBB@yahoo.com...
> > I was planning on using a Coolrunner part, the XCR3256XL in the FT256
> > package on a new design that we want to prototype the end of April.  I
> > kept trying to get P&A (price and availability) from my disti and was
> > not getting an answer for weeks, it was always left off of the message
> > that had the P&A of the other parts.  I finally got an answer Wednesday
> > and they are telling me they aren't making parts until MAY/JUNE with a 6
> > week lead time.  I expected this meant I needed to order them 6 weeks
> > ahead.  Now they are telling me that I won't be able to get them until 6
> > weeks AFTER May/June.
> >
> > Obviouly I need to find a different part.
> >
> > The coolrunner was pretty much perfect for the job.  It had 256
> > Macrocells and 164 IOs along with 20 mA power consumption that dropped
> > to nearly zero when it was not needed.  Of course, it ran from 3.3volts
> > and was fully 5 volt tolerant.  Finally it supported JTAG boundary
> > scan.
> >
> > Is there any chance of finding a part like this elsewhere?  How about if
> > I drop the zero power?  I can live with a bit higher power consumption,
> > but all of the parts I have found use 100 mA or more when idling!  That
> > is more than the MCU!
> >
> >
> If you can use the CS280 package (0.8mm pitch "chip scale" but like a BGA)
> they have them ex stock at Xilinx.
> 
> Michael Kellett

I had a conversation with the local Avnet/Xilinx FAE and we determined
that the CS280 would support the XC3256XL, but we are not sure if I have
an escape path to the XC3384XL if I outgrow the smaller part.  I really
don't want to use the larger part since it is pushing my $ budget.  But
I may need to make a small FIFO and the 3256 may not be quite big
enough.  

All of the current literature I have says the XC3256XL is the only chip
supported in the CS280.  The FAE said that the 3384 is also available
with 3-4 wk lead time.  Inside sales said it was not on the price list
anywhere.  Any Xilinx guys care to jump in here?  Is the
XC3384XL-xxCS280 on the roadmap?  Is it within view as in, can I order
it to have in my hands in 5 weeks?  

I still need to check with my board houses and see if they are happy
with the finer pitch part.  I really wanted to stay with the FT256 since
it made the 3384 and the 3512 available if I needed growth and it has
the same pitch as the other three BGAs on the board.  Nice and simple, I
think. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 41222
Subject: Re: Poor availability problems on Coolrunner
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Fri, 22 Mar 2002 13:44:14 -0800
Links: << >>  << T >>  << A >>
Rick,

I have asked my friends in CPLD-land here at Xilinx to contact you.  They rely
on Peter or myself to alert them to CPLD issues on this newsgroup.

Let me know if they don't!

I would answer if I could,

Austin

rickman wrote:

> MK wrote:
> >
> > "rickman" <spamgoeshere4@yahoo.com> wrote in message
> > news:3C9B5088.C4ACCCBB@yahoo.com...
> > > I was planning on using a Coolrunner part, the XCR3256XL in the FT256
> > > package on a new design that we want to prototype the end of April.  I
> > > kept trying to get P&A (price and availability) from my disti and was
> > > not getting an answer for weeks, it was always left off of the message
> > > that had the P&A of the other parts.  I finally got an answer Wednesday
> > > and they are telling me they aren't making parts until MAY/JUNE with a 6
> > > week lead time.  I expected this meant I needed to order them 6 weeks
> > > ahead.  Now they are telling me that I won't be able to get them until 6
> > > weeks AFTER May/June.
> > >
> > > Obviouly I need to find a different part.
> > >
> > > The coolrunner was pretty much perfect for the job.  It had 256
> > > Macrocells and 164 IOs along with 20 mA power consumption that dropped
> > > to nearly zero when it was not needed.  Of course, it ran from 3.3volts
> > > and was fully 5 volt tolerant.  Finally it supported JTAG boundary
> > > scan.
> > >
> > > Is there any chance of finding a part like this elsewhere?  How about if
> > > I drop the zero power?  I can live with a bit higher power consumption,
> > > but all of the parts I have found use 100 mA or more when idling!  That
> > > is more than the MCU!
> > >
> > >
> > If you can use the CS280 package (0.8mm pitch "chip scale" but like a BGA)
> > they have them ex stock at Xilinx.
> >
> > Michael Kellett
>
> I had a conversation with the local Avnet/Xilinx FAE and we determined
> that the CS280 would support the XC3256XL, but we are not sure if I have
> an escape path to the XC3384XL if I outgrow the smaller part.  I really
> don't want to use the larger part since it is pushing my $ budget.  But
> I may need to make a small FIFO and the 3256 may not be quite big
> enough.
>
> All of the current literature I have says the XC3256XL is the only chip
> supported in the CS280.  The FAE said that the 3384 is also available
> with 3-4 wk lead time.  Inside sales said it was not on the price list
> anywhere.  Any Xilinx guys care to jump in here?  Is the
> XC3384XL-xxCS280 on the roadmap?  Is it within view as in, can I order
> it to have in my hands in 5 weeks?
>
> I still need to check with my board houses and see if they are happy
> with the finer pitch part.  I really wanted to stay with the FT256 since
> it made the 3384 and the 3512 available if I needed growth and it has
> the same pitch as the other three BGAs on the board.  Nice and simple, I
> think.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX


Article: 41223
Subject: Re: Poor availability problems on Coolrunner
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 22 Mar 2002 16:47:44 -0500
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> 
> rickman wrote:
> >
> > I was planning on using a Coolrunner part, the XCR3256XL in the FT256
> > package on a new design that we want to prototype the end of April.  I
> > kept trying to get P&A (price and availability) from my disti and was
> > not getting an answer for weeks, it was always left off of the message
> > that had the P&A of the other parts.  I finally got an answer Wednesday
> > and they are telling me they aren't making parts until MAY/JUNE with a 6
> > week lead time.  I expected this meant I needed to order them 6 weeks
> > ahead.  Now they are telling me that I won't be able to get them until 6
> > weeks AFTER May/June.
> >
> > Obviouly I need to find a different part.
> >
> > The coolrunner was pretty much perfect for the job.  It had 256
> > Macrocells and 164 IOs along with 20 mA power consumption that dropped
> > to nearly zero when it was not needed.  Of course, it ran from 3.3volts
> > and was fully 5 volt tolerant.  Finally it supported JTAG boundary
> > scan.
> >
> > Is there any chance of finding a part like this elsewhere?  How about if
> > I drop the zero power?  I can live with a bit higher power consumption,
> > but all of the parts I have found use 100 mA or more when idling!  That
> > is more than the MCU!
> 
> There is no exact match, if you need all the pins and registers.
> The Atmel ATF1508ASVL has 128MC, but can pack more into a macrocell.
> It does have low static Icc.
> Newest Lattice MAC devices are 1.8/2.5V so 5V io is out...
> -jg

Thanks for the advice.  But I need 200+ macrocells and will need 140+
IOs.  I also HAVE to have the 5 volt tolerance.  If it wern't for that,
I could leave this part off the board and use a couple of 16 bit buffer
chips for the inter-processor interfaces.  A PC/104 interface requires
some 6 or 7 - 16 bit buffer chips which are way far larger than the
FT256 or CS280 packages.  

I considered an FPGA, but all the Xilinx devices that have 5 volt
tolerance are not very cheap and/or won't run off of 3.3 volts.  :(


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 41224
Subject: Re: Can't program XC4010 with JTAG without BSCAN???
From: Arthur <>
Date: Fri, 22 Mar 2002 13:53:58 -0800
Links: << >>  << T >>  << A >>
In your Bitgen settings - do you have your Startup clock set to Jtag clock instead of CCLK? This could explain the programming complete but 'I/O not active' situation because after the bitstream is sent into the device, the part waits for a few extra clocks in order to start up. These 'start up' actions are things like 'toggle gsr' and 'release IO pins to user mode', etc. and they are, by default, looking for these clock edges on CCLK as opposed to TCK.  This is why you need to make that change in the bitgen setting to 'jtag clock'.

The one hole in this theory is that the bitgen defaults should be the same regardless of if you have the BSCAN component in your design or not..  

Arthur



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