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Messages from 41425

Article: 41425
Subject: Re: Logiblox cells not connected in ISE4.1 HDL project
From: "Aaron Eberhart" <>
Date: Wed, 27 Mar 2002 15:16:10 -0800
Links: << >>  << T >>  << A >>
*bump*

when are they going to add post counts?

Article: 41426
Subject: Partial Reconfiguration (was: GREAT availability on Coolrunner)
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Wed, 27 Mar 2002 23:34:20 -0000
Links: << >>  << T >>  << A >>
Peter Alfke wrote

> Now, what do you need for partial reconfig ?
> I am involved in a Virtex-II design that totally relies on partial
reconfiguration
> How do you want to go about it ?
> I suppose you understand the basics:
> Reconfigure one complete frame at a time. Neither more nor less...

Presumably the Pro parts add a new frame type which covers
the columns over the PPCs.

Can you give us any insight into a realistic scenario for
tool support over the next few years?  Or is it there already
if we just knew where to look?

(trimmed to c.a.fpga)





Article: 41427
Subject: Re: FPGA config without boot PROM???
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Wed, 27 Mar 2002 17:43:15 -0600
Links: << >>  << T >>  << A >>
Peter,

You might have forgotten Actel ProASIC which is flash-based.
I have never used it, so I don't too much about it though.
Why doesn't Xilinx make something like that?



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 41428
Subject: Re: FPGA config without boot PROM???
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 27 Mar 2002 16:04:44 -0800
Links: << >>  << T >>  << A >>


Kevin Brace wrote:

> Peter,
>
> You might have forgotten Actel ProASIC which is flash-based.
> I have never used it, so I don't too much about it though.
> Why doesn't Xilinx make something like that?
>

We have looked at this several times. Here is my -somewhat personal- opinion:

The standard CMOS process without any exotic additions ( like EEPROM or
antifuse) is always better ( smaller, faster, higher-yielding, and earlier
available) than a mixed process. We prefer the most aggressive
microprocessor-oriented process.

The benefit of a EEPROM-based FPGA are really limited to very small designs,
(where single-chip is seen as an advantage) and to certain high-security
applications, which we already cover with triple-DES encrypted bitstreams.

The market niche is small, and we prefer our present, very successful approach.

Peter Alfke



Article: 41429
Subject: Re: Pipelined sorting algorithms...
From: John_H <johnhandwork@mail.com>
Date: Thu, 28 Mar 2002 00:44:07 GMT
Links: << >>  << T >>  << A >>
Ohhhhh, I've figured out what Batcher was all about.  The "bitonic sort"
algorithm is a very nice way to do things!  Rather than the n-1 = 15 cycles of
pipeline to do the sort with 2-input compare/swap elements, the whole 16 values
can be sorted with 10 compare/swap elements.  Wow.  (I prototyped the system in
Excel and it's clean).

If you had a zero-cost method of determining what index corresponded to ranks
0-15, it'd take 16-1 multiplexers (composed of 2 stages of 4-1 muxes for 10
LUTs per bit) 32 bits wide to accomplish the ordering.  The 10-stage
compare/swap uses...  10 LUTs per bit without the cost of finding the index
order!

I'd love to extend the method to 4-input compare/order elements instead of the
2-input items in an attempt to save on resources further, but the direct
bitonic sort is such a pretty method and the complexities are so low.

This post is late but the topic's been on my mind for a few days.  A good sort
can be a nice tool in my verilog toolbox so I wouldn't let it die.



Jonathan Bromley wrote:

> In article <3C9BB6A0.B9DBB6C1@mail.com>, John_H <johnhandwork@mail.com>
> writes
>
> [a radix sort]
> >Sounds like the best approach for the parts he's dealing with.
> [snip]
>
> Radix sorts are good if the key is small (as is yours) but in the
> general case of a larger key there are other hardware-friendly
> methods.
>
> The classic source for this kind of material is Donald Knuth's
> masterly work "The Art of Computer Programming"; volume 3 covers
> sorting and searching.  He describes a method due to Batcher, which
> Knuth calls "merge-exchange" sort.  It maps really nicely on to
> hardware because:
> * it uses lots of instances of a single, simple logic element
>   (compare two values, swap them if they're out of order)
> * it is very pipeline-friendly;  the software algorithm
>   naturally suggests a pipelined hardware implementation
> * although it's fairly extravagant of hardware, as any
>   fully-parallel sort is sure to be, it is not as expensive
>   as some of the better known methods
>
> I have a little C program that "designs" Batcher sorting
> networks for arbitrary numbers of input words:  source code
> by email on request!  Here's its output for a network to sort
> six numbers into order.  The data comes in at the top and
> falls out, sorted, at the bottom.  The "|-|-|-|-|-|" lines
> represent places where a pipeline register could go.
> Strings like "O======O" represent a compare/swap module.
> The numbers on the left represent steps in the algorithm
> given by Knuth, and use the same notation - they only make
> sense if you read his description.
>
> View this in a monospaced font!!!!
> =========================================
>   p,q,r,d =  4, 4, 0, 4  |-|-|-|-|-|
>                          O=======O |
>                          | O=======O
>   p,q,r,d =  2, 4, 0, 2  |-|-|-|-|-|
>                          O===O | | |
>                          | O===O | |
>   p,q,r,d =  2, 2, 2, 2  |-|-|-|-|-|
>                          | | O===O |
>                          | | | O===O
>   p,q,r,d =  1, 4, 0, 1  |-|-|-|-|-|
>                          O=O O=O O=O
>   p,q,r,d =  1, 2, 1, 3  |-|-|-|-|-|
>                          | O=====O |
>   p,q,r,d =  1, 1, 1, 1  |-|-|-|-|-|
>                          | O=O O=O |
>
>   Sorted 6 elements using:
>      6 levels of logic;
>     12 compare/exchange modules.
> =========================================
> --
> Jonathan Bromley
> DOULOS Ltd.
> Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
> Tel: +44 1425 471223                     Email: jonathan.bromley@doulos.com
> Fax: +44 1425 471573                             Web: http://www.doulos.com
>
>                    **********************************
>                    **  Developing design know-how  **
>                    **********************************
>
> This e-mail and any  attachments are  confidential and Doulos Ltd. reserves
> all rights of privilege in  respect thereof. It is intended for the  use of
> the addressee only. If you are not the intended  recipient please delete it
> from  your  system, any  use, disclosure, or copying  of this  document  is
> unauthorised. The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


Article: 41430
Subject: Re: I2C Slave sampling edge
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Thu, 28 Mar 2002 03:50:24 -0000
Links: << >>  << T >>  << A >>
>As for hysteresis, the Spartan pins do not have it built in, but you can
>easily create an input with hsyteresis by using a second pin as a feedback
>output and a pair of resistors.

There is a time delay on that feedback path.  Does that cause any problems?

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 41431
Subject: Re: I2C Slave sampling edge
From: Ray Andraka <ray@andraka.com>
Date: Thu, 28 Mar 2002 04:34:21 GMT
Links: << >>  << T >>  << A >>
It is positive feedback, so unless your signals are toggling very fast, the
delay is of no consequence.  If you are toggling fast enough for it to be an
issue, you probably don't need the hysteresis in the first place.

Hal Murray wrote:

> >As for hysteresis, the Spartan pins do not have it built in, but you can
> >easily create an input with hsyteresis by using a second pin as a feedback
> >output and a pair of resistors.
>
> There is a time delay on that feedback path.  Does that cause any problems?
>
> --
> These are my opinions, not necessarily my employer's.  I hate spam.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 41432
Subject: Re: ByteblasterMV EPM7064S voltage problem
From: "Daniel Lang" <dblx@xtyrvos.caltech.edu>
Date: Wed, 27 Mar 2002 22:18:41 -0800
Links: << >>  << T >>  << A >>
Use a 74HCT244 or 74LS244 for 5 volt operation.
Use the 74HC244 for 3.3 volts.

Daniel Lang

"Arbitrary" <wackedy@XXXhotmail.com> wrote in message
news:eSao8.27742$n4.5472550@newsc.telia.net...
> I am using a 5 meter long cable from the computer to the Byteblaster
perhaps
> this is the cause of my problem. I thought that 5 meters was the longest
> recommendend cable length and since the table I work on is about 5 meters
> away from my computer this is what I used. I tried running a thick wire
from
> the chassis of the computer to the circuit power supply but to no avail.
To
> bad I was really hoping that I could have the programmer next to my work
> table. Anyone know of a way to resolve this other than using a shorter
> cable? I also checked that the chip I used was a 74HC244 which it should
be
> according to the schematic in the ByteblasterMV manual. Anyway thanks for
> all the help you have given me.
>
> Arbitrary
>
>



Article: 41433
Subject: Re: XC9500 low temp. problem
From: "Dziadek" <dziales@poczta.onet.pl>
Date: Thu, 28 Mar 2002 07:43:54 +0100
Links: << >>  << T >>  << A >>
>
>Are you trying to erase and write a new configuration to the CPLD
>in the cold chamber?  Is it necessary for this to work?
>
>Is it OK to configure the CPLD at room temp, and then run the CPLD
>at other temps?  Or, am I misunderstanding the word "configure"?
>
>Jon
>

Hi,

When the startup fails, it is enough to make a readback or verify, then the
device starts OK.
If started in room temp., it works well at low temp.

Dziadek




Article: 41434
Subject: Re: XC9500 low temp. problem
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Thu, 28 Mar 2002 06:48:09 -0000
Links: << >>  << T >>  << A >>
In article <3ca204ed$1@news.vogel.pl>,
 "Dziadek" <dziales@poczta.onet.pl> writes:
>Device: XC95144, industrial temp. grade.
>At room temp. it operates OK.
>At -25 deg C and below it sometimes fails to configure.
>This is rather not the problem of supply, since supply is out of temperature
>chamber during tests and the scope shows that supply rises correctly (20 ms
>time, monotonic or almost monotonic).

Have you looked at the clocks?

When chips get colder they usually get faster.  Maybe one of your
clocks now has a rise time that is fast enough to cause glitches
from reflections.

Might also be ground bounce if you have several outputs switching
at the same time.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 41435
Subject: Filter design problem
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Thu, 28 Mar 2002 09:22:08 +0200
Links: << >>  << T >>  << A >>
Hi,

This is more of a signal processing problem which I am implementing on FPGA
(Spartan II 200k). I have two 40 tap FIR filters for a complex signal. The
imaginary filter is a normal low pass filter which has been convolved with a
hilbert transform. The real filter is just a normal low pass filter.

My question is this: I want to add a dc blocker into the real filter to
attempt to get my passbands in the imaginary and real filters the same. The
imaginary filter has one automatically due to the nature of the hilbert
transform, which makes the roll-off to DC very large. As the filters were
designed using a hamming window, my first attempt was to subtract a 40 unit
hamming window from the real coefficients such that the DC gain of the
coefficients was 0. This is effectively a DC block. However, due to the
nature of the infinite negative spike I have put in the pass band, the
roll-off to DC is not as large as the imaginary filter => pass bands do not
match.

Does anyone have any other ideas on how to implement a DC block and still
have the same roll-off to DC as that in a hilbert transform. It seems this
won't be possible, since the "negative spike" in a hilbert transform is
finite, but the DC block is infinite.

Thanks
Adrian




Article: 41436
Subject: Re: how to prevent infer of Mult18x18 in VirtexII
From: ospyng@yahoo.com (spyng)
Date: 28 Mar 2002 06:23:48 -0800
Links: << >>  << T >>  << A >>
hi,
I have try syn_multstyle both in the verilog code and in the sdc
constraint file.

although, in the *.srr log file it did show that property is added,
but both in the gate level netlist *.srm and the edf the mult18*18 is
still there. any one know is there a bug with the syn_multstyle?

in the *.sdc
define_attribute          {*mult_26bitx4bit_3.I_1*} syn_multstyle
{logic}

in the *.srr
Adding property syn_multstyle, value "logic", to instance
mult_26bitx4bit_3.I_1

in the *.edf
(instance (rename mult_26bitx4bit_3_I_1 "mult_26bitx4bit_3.I_1")
(viewRef PRIM (cellRef MULT18X18 (libraryRef VIRTEX)))

any help?
spyng
thanks






sunny <sunshine@sunrise.at> wrote in message news:<ee75cf4.0@WebX.sUN8CHnE>...
> u could use the synplify attribute
> syn_multstyle = logic. This would prevent Synplify of using the 18x18 multiplier. Information will be forward annotated to ISE thru the ncf.

Article: 41437
Subject: PLLs included in Altera Stratix Devices
From: "Steffen Thieringer" <steffen.thieringer@nmb.co.uk>
Date: Thu, 28 Mar 2002 15:38:53 +0100
Links: << >>  << T >>  << A >>
May provide me with following information about implemented "enhanced PLLs"
in the new Altera Stratix devices:

- what are the thresholds of this phase locked loops?
- how fast are they ajustable within a running system?
- estimated jitter in a noisy environment at low frequencies?

My needs for this circuit:
I need a _very_ accurate phase looked loop for special motors positioning
systems.
With the PLL I have to control and influence measurement equipment which
should be in pase with motor speed and position.
May I use this PLLs for external use?
For any request: Thanks in advance.

Regards,
Steffen


Article: 41438
Subject: Re: cyphers
From: "Wesley J. Landaker" <wjl@ee.byu.edu>
Date: Fri, 29 Mar 2002 15:25:42 +2328
Links: << >>  << T >>  << A >>
<posted & mailed>

On Tuesday 12 March 2002 01:06 pm, in comp.arch.fpga, drake wrote:

> i am looking for VHDL to implement cryptographic cyphers in an FPGA,
> and an FPGA with a PCI interface.  does anybody have any ideas?

See http://sourceforge.net/projects/blowfishvhdl for a VHDL Blowfish 
implementation I originally wrote for a school project a few years ago.

No guarantees that it will work for you (and I've had reports of it failing 
to synthesize on some tools), but it's free and pretty easy to follow VHDL, 
and it worked for me when I slapped it in a Xilinx XCV1000.

-- 
Wesley J. Landaker - wjl@ee.byu.edu
BYU Configurable Computing Laboratory - http://www.jhdl.org
OpenPGP FP: C99E DF40 54F6 B625 FD48  B509 A3DE 8D79 541F F830


Article: 41439
Subject: Re: I2C Slave sampling edge
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 28 Mar 2002 11:20:06 -0500
Links: << >>  << T >>  << A >>
Except that the time delay interferes with the correct operation of the
hysteresis.  If there is a 10 nS delay for the feedback, then you will
have a 10 nS window for noise to cause a glitch after the input crosses
the threshold.  Unfortunately, this is exactly when the slow rising
input is most susceptible to noise causing a glitch.  

Likewise, noise can cause the slow rising input to glitch before it has
reached the true threshold level and the 10 nS delay will prevent the
hysteresis from forcing the input to stay across the threshold level
giving you a second crossing when the slow input finally does cross.  

For hysteresis to work, it needs to be quick.  


Ray Andraka wrote:
> 
> It is positive feedback, so unless your signals are toggling very fast, the
> delay is of no consequence.  If you are toggling fast enough for it to be an
> issue, you probably don't need the hysteresis in the first place.
> 
> Hal Murray wrote:
> 
> > >As for hysteresis, the Spartan pins do not have it built in, but you can
> > >easily create an input with hsyteresis by using a second pin as a feedback
> > >output and a pair of resistors.
> >
> > There is a time delay on that feedback path.  Does that cause any problems?
> >
> > --
> > These are my opinions, not necessarily my employer's.  I hate spam.
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 41440
Subject: Re: how to prevent infer of Mult18x18 in VirtexII
From: Ken McElvain <ken@synplicity.com>
Date: Thu, 28 Mar 2002 17:01:05 GMT
Links: << >>  << T >>  << A >>

You need

define_attribute {<entityname>|I_1*} syn_multstyle {logic}

The syntax  {<entityname>|<objectname>}  finds object <objectname>
relative to <entityname>.  <entityname> is not a path, it is
simply the VHDL entityname or verilog module name.

I imagine that you have multiple instantiations of the entity/module
containing the multipler.


spyng wrote:

> hi,
> I have try syn_multstyle both in the verilog code and in the sdc
> constraint file.
> 
> although, in the *.srr log file it did show that property is added,
> but both in the gate level netlist *.srm and the edf the mult18*18 is
> still there. any one know is there a bug with the syn_multstyle?
> 
> in the *.sdc
> define_attribute          {*mult_26bitx4bit_3.I_1*} syn_multstyle
> {logic}
> 
> in the *.srr
> Adding property syn_multstyle, value "logic", to instance
> mult_26bitx4bit_3.I_1
> 
> in the *.edf
> (instance (rename mult_26bitx4bit_3_I_1 "mult_26bitx4bit_3.I_1")
> (viewRef PRIM (cellRef MULT18X18 (libraryRef VIRTEX)))
> 
> any help?
> spyng
> thanks
> 
> 
> 
> 
> 
> 
> sunny <sunshine@sunrise.at> wrote in message news:<ee75cf4.0@WebX.sUN8CHnE>...
> 
>>u could use the synplify attribute
>>syn_multstyle = logic. This would prevent Synplify of using the 18x18 multiplier. Information will be forward annotated to ISE thru the ncf.
>>


Article: 41441
Subject: time_sim.vhd and time_sim.sdf
From: lapraveen@yahoo.com (praveen)
Date: 28 Mar 2002 09:22:02 -0800
Links: << >>  << T >>  << A >>
Hi,

Is there a way of simulating "time_sim.vhd" and "time_sim.sdf"
filesusing cadence tools?(I'm using Xilinx Foundation Tool 4.1i)

thanks
praveen

Article: 41442
Subject: Re: PLLs included in Altera Stratix Devices
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 28 Mar 2002 09:54:23 -0800
Links: << >>  << T >>  << A >>


Steffen Thieringer wrote:

> I need a _very_ accurate phase looked loop for special motors positioning
> systems.

Steffen, can you give some quantitative data? What is "very accurate"? How much
phase error and jitter can you tolerate? Give us the  picoseconds  :-)

Peter Alfke



Article: 41443
Subject: Re: Handel-C useless.. Move to SystemC
From: Henry Styles <hes2@doc.ic.ac.uk>
Date: Thu, 28 Mar 2002 17:59:34 +0000
Links: << >>  << T >>  << A >>
>I've
>done a couple of experiments with DK1 3.0 and the language is painful
>to use, doesn't leverage C++ and once I do soemthing in Handel-C, I
>can't use with any other design or verification tools like I can with
>SystemC.

wrong, "thank God", and wrong

>There's a germ of value in Celoxica stuff but not while it
>is encumbered by a dead-end proprietary language.
>
>When are these guys going to get real ??

Did you cut and paste this stuff out of the Language Advocate's Guide to
Flaming ? This is such a blatant troll.



Article: 41444
Subject: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 28 Mar 2002 10:02:38 -0800
Links: << >>  << T >>  << A >>


Tim wrote:

> Can you give us any insight into a realistic scenario for
> tool support over the next few years?  Or is it there already
> if we just knew where to look?

Tool support for partial reconfiguration was the question.

I do not have a ready answer. Will try to research this.
I have looked  (very seriously) at designs where the course inter-CLB routing
structure is constant, but the innards of the CLBs and DCMs are being
re-configured. That is not too difficult.
I will get involved more in J-Bits, maybe that is the (partial) answer...
Peter Alfke



Article: 41445
Subject: core generator bus multiplexer and simulation
From: "H.L" <alphaboran@yahoo.com>
Date: Thu, 28 Mar 2002 21:10:27 +0200
Links: << >>  << T >>  << A >>
Hello all,
when I functional simulate a registered (latency 1) bus multiplexer made by
ise 4.1i sp3 core generator in Modelsim I get the right output BUT 1ns after
the clock's rising edge. I open the c_mux_bus_v4.0.vhd in xilinxcorelib
sources and I saw that the model uses 1ns delay in signals' assignments. Can
somebody tell me why that? Also sometimes I get in the rising edge of the
clock some bus conflicts and 1ns (again!!!) the conflicts disappear and I
get the right data :) , in xilinx.com I got some info about bus conflicts
during simulation but for BUFT based bus muxes only (mine is LUT), xilinx
suggestion is to ignore them. Am I in the same case, the only thing is to
ignore them?

Greetings,
Harris



Article: 41446
Subject: I need an advice regarding a switch to a Digital Design Career
From: bilalmo@yahoo.com (BAM)
Date: 28 Mar 2002 11:35:03 -0800
Links: << >>  << T >>  << A >>
Hi,
 This is my first post in this group.
 I have an accepatance for graduate study in the US, i am EXTREMELY
 interested to earn my masters in digital design and DSP. I will be 28
when i graduate with  a masters degree...i am alreadsy an electrical
engineer, and most of my undergarduate courses were electronics
related..i dont have pratical experience,thats job expirience in
digital design, because i come from the middle east, where DSP or
digital design companies dont exist.....but i am very motivated.

 do u think that i am very late to persue a careeer in Digital design,
i mean which company would recruit a 28 year old guy with no previous
exp...

 i need an advice, since  i think this field is somewhat special or
not similar to other classical fileds of electrcal and compuetr
en'g...

 thank very much...

Article: 41447
Subject: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 28 Mar 2002 15:42:19 -0500
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> Tim wrote:
> 
> > Can you give us any insight into a realistic scenario for
> > tool support over the next few years?  Or is it there already
> > if we just knew where to look?
> 
> Tool support for partial reconfiguration was the question.
> 
> I do not have a ready answer. Will try to research this.
> I have looked  (very seriously) at designs where the course inter-CLB routing
> structure is constant, but the innards of the CLBs and DCMs are being
> re-configured. That is not too difficult.
> I will get involved more in J-Bits, maybe that is the (partial) answer...
> Peter Alfke

I am confused.  I thought the web site clearly says that partial
reconfiguration is currently supported in the tools for the VirtexE and
VirtexII devices?  Of course, this is clearly a marketing page with
little technical detail, but they do make this claim without caveats.  

http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=partial_reconfig

and 

http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=modular_design

Am I reading something into this that is not there?  

It is also not clear to me if (or moreso why-not?) this is available for
the Spartan-IIE chips.  They are supposed to be the same as the VirtexE
and I have heard they even support the same bit streams, even though
they don't have as much BRAM.  The modular design page says SpartanII is
supported, but the Partial Reconfig page does not.  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 41448
Subject: Unrecognized LUTs Inserted in A FLEX10KE/ACEX1K Design
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 28 Mar 2002 13:00:25 -0800
Links: << >>  << T >>  << A >>
I am have been playing around with Quartus II 2.0 Web Edition for the
past few days trying to port my PCI IP core to Altera FLEX10KE/ACEX1K.
One problem I observed with FLEX10KE/ACEX1K is that FLEX10KE/ACEX1K
IOE (IOB in Xilinx's devices) has only one FF, and furthermore, it
only seems to support asynchronous clear, and not asynchronous set.
If what I am saying is true, that's pretty bad for PCI because almost
all control signals in PCI are active low, and have to be high when
they detect a reset signal being asserted.
So, I decided not to use the IOE FF for output FFs, and decided to
manually place the output FFs and OE (Output Enable) FFs by near the
pins using floorplanner to reduce routing delay.
The problem I noticed when I manually floorplanned my design is that
when I place the output FFs near the pins, sometimes some of the
output FFs don't go directly into the pins, but get rerouted to
another LEs.
I looked at the equation the one of such LE, and it tells me 
that the LE has only one input (from the output FF), and one output
(finally going towards the pin).
Sometime ago in this newsgroup, I thought I read something like in an
Altera LAB, the local LAB routing can run out when the LAB is about
70% full.
Does my problem have to do something with this issue?
I did notice that when I spread out some of the output FFs to another
LAB, the problem seems to disappear, but I am not 100% sure about
that.



Thanks,



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 41449
Subject: Re: I need an advice regarding a switch to a Digital Design Career
From: "Kevin Neilson" <kevin_neilson@removethis-yahoo.com>
Date: Thu, 28 Mar 2002 21:07:50 GMT
Links: << >>  << T >>  << A >>
I wouldn't say there's no DSP in the middle east; Israel has a slew of DSP
companies.  Not everybody wants to work there though...

I don't think you're going to suffer age discrimination at 28.  Hopefully by
the time you finish your degree hiring will be back up again.  I think there
will probably be a demand for guys with a master's degree in DSP.  Usually
you don't have to worry about age discrimintation for another 15 years at
least.

"BAM" <bilalmo@yahoo.com> wrote in message
news:1cb439a5.0203281135.3bd463a8@posting.google.com...
> Hi,
>  This is my first post in this group.
>  I have an accepatance for graduate study in the US, i am EXTREMELY
>  interested to earn my masters in digital design and DSP. I will be 28
> when i graduate with  a masters degree...i am alreadsy an electrical
> engineer, and most of my undergarduate courses were electronics
> related..i dont have pratical experience,thats job expirience in
> digital design, because i come from the middle east, where DSP or
> digital design companies dont exist.....but i am very motivated.
>
>  do u think that i am very late to persue a careeer in Digital design,
> i mean which company would recruit a 28 year old guy with no previous
> exp...
>
>  i need an advice, since  i think this field is somewhat special or
> not similar to other classical fileds of electrcal and compuetr
> en'g...
>
>  thank very much...





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