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In article <a8dmma$q8f$1@newsreader.mailgate.org>, Kevin Brace
<ihatespam99kevinbraceusenet@ihatespam99hotmail.com> writes
>I have gotten some personal attacks from a few die-hard Altera fans
>because I made some negative comments about Altera's products. (About
>the free tools available from Altera).
>Not everyone is professional in this newsgroup.
Try putting your head over the parapet in sci.electronics.design
to find out what unjustified personal attacks, and unprofessional
behaviour, are all about :-)
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Article: 41601"Anon" <Anon> wrote in message news:a8csm8$j5r$1@slb6.atl.mindspring.net... Well said that man, although exagerated for effect I think. Responses like "read a book" and "show a bit of initiative, man" are not encouraging to self-acknowledged newcomers to the field maybe without access to the resources many of us take for granted. "sympathy is what we need my friends because there's not enough love to go round". Phil -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 41602
Hello Falk, Thanks a lot for your suggestions!!!! Actually I wanted to synchronize two inputs which are continuously changing on different clocks. e.g. say inputA changing on clkA and inputB changing on clkB. and is it is not fixed that wheather clkA is faster or clkB.It can be either way. So can you plz suggest me, is there any method by which I can do it? Thanks and regards, Amit > > ----- Original Message ----- > From: Falk Brunner <Falk.Brunner@gmx.de> > Newsgroups: comp.arch.fpga > Sent: Tuesday, April 02, 2002 11:05 PM > Subject: Re: how to synchronise asynchronous inputs? > > > > > > > > "Amit Deshpande" <amitvlsi@hotmail.com> schrieb im Newsbeitrag > > news:325691ba.0204020647.6be7f0ec@posting.google.com... > > > Hello, > > > > > > Can anybody tell me how to synchronize two asynchronous inputs? > > > > It depends . . . > > > > > one method is pulse streching but in this the input should not change > > > for some fixed time interval. > > > > A common method is oversampling. For this you need a fast clock, at least > so > > fast to give you two samples for the shortest pulse width (e.g. 1us > minimum > > pulse width -> 2 Mhz). But when doing so, a effect called metastability > can > > (and WILL!!) hit you. Do a websearch on this. The solution is to use a > > synchronizer which is nothing else than a one or two stage shift register > > after your sampling flipflop. > > > > > But if the input is continuously changing at faster speed the input > > > data will be lost.And we don't want that. > > > > If you want to capture short pulses with a slow clock, use a flipflop > where > > its input is connected to HIGH and the clock is connectet to your fast > pulse > > input. When there is a rising or falling edge, the flipflop will load a > > HIGH. You can sample this with your low frequency clock and after > detection > > you can reset the flipflop asynchronous. > > > > -- > > MfG > > Falk > > > > > > > > > >Article: 41603
On Wed, 03 Apr 2002 03:25:51 GMT, "sweir" <weirsp@yahoo.com> wrote: >Allan, > >I do not see the distinction that you attempt to draw. This replication is something that a reasonable synthesiser would do, so perhaps it's a little off-topic for this thread. The point I attempted to make was that the synthesiser can create a replicated flip flop which may have a different value to the original flip flop that's described in the RTL source code. If it can have a different value, it must be "a new logical storage point" (to borrow your words). You had asserted that replication did not lead to the creation of a new logical storage point ... but let's not argue semantics. >The fact that timing >variations, ( could be async input, could be a crummy clock tree ), could >yield different results in different places still doesn't seem to address >the issue that to replicate, there must first be a signal or reg to copy. Yes. I didn't mention that in my reply. It wasn't relevant. Please note that I am *not* contradicting your conclusions about the tristate pushthrough feature. Regards, Allan.Article: 41604
Hello, I have a design with the XC2S50 -5TQ144. Implementing my project I have used pullups in UCF Xilinx constrain file. After programming selected pads should be pullup but are not. The implementation log indicate there are pullups. The pads voltage is about 1V and external 2k pullup is too weak. Could you have any idea what is going on? The chip starts (DONE='1') and active outputs are working. Bests regards KrisArticle: 41605
oh,I have uninstall and install QuartusII2.0 many times. But................. fastgirl70@hotmail.com (Girl) wrote in message news:<e8be3828.0204022208.7ead2d4c@posting.google.com>... > Try uninstalling Quartus II v2.0 and re-install it, then install the > service pack and it should work. > > > > lyqin@cti.com.cn (Leon Qin) wrote in message news:<23c59085.0204021913.7c175f07@posting.google.com>... > > Anybody can help me? > > > > btw: > > My Quartus is: > > Version 2.0 build 188 01/22/2002 SJ Full Version > > > > lyqin@cti.com.cn (Leon Qin) wrote in message news:<23c59085.0204012110.53673788@posting.google.com>... > > > When I Try to install Service Pack1 on my machine(P3+Win98 OR > > > P4+Win2000),I get a error Message: > > > "Quartus II 2.0 Full Version is not install on this machine.The > > > Service Pack set will exit now." > > > > > > But I had installed Full Version QuartusII 2.0 on my machine. > > > > > > Why?Article: 41606
Yves Petinot wrote > does any of you know where to find a C-library handling the compilation from > VHDL to the bitstream format ? Any target FPGA will do ... The whole job is something to reserve for a big corporation... But for academic research, the VHDL FAQ (comp.lang.vhdl) has pointers to various VHDL parsers, and Verific (www.verific.com) sell a VHDL and/or Verilog front-end. For the downstream stuff, the nearest I know of is the Xilinx jbits package, though this still leaves you with lots and lots and lots of work to do.Article: 41607
Xilinx removed the tool 'makesrc' from their website because of errors in the program. Does anybody know what these errors are and/or if there exists a similar (working) tool for translating PROM data files into user controlled (ascii) file formats ? Thank you. RolfArticle: 41608
Rolf wrote > Xilinx removed the tool 'makesrc' from their website because of errors in > the program. > Does anybody know what these errors are and/or if there exists a similar > (working) tool for translating PROM data files into user controlled (ascii) > file formats ? As I recall, makesrc was a DOS program which used used a non-standard (i.e. not DPMI) memory extender - probably VCPI. This meant that the user had to reboot to DOS to run the tool, shelling to DOS was not enough. The easiest solution is to write your own. The fpgafaq site has the info. The bit file is just a series of fields, flagged by length codes and markers (0x61, 0x62, ... ), ending with the bit data.Article: 41609
Dear sirs, I'm a newbie and I have a problem with a signal. On my FPGA (Xilinx XCS10 -3 TQ144) I use three pins (P51, P50 and P49 - GP I/O) as indipendent outputs; on the pin 49 (Sig1) and pin 50 (Sig2) I generate signals that change rarely and on the pin 51 (Sig3) I have a fast signal (2 Mhz). On the Sig1 and Sig2 I have a ripple of about 0.8 V (peak to peak) similar to Sig3. It is not a problem of the board, because the pins are unconnected (for the test). In the constrain file I have defineded only the locations. Have somebody an idea about it? Thank a lot. Frank.Article: 41610
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:a8d1vb$l0r@gap.cco.caltech.edu... > "Mark Nelson" <markn@ieee.org> writes: > > >>IBM has a hardware compression chip with a patented algorithm. See: > > >I believe that IBM end-of-lifed that chip last year. Don't know if it is > >possible to get your hands on any more parts. > > That may be true. Though the reference was more to show the > possibilities than to suggest actually buying one. > > The problem then is not to design so close as to infringe the patent. > > One project that I almost worked on needed a hardware decompression, > but could have used a software compressor. The compression algorithm > could use a large table to minimize the table size for decompression, > and also simplify the decompression memory access. > > My favorite asymmetric compression system is the ICT algorithm used > by JPL for Galileo. It runs on an RCA CPD1602, which has no multiply > instruction, but decompression is done on earth, with a much > larger computer. ICT is similar to a DCT algorithm, with the > coefficients selected to minimize the number of '1' bits. In the area of DCTs without multiplies are the binDCT algorithms. I read a few papers on the concept and in hardware they can be very fast given 16-bit data buses for each coefficient. Basically the binDCT computes an approximation of the DCT. It uses only logical shifts, add and subtract operations. The neat thing though is even though it is an approximation of the DCT it still has amazing coding gain which means in the lossy mode it can still compress images well. A nice benefit over the normal DCT though is that the binDCT can be operated in a perfectly lossless mode of operation. TomArticle: 41611
On Wed, 3 Apr 2002 14:10:55 +0100, Tom St Denis wrote
(in message <zbDq8.252$_q1.123@news02.bloor.is.net.cable.rogers.com>):
>
> In the area of DCTs without multiplies are the binDCT algorithms. I read a
> few papers on the concept and in hardware they can be very fast given 16-bit
> data buses for each coefficient. Basically the binDCT computes an
> approximation of the DCT. It uses only logical shifts, add and subtract
> operations. The neat thing though is even though it is an approximation of
> the DCT it still has amazing coding gain which means in the lossy mode it
> can still compress images well. A nice benefit over the normal DCT though
> is that the binDCT can be operated in a perfectly lossless mode of
> operation.
>
> Tom
>
>
Interesting - does it work in a similar vein to integer-based (I forgot the
term, 'invertible' or thereabouts) wavelets? From what I read these also
possess the property of perfect reconstruction.
Regards,
Jose.
--
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Article: 41612The design should be strictly synchroneous, otherwise signals carry odd currents. Are these long highimpedance lines ? What happens when the lines are terminated ? Rene -- Ing.Buero R.Tschaggelar http://www.ibrtses.com Frank Zampa wrote: > Dear sirs, I'm a newbie and I have a problem with a signal. > On my FPGA (Xilinx XCS10 -3 TQ144) I use three pins (P51, P50 and P49 > - GP I/O) as indipendent outputs; on the pin 49 (Sig1) and pin 50 > (Sig2) I generate signals that change rarely and on the pin 51 (Sig3) > I have a fast signal (2 Mhz). > On the Sig1 and Sig2 I have a ripple of about 0.8 V (peak to peak) > similar to Sig3. It is not a problem of the board, because the pins > are unconnected (for the test). In the constrain file I have defineded > only the locations.Article: 41613
"Jose Commins" <axora@axo-AnTiSpaM-ra.net> wrote in message news:01HW.B8D0CB8A000E7D291803C430@news.homechoice.co.uk... > On Wed, 3 Apr 2002 14:10:55 +0100, Tom St Denis wrote > (in message <zbDq8.252$_q1.123@news02.bloor.is.net.cable.rogers.com>): > > > > > In the area of DCTs without multiplies are the binDCT algorithms. I read a > > few papers on the concept and in hardware they can be very fast given 16-bit > > data buses for each coefficient. Basically the binDCT computes an > > approximation of the DCT. It uses only logical shifts, add and subtract > > operations. The neat thing though is even though it is an approximation of > > the DCT it still has amazing coding gain which means in the lossy mode it > > can still compress images well. A nice benefit over the normal DCT though > > is that the binDCT can be operated in a perfectly lossless mode of > > operation. > > > > Tom > > > > > > > Interesting - does it work in a similar vein to integer-based (I forgot the > term, 'invertible' or thereabouts) wavelets? From what I read these also > possess the property of perfect reconstruction. I don't claim to understand it all but the jist of it is that they are performing a lifting type scheme to decompose the DCT into the invertable functions. I can email a zip file with the papers I read if you want. Just contact me via email. TomArticle: 41614
On Wed, 03 Apr 2002 16:27:38 +0200, Rene Tschaggelar <tschaggelar@dplanet.ch> wrote: >The design should be strictly synchroneous, otherwise >signals carry odd currents. Are these long highimpedance >lines ? In the normal use these lines are 40 millimeters long, but for the test are only 8-10 millimeters or only the pin unconnected, but I have the problem too. >What happens when the lines are terminated ? If I add a 10kohm resistor between the pin and GND the ripple is off, but the high voltage is only 3.6 Volt. Frank.Article: 41615
Krzysztof Szczepanski wrote: > > Hello, > > I have a design with the XC2S50 -5TQ144. Implementing my project I have used > pullups in UCF Xilinx constrain file. After programming selected pads should > be pullup but are not. The implementation log indicate there are pullups. > The pads voltage is about 1V and external 2k pullup is too weak. > Could you have any idea what is going on? > The chip starts (DONE='1') and active outputs are working. > > Bests regards > Kris I think what you are saying is that you have tried to enable internal pullups on the pin in the UCF file and the report says that they are there. But when you measure the voltage on the pin, you only read 1 volt. But then you also mention an external pullup of 2k. A 2k pullup should pull the signal all the way to Vdd. So if this is really what you have, there is something wrong with your board, not the FPGA. If you only have the internal pullup on the pin, then I think you should still be seeing larger than 1 volt. But I do remember seeing warings about some internal pullups not being used to pullup external nets. I don't remember if this applies to the IOB pullups or not. I think this was only on configuration control pins and similar. So check your external net and find that 470 ohm resistor pulling it toward ground. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 41616
Is the 0.8V p-p only on the positive logic level of an LVTTL signal? Many engineers worry about a signal "looking good" when the logic levels are just fine. FPGAs aren't meant to be part of an analog chain. Frank Zampa wrote: > > Dear sirs, I'm a newbie and I have a problem with a signal. > On my FPGA (Xilinx XCS10 -3 TQ144) I use three pins (P51, P50 and P49 > - GP I/O) as indipendent outputs; on the pin 49 (Sig1) and pin 50 > (Sig2) I generate signals that change rarely and on the pin 51 (Sig3) > I have a fast signal (2 Mhz). > On the Sig1 and Sig2 I have a ripple of about 0.8 V (peak to peak) > similar to Sig3. It is not a problem of the board, because the pins > are unconnected (for the test). In the constrain file I have defineded > only the locations. > > Have somebody an idea about it? > > Thank a lot. > > Frank.Article: 41617
If you want to sample the B generated data in clock domain A or vice-versa, the asynchronous nature of the clocks can lead to metastability which might be what you're trying to resolve. If you have multiple inputs, the situation is different. For single inputs, use of a single "synchronizing flop" may or may not sample the data "properly" when the data is changing. After a short time (a nanosecond or two in today's devices?) the value of "unsure" will settle to either the previous data value or the new data value. As long as you use this *single register* to drive the rest of the logic in the new domain, the transfer happens cleanly: all logic depending on the input have a stable data value (the same data value) to work from. If the unsynchronized async input drove more than one logical element, the different elements might not agree on previous or new value resulting in strange behavior. The single point makes the decision clean. If you need more than one piece of data to transfer cleanly between clock domains - all changing during the same cycle - a FIFO would be the right element to use. Amit Deshpande wrote: > Hello Falk, > Thanks a lot for your suggestions!!!! > Actually I wanted to synchronize two inputs which are continuously > changing on different clocks. > e.g. say inputA changing on clkA and inputB changing on clkB. and is > it is not fixed that wheather clkA is faster or clkB.It can be either > way. > So can you plz suggest me, is there any method by which I can do it? > > Thanks and regards, > Amit > > > > > ----- Original Message ----- > > From: Falk Brunner <Falk.Brunner@gmx.de> > > Newsgroups: comp.arch.fpga > > Sent: Tuesday, April 02, 2002 11:05 PM > > Subject: Re: how to synchronise asynchronous inputs? > > > > > > > > > > > > > "Amit Deshpande" <amitvlsi@hotmail.com> schrieb im Newsbeitrag > > > news:325691ba.0204020647.6be7f0ec@posting.google.com... > > > > Hello, > > > > > > > > Can anybody tell me how to synchronize two asynchronous inputs? > > > > > > It depends . . . > > > > > > > one method is pulse streching but in this the input should not change > > > > for some fixed time interval. > > > > > > A common method is oversampling. For this you need a fast clock, at least > > so > > > fast to give you two samples for the shortest pulse width (e.g. 1us > > minimum > > > pulse width -> 2 Mhz). But when doing so, a effect called metastability > > can > > > (and WILL!!) hit you. Do a websearch on this. The solution is to use a > > > synchronizer which is nothing else than a one or two stage shift register > > > after your sampling flipflop. > > > > > > > But if the input is continuously changing at faster speed the input > > > > data will be lost.And we don't want that. > > > > > > If you want to capture short pulses with a slow clock, use a flipflop > > where > > > its input is connected to HIGH and the clock is connectet to your fast > > pulse > > > input. When there is a rising or falling edge, the flipflop will load a > > > HIGH. You can sample this with your low frequency clock and after > > detection > > > you can reset the flipflop asynchronous. > > > > > > -- > > > MfG > > > Falk > > > > > > > > > > > > > > > >Article: 41618
My VHDL design uses 'generate' to instantiate a bunch of FDPE primitives (XC4000). These are flip-flops with preset. But one always gets synthesized as an IDFX type, which is an input flip-flop without preset. This changes the circuit function. Why does it do this? How can I prevent it? Thanks, -- Don Teeter * I do NOT speak for the Company *Article: 41619
the maximum clock frequency is highly dependent on your design. it is also highly dependent on quality of source code, quality of synthesis tools, usage of I/O registers, placement of logic. I saw ACEX -3 parts running at 200MHz. I saw bad designs failing at 2MHz.Article: 41620
Check the parallel port settings for your PC in the BIOS. This will control the drive of the port pins used to control that TTL part. Some settings just have a slow pull up on the plus side, others actually drive the pin high. And as a matter of fact, the old original Byteblaster used the LS part and was 5V only, the newer Byteblaster MV had to have used an HC part to support both 5V and 3.3V chips. Regards "Arbitrary" <wackedy@XXXhotmail.com> wrote in message news:<473o8.34884$l93.6947490@newsb.telia.net>... > Hi > I have built myself a ByteblasterMV cable according to the schematic in the > BytblasterMV manual and a small PCB with an EPM7064S mounted on it. Running > the board and Byteblaster on 5 Volts I could examine the chip but when > running verify directly after it discovered somewhere between 300-3000 > errors and also I could not get the blankcheck to pass although the chip is > brand new. Then I started looking for errors everywhere and finally I got > desperate changed the supply voltage. I started by raising the voltage to > around 5.5 V and it didn't work at all then I lowered the voltage to 4.5 > Volts and everything worked perfectly. Increasing the supply voltage above > 4.7 Volts and the errors start to come back. It's great that I can program > the chip but I would prefer if it worked at 5 Volts like its supposed to. > After the chip is programmed its no problem to increase the supply voltage > up to 5 Volts again. The PCB on which the EPM7064S is mounted is basically a > card with pinheaders for all pins on the chip and a few decoupling caps. > > Any help is greatly appreciated > ArbitraryArticle: 41621
It depends on what you're trying to do with your clock, need to supply more detail... "S?awomir Balon" <antyspam.bsl@post.pl> wrote in message news:<a8e5ap$3k4$1@news.tpi.pl>... > Hi! > I'm planning to use ACEX devices in my designs. Can anyone tell me what is > maximum clock frequency for -2 and -3 devices? > I mean external clock input (without clock-lock option). > thanx > SlawekArticle: 41622
Sounds like those pins are being driven low. Is it a bidirectional pin by any chance? What's on the other side of that wire from the pin? Regards "Krzysztof Szczepanski" <kszczepa@poczta.wp.pl> wrote in message news:<a8enmp$a4m$1@korweta.task.gda.pl>... > Hello, > > I have a design with the XC2S50 -5TQ144. Implementing my project I have used > pullups in UCF Xilinx constrain file. After programming selected pads should > be pullup but are not. The implementation log indicate there are pullups. > The pads voltage is about 1V and external 2k pullup is too weak. > Could you have any idea what is going on? > The chip starts (DONE='1') and active outputs are working. > > Bests regards > KrisArticle: 41623
Terry, To bypass any device in a JTAG chain with iMPACT - whether it's an XC18v00 PROM or a third party device, all you need to do is to associate the appropriate BSDL file with the part. I'd suggest that you use these steps to program your device: 1. Connect your cable to the board and launch iMPACT 2. Use File -> Initialize Chain to detect the devices in the chain If iMPACT doesn't at least detect the correct number of devices, and recognize any Xilinx devices in the chain at this point, you probably have a hardware problem. 3. iMPACT will prompt you to assign files to each of the devices. If you want to bypass the 18v00 PROM, you can either assign a .mcs file to it OR you may assign the appropriate BSDL file. The 18v00 BSDL files are installed to the $xilinx\xc1800\data folder, or you can get them from the Xilinx Support website at http://www.support.xilinx.com -> Software -> BSDL Files. Assign your .bit file to the Virtex-II device. 4. You should now be able to program the Virtex-II part. If you get error messages at this point, you may want to consult the Xilinx Answers Database or open a case with Xilinx Technical Support for debugging suggestions. Brendan Bridgford Terry wrote: > Hi all, > > I am testing my designs using the Insight MicroBlaze development board > with the Virtex II 1 million gate FPGA. When configuring the FPGA > directly (ie. bypassing PROM) using the JTAG port, I first attempt to > establish communication through reading the idcode. I received an > error message from iMPACT that the device idcode doesn't match the > idcode in the bsdl file. I'm guessing the problem is related to > bypassing the ISP PROM, and I should perhaps associate the ISP PROM > with either a dummy .mcs file or a .bsd file to bypass it. My > question is: can I just use the generic bsdl file available on the > Xilinx site as the dummy .bsd file? And if so, where should I save > this file and how do I specify that it's targeted for the PROM? > > I'd appreciate any help on this matter, > > TerryArticle: 41624
The pins seem to be driven Low by a resistance of several hundred ohms. That cannot possibly come from inside the chip, where an active output is ten or tens of ohms, alternatively a weak pull-up/down is multiple kilohms. Investigate your board ! Peter Alfke ====================== Jay wrote: > Sounds like those pins are being driven low. Is it a bidirectional > pin by any chance? What's on the other side of that wire from the > pin? > > Regards > > "Krzysztof Szczepanski" <kszczepa@poczta.wp.pl> wrote in message news:<a8enmp$a4m$1@korweta.task.gda.pl>... > > Hello, > > > > I have a design with the XC2S50 -5TQ144. Implementing my project I have used > > pullups in UCF Xilinx constrain file. After programming selected pads should > > be pullup but are not. The implementation log indicate there are pullups. > > The pads voltage is about 1V and external 2k pullup is too weak. > > Could you have any idea what is going on? > > The chip starts (DONE='1') and active outputs are working. > > > > Bests regards > > Kris
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