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Messages from 41750

Article: 41750
Subject: Re: Simulator for xilinx Cores?
From: a_darabiha@yahoo.com (a_darabiha)
Date: 6 Apr 2002 12:02:13 -0800
Links: << >>  << T >>  << A >>
I think I had this kind of problem and finally figured it out from
xilinx
Technical answers #9755. the problem was that it is so 
misleading and poorly documented which takes much longer
than it should to set the things up, 

This is a copy of xilinx instructions:

--CORE Generator: The CORE Generator HDL library models are used for
--                   RTL simulation. 
--
--                   - Add the following line to the
.synopsys_vss.setup file:
--                   XILINXCORELIB : /path_to_directory/xilinxcorelib 
--
--                   - Create the physical directory as follows: 
--                   mkdir /path_to_directory/xilinxcorelib 
--
--
--                   - Then, compile the library in VSS: 
--                   vhdlan -i -w
xilinxcorelib/path_to_directory/<filename>.vhd
--
--                   NOTE: A specific order of compilation needs to be
followed 	--			for CORE
--                   Generator VHDL models. This order can be found in
the file
--                  
"$XILINX/vhdl/src/XilinxCoreLib/vhdl_analyze_order".
--

the thing is that here there are three "/path_to_directoriy/"s
with different meanings !

-the first two should point to your current working directory.
- the last one ( in vhdlan command) should pint to the xilinx
directory
 where the actual xilinxcorelib is.

The other point is that there is a certain order that should be
followed
when compiling cores as is mentioned in xilinx instruction. but the
problem is that sometimes
the cores themself have some sub_cores that need to be compiled first
and
so on and each time one needs to refer to the order list to figure
what should be done first...

imagine how hard it would be to compile all these cores and sub-cores
one by one manually :(

I did that once only for one of my cores but not sure it is the best
way. maybe I should write a script to do that ....

Isn't there any better solution to do that automatically and
recurcively?

Cheers,
Ahmad Darabiha

Article: 41751
Subject: Re: strange RAM timing problem (VirtexE)
From: kayrock66@yahoo.com (Jay)
Date: 6 Apr 2002 12:07:20 -0800
Links: << >>  << T >>  << A >>
I don't think thats verilog unless you have defines a function called
"ram" somewhere else.

One thing to keep in mind is that as I understand it, the Block ram
cannot have an Async read, while the ditributed ram can.  What was
your intended imlimentation?

Regards

spam_hater_7@email.com (Spam Hater) wrote in message news:<3ca3cd6e.2572669@64.164.98.7>...
> Change:
> >assign dout = ram[read_addrb];
> To:
>     dout <= ram(read_addrb);
> 
> 
> 
> On Thu, 28 Mar 2002 19:27:41 -0500, Tullio Grassi
> <tullio@physics.umd.edu> wrote:
> 
> >Hi,
> >
> > in a fpga design for our research project we have differencies
> >between functional simulation and timing simulation.
> >Our verilog design :
> >-  use ActiveHDL in the foreground
> >-  use a lot of VirtexE block RAM, logical simulation is ok.
> >-  infer RAM like that:
> >
> > /********************************************************************************
> >
> >This module is a Dual Port Synchronous RAM.
> >The Xilinx sythesiser XST infers actual RAM from it.
> >Do not change it, but instatiate it in higher level modules.
> >*/
> >`timescale 1ns / 1ns
> >module DP_Syn_RAM
> >   (   clk,    we,   wr_addr,   rd_addr,   din,   dout );
> >parameter
> >    RAM_ADDR_WIDTH = 8,
> >    DATA_WIDTH = 8,
> >    RAM_DEPTH = 256;
> >
> >    input                                 clk;
> >    input                                 we;
> >    input    [RAM_ADDR_WIDTH - 1:0]       wr_addr;
> >    input    [RAM_ADDR_WIDTH - 1:0]       rd_addr;
> >    input    [DATA_WIDTH - 1:0]           din;
> >    output   [DATA_WIDTH - 1:0]           dout;
> >
> >    reg      [DATA_WIDTH - 1:0]           ram [RAM_DEPTH - 1:0];
> >    reg      [RAM_ADDR_WIDTH - 1:0]       read_addrb;
> >
> >always @(posedge clk) begin
> >     if (we)
> >            ram[wr_addr] <= din;
> >            read_addrb  <= rd_addr;
> >      end
> >assign dout = ram[read_addrb];
> >endmodule
> >//******************************************************************************
> >
> >- higher level modules are fully synchronous [always @(posedge clk)...]
> >,
> >   make sure that rd_addr is different from wr_addr at any time; but the
> >signal
> >  interfacing the RAM are NOT latched as the VirtexE data sheet states:
> >  "All inputs are registered with the port clock and have a
> >   set-up to clock timing specification."
> >- asyncronous report is fine (max delay path ~9ns, while Tck=25ns)
> >- syntesis and implementation with XST
> >- from timing simulation we get a lot of errors like:
> >   # : C:\Program Files\Aldec\Active-HDL
> >5.1\vlib\OVI_Simprim/./src/x_ramb4_s16_s16.v, 0:
> >  Timing violation in
> >/daqpath/\ram_derandomizer/drnd13/Mram_ram_inst_ramb_7 \
> >   # : $recovery(CLKB:13987,CLKA:13997,2328)
> >  They happen at every clk edge, for most of the block rams.
> >- Some output waveforms are wrong: the dout from a few rams are wrong
> >  and data seem to come from a location different from the location
> >  actually addressed. These RAMs are part of o group of 24 parallel RAMs
> >
> >  (that is sharing the same address lines). Is a fanout problem ?
> >
> >Thanks in advance for any help,
> >
> >Tullio Grassi
> >
> >======================================
> >Univ. of Maryland - Dept. of Physics
> >College Park, MD 20742 - US
> >Tel +1 301 405 5970
> >Fax +1 301 699 9195
> >======================================
> >

Article: 41752
Subject: Re: Distributed ram
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sat, 6 Apr 2002 22:12:29 +0200
Links: << >>  << T >>  << A >>
"Jay" <kayrock66@yahoo.com> schrieb im Newsbeitrag
news:d049f91b.0204061124.3907028c@posting.google.com...
> I hear the newest Altera FPGA product line (Stratix?) has ram blocks
> in 3 levels of granularity, from little chuncks on up to big 'uns.
> You don't have to give up any of your logic resources to use them
> either.

The holy light of Stratix (tm) will save our souls from the demon of old,
crude technology of today.
Praise the name of the lord.
Amen.

SCNR.
;-))

--
MfG
Falk




Article: 41753
Subject: Re: How to probe internal signals from Xilinx netlist?
From: "Steve Casselman" <sc.nospam@vcc.com>
Date: Sat, 06 Apr 2002 20:53:58 GMT
Links: << >>  << T >>  << A >>
I think that chipscope gets inserted at the edif level. Why is it that you
can't simulate it? Why not hook up the signals you want to look at and run
them into a block ram?

If your using VHDL it might be less messy in the gate level netlist if you
name everything. You usually just name a component, process or entity. You
can label any statement though.

my_and_gate: a<=b and c;

If you don't do this any synthesis tool will give it some odd name (usually
different every time).

Steve

> Chipscope, as awesome as it is, is only useful after its been loaded
> into an actual FPGA.  I think the question was regarding simulation of
> a gate level netlist.




Article: 41754
Subject: Re: How sensitive is the EPM7064?
From: "Alexander Miks" <monstrum@tiscali.se>
Date: Sat, 6 Apr 2002 23:37:25 +0200
Links: << >>  << T >>  << A >>
I'm pretty sure that the unused I/O's are set to output, and nothing are
driving them. But could this actually have caused the problem or is there
something else that I haven't thought of.

"Cyra.Nargolwalla" <Cyra.Nargolwalla@wanadoo.fr> wrote
news:a8mm5i$l94$1@wanadoo.fr...
> What is the exact reference of the device you are using?
>
> I would recommend to look at the report file in order to verify how each
> pins (included the unused user I/Os) should be connected.
>
> "Alexander Miks" <monstrum@tiscali.se> a écrit dans le message de news:
> nDpr8.1110$m4.20430@news010.worldonline.se...
> > I've built a small prototypeboard for experimenting with this Altera
PLD.
> > Basically, all pins are routed to some expansions connectors. But I
really
> > don't know what happened, because first I managed to download a simple
> > design into the chip. It was just an input connected through a
T-flipflop
> to
> > an outout. Then I hooked up a led to the output (through a 1k resistor),
> and
> > had a 1kHz clock connected to the input. Everything worked, wow I
though.
> > But then I touched the chip and noticed it was very hot. The led still
> > toggled as it was supposed to, but the programmer got no contact. I've
> > dubble-checked all connections and there are no shorts or missroutings.
> I've
> > heard of the so called latch-up effect on the inputs when they're not
> > connected but can that really have made the chip get hot and crack?
> >
> >
>
>



Article: 41755
Subject: Re: Distributed ram
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Sun, 07 Apr 2002 01:52:15 GMT
Links: << >>  << T >>  << A >>


Falk Brunner wrote:
> 
> "Jay" <kayrock66@yahoo.com> schrieb im Newsbeitrag
> news:d049f91b.0204061124.3907028c@posting.google.com...
> > I hear the newest Altera FPGA product line (Stratix?) has ram blocks
> > in 3 levels of granularity, from little chuncks on up to big 'uns.
> > You don't have to give up any of your logic resources to use them
> > either.
> 
> The holy light of Stratix (tm) will save our souls from the demon of old,
> crude technology of today.
> Praise the name of the lord.
> Amen.
> 
> SCNR.
> ;-))

I looked at the stratix data, but the size is a bit of an
overkill. I need an acex size stratix *now*. AFAIK, the
flex 10K has the same problems too.

Article: 41756
Subject: Re: strange RAM timing problem (VirtexE)
From: spam_hater_7@email.com (Spam Hater)
Date: Sun, 07 Apr 2002 02:10:37 GMT
Links: << >>  << T >>  << A >>

For a sync RAM, the output is latched based on the address that -was-
latched.  Not the address that is latched.  The data comes out a full
clock later.

Yeah, there will have to be a memory function.  or ram[read_addr]



On 6 Apr 2002 12:07:20 -0800, kayrock66@yahoo.com (Jay) wrote:

>I don't think thats verilog unless you have defines a function called
>"ram" somewhere else.
>
>One thing to keep in mind is that as I understand it, the Block ram
>cannot have an Async read, while the ditributed ram can.  What was
>your intended imlimentation?
>
>Regards
>
>spam_hater_7@email.com (Spam Hater) wrote in message news:<3ca3cd6e.2572669@64.164.98.7>...
>> Change:
>> >assign dout = ram[read_addrb];
>> To:
>>     dout <= ram(read_addrb);
>> 
>> 
>> 
>> On Thu, 28 Mar 2002 19:27:41 -0500, Tullio Grassi
>> <tullio@physics.umd.edu> wrote:
>> 
>> >Hi,
>> >
>> > in a fpga design for our research project we have differencies
>> >between functional simulation and timing simulation.
>> >Our verilog design :
>> >-  use ActiveHDL in the foreground
>> >-  use a lot of VirtexE block RAM, logical simulation is ok.
>> >-  infer RAM like that:
>> >
>> > /********************************************************************************
>> >
>> >This module is a Dual Port Synchronous RAM.
>> >The Xilinx sythesiser XST infers actual RAM from it.
>> >Do not change it, but instatiate it in higher level modules.
>> >*/
>> >`timescale 1ns / 1ns
>> >module DP_Syn_RAM
>> >   (   clk,    we,   wr_addr,   rd_addr,   din,   dout );
>> >parameter
>> >    RAM_ADDR_WIDTH = 8,
>> >    DATA_WIDTH = 8,
>> >    RAM_DEPTH = 256;
>> >
>> >    input                                 clk;
>> >    input                                 we;
>> >    input    [RAM_ADDR_WIDTH - 1:0]       wr_addr;
>> >    input    [RAM_ADDR_WIDTH - 1:0]       rd_addr;
>> >    input    [DATA_WIDTH - 1:0]           din;
>> >    output   [DATA_WIDTH - 1:0]           dout;
>> >
>> >    reg      [DATA_WIDTH - 1:0]           ram [RAM_DEPTH - 1:0];
>> >    reg      [RAM_ADDR_WIDTH - 1:0]       read_addrb;
>> >
>> >always @(posedge clk) begin
>> >     if (we)
>> >            ram[wr_addr] <= din;
>> >            read_addrb  <= rd_addr;
>> >      end
>> >assign dout = ram[read_addrb];
>> >endmodule
>> >//******************************************************************************
>> >
>> >- higher level modules are fully synchronous [always @(posedge clk)...]
>> >,
>> >   make sure that rd_addr is different from wr_addr at any time; but the
>> >signal
>> >  interfacing the RAM are NOT latched as the VirtexE data sheet states:
>> >  "All inputs are registered with the port clock and have a
>> >   set-up to clock timing specification."
>> >- asyncronous report is fine (max delay path ~9ns, while Tck=25ns)
>> >- syntesis and implementation with XST
>> >- from timing simulation we get a lot of errors like:
>> >   # : C:\Program Files\Aldec\Active-HDL
>> >5.1\vlib\OVI_Simprim/./src/x_ramb4_s16_s16.v, 0:
>> >  Timing violation in
>> >/daqpath/\ram_derandomizer/drnd13/Mram_ram_inst_ramb_7 \
>> >   # : $recovery(CLKB:13987,CLKA:13997,2328)
>> >  They happen at every clk edge, for most of the block rams.
>> >- Some output waveforms are wrong: the dout from a few rams are wrong
>> >  and data seem to come from a location different from the location
>> >  actually addressed. These RAMs are part of o group of 24 parallel RAMs
>> >
>> >  (that is sharing the same address lines). Is a fanout problem ?
>> >
>> >Thanks in advance for any help,
>> >
>> >Tullio Grassi
>> >
>> >======================================
>> >Univ. of Maryland - Dept. of Physics
>> >College Park, MD 20742 - US
>> >Tel +1 301 405 5970
>> >Fax +1 301 699 9195
>> >======================================
>> >


Article: 41757
Subject: Re: Distributed ram
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Sat, 06 Apr 2002 19:05:35 -0800
Links: << >>  << T >>  << A >>
Although the English language has little in the way of declination and
conjugation, it still has present, past, and future tense.
So we should be precise:   "Stratix will have"...
It ain't there yet... Even a copy-job takes time.
In the meantime, you can buy today from the company that invented most of
Stratix' future features.

Peter Alfke, Xilinx Applications
===================
Russell Shaw wrote:

> Falk Brunner wrote:
> >
> > "Jay" <kayrock66@yahoo.com> schrieb im Newsbeitrag
> > news:d049f91b.0204061124.3907028c@posting.google.com...
> > > I hear the newest Altera FPGA product line (Stratix?) has ram blocks
> > > in 3 levels of granularity, from little chuncks on up to big 'uns.
> > > You don't have to give up any of your logic resources to use them
> > > either.
> >
> > The holy light of Stratix (tm) will save our souls from the demon of old,
> > crude technology of today.
> > Praise the name of the lord.
> > Amen.
> >
> > SCNR.
> > ;-))
>
> I looked at the stratix data, but the size is a bit of an
> overkill. I need an acex size stratix *now*. AFAIK, the
> flex 10K has the same problems too.


Article: 41758
Subject: Re: strange RAM timing problem (VirtexE)
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Sat, 06 Apr 2002 19:16:39 -0800
Links: << >>  << T >>  << A >>



Spam Hater wrote:

> For a sync RAM, the output is latched based on the address that -was-
> latched.  Not the address that is latched.  The data comes out a full
> clock later.

That statement is dead wrong !!!
The Xilinx BlockRAMs are NOT internally pipelined.
The active edge of an enabled  clock starts an unstoppable sequence of events that first  latch
up the address and write-data, determine read or write, and soon after (still in the same clock
cycle) latch up the data output.
And Virtex-II has three options for the data output while writing: latch up the old content,
latch up the new content, or just ignore everything andstay latched up.

Peter Alfke, Xilinx Applications





Article: 41759
Subject: Xilinx programmer
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Sun, 07 Apr 2002 05:11:22 GMT
Links: << >>  << T >>  << A >>
Hi,

What is the recommended spartan-xc2s30 variant that has 5V tolerant
inputs and 3.3V outputs?

Will this programmer work for it? :

  http://toolbox.xilinx.com/docsan/2_1i/data/common/jtg/fig26.htm
  http://toolbox.xilinx.com/docsan/2_1i/data/common/jtg/jtg.htm

Article: 41760
Subject: Re: How to probe internal signals from Xilinx netlist?
From: wacky_me@rediffmail.com (freny)
Date: 6 Apr 2002 23:34:35 -0800
Links: << >>  << T >>  << A >>
> I think that chipscope gets inserted at the edif level. Why is it that you
> can't simulate it? Why not hook up the signals you want to look at and run
> them into a block ram?

hey,

how do u hook up the signals into the block ram
tell me the actuall process

Article: 41761
Subject: Re: Xilinx programmer
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sun, 7 Apr 2002 10:31:07 +0200
Links: << >>  << T >>  << A >>
"Russell Shaw" <rjshaw@iprimus.com.au> schrieb im Newsbeitrag
news:3CAFD530.B55031E5@iprimus.com.au...
> Hi,
>
> What is the recommended spartan-xc2s30 variant that has 5V tolerant
> inputs and 3.3V outputs?

All Spartan-II devices are 5V tolerant without any additional components.
And they have 3.3V outputs. (If you power the IO-Banks with 3.3V, 2.5V is
also possible)

--
MfG
Falk





Article: 41762
Subject: Re: FPGA config without boot PROM???
From: tpmanakkil@iprimus.com.au (Thomas)
Date: 7 Apr 2002 05:41:51 -0700
Links: << >>  << T >>  << A >>
Is it true the CPLD's like coolrunner from Xilinx contain flash inside
which can boot by itself?..May be i miss-Interpret the information i
recieved.please
provide me the facts..By the way is my design based on Spartan2 FPGA
can be transformed to a Coolrunner without much complexity?.Which is
ecomoical? CPLD's like coolrunner or FPGA..IS there any Industrial
equvalent to Coolrunner from other chip manufactures?/..sorry.. is
this topic is drifting away.../?



"Ulf Samuelsson" <ulf@atmel.REMOVE.com> wrote in message news:<553q8.1528$tI1.4298@nntpserver.swip.net>...
> "Chris Wilkson" <cwilkson@mit.edu> skrev i meddelandet
> news:ee75da9.-1@WebX.sUN8CHnE...
> > I'm looking for an FPGA family that doesn't require a separate boot
> > PROM.  (I can't afford the board space for the second chip.)
> >
> > Does anyone have any suggestions?
> > Please respond by email as I don't regularly read this forum.
> >
> > Thanks!
> > -Chris
> 
> The AT94S Family (S for Secure) is available with
> the FPGA and Configurator in a single BGA package.
> The FPGA also contains the AVR micro, SRAM and AVR peripherals.

Article: 41763
Subject: Re: FPGA config without boot PROM???
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sun, 7 Apr 2002 16:34:53 +0200
Links: << >>  << T >>  << A >>
"Thomas" <tpmanakkil@iprimus.com.au> schrieb im Newsbeitrag
news:d72b1b1c.0204070441.1201a289@posting.google.com...
> Is it true the CPLD's like coolrunner from Xilinx contain flash inside
> which can boot by itself?..May be i miss-Interpret the information i

Right, the Coolrunners as well as the classic CPLDs 95xx(XL) have Flash to
hold their configuration, so they are active just right after power-up.

> recieved.please
> provide me the facts..By the way is my design based on Spartan2 FPGA
> can be transformed to a Coolrunner without much complexity?.Which is

;-), if you have a small design without using special features of Spartan-II
(like RAM, SRL16),then it may be possible, even without much stress.
BUT as I said, size DOES matter (didnt we knew this already?? ;-)
Just some numbers.

Coolrunner 32..512 Macrocells (means 32..512 FlipFlops plus product term
function generators)
Sparatan-II 384..4704 Logic cells (means 384..4704 FlipFlops plus 4 input
LUTs)

Got the point?

> ecomoical? CPLD's like coolrunner or FPGA..IS there any Industrial

Can you fit the design into a Coolrunner? So go for it. If not, a FPGA is
the only way. In general, FPGAs are WAY less expensive when you look at
$/FlipFlop (I know, this is not the ultimate measure).
If you would like to compare prizes, go for

www.nuhorizons.com

Just enter the part number (e.g. XCR3032XL) into the search field and see.

> equvalent to Coolrunner from other chip manufactures?/..sorry.. is

If you mean very similar in function, yes, e.g. from lattice
(www.latticesemi.com)
But you wont find a pin compatible type, since there is no standard like in
the good old days of GALs.

> this topic is drifting away.../?

No.

--
MfG
Falk





Article: 41764
Subject: Re: powerpc in virtex2pro
From: "Jan Gray" <jsgray@acm.org>
Date: Sun, 7 Apr 2002 08:14:56 -0700
Links: << >>  << T >>  << A >>
"Steve Casselman" <sc.nospam@vcc.com> wrote
> For example my patent http://www.delphion.com/details?pn=US06178494__
> suggests that it might be useful to have a part that can be inserted into
a
> pre-existing socket.

http://www.fpgacpu.org/usenet/fpgas_as_pc_coprocessors.html:
"Five times better latency and four times better bandwidth could be
achieved if FPGA vendors invent a way to directly connect their parts
to the Pentium Pro external bus, as a peer of the memory/bus
controller.  A custom, dedicated Pentium Pro interface would probably
be required, since FPGA configurable logic would be too slow and
electrically incompatible."

(4/96, 5/96 threads:
http://groups.google.com/groups?th=589c20eee24735de,
http://groups.google.com/groups?th=2946a4c24dd295ae)

Jan Gray, Gray Research LLC




Article: 41765
Subject: Re: 32 bit accumulator/comparator PWM?
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Sun, 07 Apr 2002 18:26:24 +0200
Links: << >>  << T >>  << A >>
I did a similar thing.

http://www.ibrtses.com/electronics/altera.html

http://www.ibrtses.com/electronics/project2.jpg

I use downcounters and output the carry. The whole runs
with a 100MHz clock.

No problems.The software was free, the part rather inexpensive,
especially compared with an alternative ECL approach.

Rene
-- 
Ing.Buero R.Tschaggelar  http://www.ibrtses.com



Patrick Robin wrote:

> Hi,
> 
> I am new to this field. I am a senior software engineer with some
> college experience in basic digital design from 12 years ago.
> 
> I also have experience programming AVR Atmel uC.
> 
> I am contemplating moving one of my uC design to part hardware, part
> software to increase speed. It consists in a frequency and pulse width
> adjustable square wave generator.
> 
> I would apreciate your opinion on how difficult and costly ($) would it
> be for someone like me to design a hardware (chip) with:
> 
> -a 32 bit accumulator
> -a 32 bit comparator
> -one 32 bit register (A) to store the number to be added by the
> accumulator
> -one 32 bit register (B) to store the number to compare against the
> accumulator sum (C)
> -one digtal output =1 if C>B 0 otherwise or vice versa
> 
> The accumulator should run at least at 25MHZ, preferably 50MHZ
> 
> I could probably do this with individual components but I want to
> minimize part count. Please let me know of the best way to approach
> this. I don't want to invest in costly ($1000) programmators if
> possible.
> 
> Of course if you already know of such a chip I would like to know also
> :)


Article: 41766
Subject: Re: strange RAM timing problem (VirtexE)
From: spam_hater_7@email.com (Spam Hater)
Date: Sun, 07 Apr 2002 16:41:04 GMT
Links: << >>  << T >>  << A >>

You would know better than me.  Sorry if I mislead anyone.

On Sat, 06 Apr 2002 19:16:39 -0800, Peter Alfke
<peter.alfke@xilinx.com> wrote:

>
>That statement is dead wrong !!!


Article: 41767
Subject: Re: Xilinx programmer
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Sun, 07 Apr 2002 12:48:22 -0500
Links: << >>  << T >>  << A >>
All Spartan-IIs are 5V I/O tolerant, and the device supports 5V TTL and
5V PCI.
In my case, 5V PCI support is the only reason I use it, otherwise I will
use a newer part like Spartan-IIE.
Spartan-IIE is not 5V I/O tolerant unless additional components were
placed outside of the chip.
Yesterday, I burned a Configuration PROM (First time since August of
2001.), and during the process, I used an Insight Electronics JTAG
cable, which I believe is exactly same as the schematics URL you
presented.
I know it can be hand made, but it was only $60, so I just paid for it.
        One more thing to note, you might think XC2S30's LUT density is
same as Altera's EP1K30, but Xilinx inflates gate counts far more than
Altera does.
I know, some people have said that's because Xilinx counts RAM bits as
gates, and I guess I don't like that.
For example, EP1K30's number of LEs is 1,728 which translates to 1,728
4-input LUTs and DFFs, but XC2S30's has 216 CLBs which translates to
only 864 4-input LUTs and DFFs (1 CLB has 2 Slices, and 1 Slice has 2
4-input LUTs and DFFs.).
So, to get similar number of LUTs and FFs, you should use at least
XC2S50 (384 CLBs = 1536 4-input LUTs and DFFs).
Why not just go ahead and use XC2S100?
That's going to be bigger than EP1K30, although I am not sure how cost
sensitive your application is.
I don't know how you simulate your design, but in my case, the lack of
HDL-based simulator in Altera's free tools and low cost prototype boards
pretty much turns me off using Altera's free tools seriously, although I
do sometimes synthesize my design targeting FLEX10KE to make sure my HDL
code is vendor independent.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)



Russell Shaw wrote:
> 
> Hi,
> 
> What is the recommended spartan-xc2s30 variant that has 5V tolerant
> inputs and 3.3V outputs?
> 
> Will this programmer work for it? :
> 
>   http://toolbox.xilinx.com/docsan/2_1i/data/common/jtg/fig26.htm
>   http://toolbox.xilinx.com/docsan/2_1i/data/common/jtg/jtg.htm

Article: 41768
Subject: signal delay in altera 20KE
From: "Matthew Plante" <maplante@iol.unh.edu>
Date: Sun, 7 Apr 2002 14:56:59 -0400
Links: << >>  << T >>  << A >>
Hello,

  I'm trying to shift around one of my clocks in my altera 20K200E chip.  I
have a clock coming in from a board, going into a global clock on my fpga.
I then send that clock to an output pin where it is used as a clock for an
external pattern generator, which then sends data to my fpga.:


Pattern
tx                       fpga            clk to generator
Generator
clk -----> +------------+ ------------------------> +---------- --+
                 |                   |      data from generator      |
|
                 |                   | <------------------------- |
|
                +------------+
+-------------+

So, the returned data from the pattern generator is clocked out with the tx
clock.  Well, they are a little out of phase, so I need to either delay the
data, shift the clk to the generator, or set another signal equal to the tx
clk, and then shift that derived clk.  Can anyone help me out.  I'm using
quartus, and my code is in verilog.

thanks,

--Matt
   maplante@iol.unh.edu



Article: 41769
Subject: Re: A learner of Modelsim
From: "Speedy Zero Two" <david@manorsway.NOSPAMPLEASE.freeserve.co.uk>
Date: Sun, 7 Apr 2002 22:03:16 +0100
Links: << >>  << T >>  << A >>
peeps,

you can use the synthesis directive like,

// synthesis translate_off
initial begin counter=0; end
// synthesis translate_on


hope this helps
Dave


"Alex Sherstuk" <sherstuk@iname.com> wrote in message
news:ee760df.2@WebX.sUN8CHnE...
> I am also fighting initial reset problem for the MODELSIM now.
> Looks like, before making functional simulation I have to modify VHDL
code - introducing excessive reset signals. Then, before the synthesys I
should remove those excessive signals - if there is a lack of routing
resources.
>
> Is that true?
>
> Thanks,
>    Alex



Article: 41770
Subject: Re: A learner of Modelsim
From: "Alex Sherstuk" <sherstuk@iname.com>
Date: Sun, 7 Apr 2002 13:22:27 -0800
Links: << >>  << T >>  << A >>
I am also fighting initial reset problem for the MODELSIM now.
Looks like, before making functional simulation I have to modify VHDL code - introducing excessive reset signals. Then, before the synthesys I should remove those excessive signals - if there is a lack of routing resources.

Is that true?

Thanks,
   Alex

Article: 41771
Subject: Re: signal delay in altera 20KE
From: Peter Alfke <palfke@earthlink.net>
Date: Sun, 07 Apr 2002 21:49:25 GMT
Links: << >>  << T >>  << A >>
Matthew, you did not tell us your clock frequency. If it is low enough, I see
no problem with your design the way it is. In a synchronous design using
edge-triggered flip-flops or registers, the data initiated by a certain clock
edge must arrive a little before the next clock edge. Anything else is
irrelevant

Peter Alfke
===========================
Matthew Plante wrote:

> Hello,
>
>   I'm trying to shift around one of my clocks in my altera 20K200E chip.  I
> have a clock coming in from a board, going into a global clock on my fpga.
> I then send that clock to an output pin where it is used as a clock for an
> external pattern generator, which then sends data to my fpga.:
>
> Pattern
> tx                       fpga            clk to generator
> Generator
> clk -----> +------------+ ------------------------> +---------- --+
>                  |                   |      data from generator      |
> |
>                  |                   | <------------------------- |
> |
>                 +------------+
> +-------------+
>
> So, the returned data from the pattern generator is clocked out with the tx
> clock.  Well, they are a little out of phase, so I need to either delay the
> data, shift the clk to the generator, or set another signal equal to the tx
> clk, and then shift that derived clk.  Can anyone help me out.  I'm using
> quartus, and my code is in verilog.
>
> thanks,
>
> --Matt
>    maplante@iol.unh.edu


Article: 41772
Subject: Re: signal delay in altera 20KE
From: "Matthew Plante" <maplante@iol.unh.edu>
Date: Sun, 7 Apr 2002 17:56:48 -0400
Links: << >>  << T >>  << A >>
My system is operating at 62.5 MHz.  The clock is skewed just enough so that
the sampled data is incorrect.  I've tried using Altera's PLL megafunctions,
but I haven't had any luck getting them to work.  Whenever I tried to use
the module, it gives me an error about my I/O assignment, but no useful
information.  I'm not quite sure what is wrong with it.  The clock input to
the PLL is one of the global clocks, and the output is going to the pll
clock output pin.


"Peter Alfke" <palfke@earthlink.net> wrote in message
news:3CB0BED1.A579AB53@earthlink.net...
> Matthew, you did not tell us your clock frequency. If it is low enough, I
see
> no problem with your design the way it is. In a synchronous design using
> edge-triggered flip-flops or registers, the data initiated by a certain
clock
> edge must arrive a little before the next clock edge. Anything else is
> irrelevant
>
> Peter Alfke
> ===========================
> Matthew Plante wrote:
>
> > Hello,
> >
> >   I'm trying to shift around one of my clocks in my altera 20K200E chip.
I
> > have a clock coming in from a board, going into a global clock on my
fpga.
> > I then send that clock to an output pin where it is used as a clock for
an
> > external pattern generator, which then sends data to my fpga.:
> >
> > Pattern
> > tx                       fpga            clk to generator
> > Generator
> > clk -----> +------------+ ------------------------> +---------- --+
> >                  |                   |      data from generator      |
> > |
> >                  |                   | <------------------------- |
> > |
> >                 +------------+
> > +-------------+
> >
> > So, the returned data from the pattern generator is clocked out with the
tx
> > clock.  Well, they are a little out of phase, so I need to either delay
the
> > data, shift the clk to the generator, or set another signal equal to the
tx
> > clk, and then shift that derived clk.  Can anyone help me out.  I'm
using
> > quartus, and my code is in verilog.
> >
> > thanks,
> >
> > --Matt
> >    maplante@iol.unh.edu
>



Article: 41773
Subject: Re: 32 bit accumulator/comparator PWM?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Mon, 08 Apr 2002 11:16:11 +1200
Links: << >>  << T >>  << A >>
Patrick Robin wrote:
> -a 32 bit accumulator
> -a 32 bit comparator
> -one 32 bit register (A) to store the number to be added by the
> accumulator
> -one 32 bit register (B) to store the number to compare against the
> accumulator sum (C)
> -one digtal output =1 if C>B 0 otherwise or vice versa
> 
> The accumulator should run at least at 25MHZ, preferably 50MHZ
> 
> Jim Granville wrote:
> 
> >  What is the application target Freq Band ?
> 
> 1 hz to 1MHZ  adjustable in .5 HZ steps or better and pulse width adjustable

 That's some dynamic Range :-)

 What load does this drive, and how does the phase jitter of a summing
system
affect this ? 
 I can see how a variable Accum gives a DDS style frequency, with a
precise average, but am unclear on how a fixed PWM can be derived from
this ?

-jg

Article: 41774
Subject: Modelsim-XE fails when simulating a VHDL model.
From: "Kelvin Xu Qijun" <qijun@okigrp.com.sg>
Date: Mon, 8 Apr 2002 09:27:20 +0800
Links: << >>  << T >>  << A >>
I am simulating some SAT calculators. It seems Modelsim-XE 5.3 crashes each
time when I load a design.
It seems that it's all right when I compile all the designs and testbenches.
The program just crash without any
warning.

Anybody knows what's the problem?
Anybody knows of any free-available simulation software besides ModelSim and
VSS?

Thanks.
Kelvin







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