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Messages from 41800

Article: 41800
Subject: Re: Distributed ram
From: "Ulf Samuelsson" <ulf@atmel.REMOVE.com>
Date: Mon, 8 Apr 2002 18:56:46 +0200
Links: << >>  << T >>  << A >>
"Russell Shaw" <rjshaw@iprimus.com.au> skrev i meddelandet
news:3CAEE835.362054C7@iprimus.com.au...
> Hi,
>
> I had a need for lots of 16-word ram blocks in an acex 1k30
> device. From what i can see in the data sheet, you can only
> use parts of EAB ram blocks to do that. For a spartan xc2s30,
> it says the CLB function generators can be used as distributed
> ram blocks. Is it right that acex devices can't do that?
>
> Can the spartan CLB ram blocks be used as 16-word 'pipes' for delaying
signals?

I think that you will find that this is an application where the Atmel
AT94K40 architecture fits.

It has 144 blocks of 32 x 4 DPRAM internally.
This will provide you with 36 (actually 32 due to routing constraints)
blocks of 32 x 16 DPRAMS
The SRAMs are actually there, so you do not lose any macro cells to use
them.

The RAMs are 32 deep, so if you could somehow use one 32 x 16 SRAM
instead of 2 x (16 x 16) SRAMs, then you should be fine.

In addition, there is an 8 bit SRAM block that can be varied in size between
4kx8 to 12kx8.

For fun, the AT94K has an AVR RISC micro and 20kB+4kB additional SRAM...

There is a development kit available for less than $500 including board, and
Mentor tools.

--
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.




Article: 41801
Subject: Re: Modelsim from Altera vs Modelsim from Menthors
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Mon, 08 Apr 2002 12:02:56 -0500
Links: << >>  << T >>  << A >>


Paul Baxter wrote:
> 
> 
> I believe it does have all features of the entry level Mentor offering
> EXCEPT speed has been reduced to 1/4 of the full version and probably it is
> only tailored to Altera libs.
> 
> A good alternative is ActiveHDL if you were thinking on splashing out on
> full versions.
> 
> Paul


        According to Altera's website, I believe it said ModelSim AE
runs at half of ModelSim PE.
Although if I am correct, ModelSim AE doesn't allow mixed language
designs.
However, ModelSim AE is part of their one year software subscription
program, so it is much cheaper than the full version though.




Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 41802
Subject: Re: XST Synthesis tool
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Mon, 08 Apr 2002 12:10:53 -0500
Links: << >>  << T >>  << A >>
I don't believe a synthesis option you are talking about even exists.
Internal tri-state buffers are always available in XST at least when
FPGAs are being targeted, and when I experimented with it, XST
synthesized internal tri-states fine.
However, you might get some warnings that multiple sources exist for
certain internal tri-state lines though.
When I simulated the design, the design functioned correctly, so it
looks like XST handled it correctly.
It looks like you are using VHDL, but in my case I used Verilog.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)



gianzi wrote:
> 
> Hi all,
> I am using ISE 4.1 and thought to try XST synthesis. While this tool is
> working fine with simple designs, It gives an error when i try to use  a
> tri-state.
> The message I get is :  ERROR:Xst:742 - Unexpected 'Z' expression found.
>                                     ERROR:Xst:746 - Failed to build equation
> for signal <....<7>> in unit <....>.
> Anyone can tell if there is a way to configure XST to be able to synthesize
> tri-states too?

Article: 41803
Subject: Re: Handel-C useless.. Move to SystemC
From: "Domagoj" <domagoj@engineer.com>
Date: Mon, 8 Apr 2002 19:32:26 +0200
Links: << >>  << T >>  << A >>
hi !

I'm not familiar with these C-like languages for hardware description, but
I'd like to learn more about it.

what's the difference between Handel-C, System-C and Spec-C ? any
free/evaluation tools available for each of them ? where are specman's E and
Vera in comparison with other mentioned languages ?

thx

Domagoj
domagoj@engineer.com


"Jeanan Del" <go_stock_boy@yahoo.com> wrote in message
news:5e59ca1f.0203261002.5fb42c34@posting.google.com...
> When is Celoxica going to kill of this useless proprietary Handel-C
> language in favor of moving to the industry standard SystemC ?? I've
> done a couple of experiments with DK1 3.0 and the language is painful
> to use, doesn't leverage C++ and once I do soemthing in Handel-C, I
> can't use with any other design or verification tools, like I can with
> SystemC.  There's a germ of value in Celoxica stuff but not while it
> is encumbered by a dead-end proprietary language.
>
> When are these guys going to get real ??



Article: 41804
Subject: How to INIT ROM in VHDL for WebPack/ModelSimXE?
From: Chip Fox <chip.f@ix.netcom.com>
Date: Mon, 08 Apr 2002 17:54:09 GMT
Links: << >>  << T >>  << A >>
Hi,

Can anyone tells me why the VHDL code below appears to synthesize OK under
Xilinx WebPack and load into ModelSimXE and simulate OK, except that the ROM
data output is always zero?

I know there's probably a lot of monkey-motion in this code.  But I already
tried the simple versions, and out of desparation, I tried adapting something
out of a Xilinx Q&A item.

Humbly,
Chip
--------------------------------------------------------------------------------

library IEEE;
library unisim; 
use IEEE.std_logic_1164.all;
use unisim.vcomponents.all;

entity rom_16x1 is 
generic (init_val : string := "5A5A" ); 
port (O : out std_logic; 
A3, A2, A1, A0: in std_logic); 
end rom_16x1; 

architecture xilinx of rom_16x1 is 

attribute INIT: string; 
attribute INIT of u1 : label is init_val; 

component ROM16X1 is port (O : out std_logic; 
A0: in std_logic; 
A1: in std_logic; 
A2: in std_logic; 
A3: in std_logic); 
end component; 

begin 

U1 : ROM16X1 port map (O => O, A0 => A0, A1 => A1, A2 => A2, A3 => A3); 

end xilinx; 

library IEEE;
library unisim;  
use IEEE.std_logic_1164.all;
use unisim.vcomponents.all; 
--use IEEE.std_logic_unsigned.all; 

entity mem is 
port (dout: out std_logic; 
a: in std_logic_vector(3 downto 0);
clk: in std_logic); 
end mem; 

architecture xilinx of mem is 
signal O: std_logic;
component rom_16x1 
generic (init_val: string := "5a5a"); 
port (O : out std_logic; 
A3, A2, A1, A0 : in std_logic); 
end component; 

begin 

U0 : rom_16x1 generic map ("5a5a") 
port map (O => O, A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3)); 
 
process (clk)
begin
	if clk'event and clk='1' then
		dout <= O;
	end if;
end process;
end xilinx;

Article: 41805
Subject: Re: powerpc in virtex2pro
From: "Steve Casselman" <sc.nospam@vcc.com>
Date: Mon, 08 Apr 2002 18:06:22 GMT
Links: << >>  << T >>  << A >>
Hey Jan. You'll notice that even though the patent was issued in 2000 it was
submitted 11/96. Of course my note book that has my initial write up is
dated dec 17, 1994...

Steve Casselman


"Jan Gray" <jsgray@acm.org> wrote in message
news:a8pnvu$e89$1@slb4.atl.mindspring.net...
> "Steve Casselman" <sc.nospam@vcc.com> wrote
> > For example my patent http://www.delphion.com/details?pn=US06178494__
> > suggests that it might be useful to have a part that can be inserted
into
> a
> > pre-existing socket.
>
> http://www.fpgacpu.org/usenet/fpgas_as_pc_coprocessors.html:
> "Five times better latency and four times better bandwidth could be
> achieved if FPGA vendors invent a way to directly connect their parts
> to the Pentium Pro external bus, as a peer of the memory/bus
> controller.  A custom, dedicated Pentium Pro interface would probably
> be required, since FPGA configurable logic would be too slow and
> electrically incompatible."
>
> (4/96, 5/96 threads:
> http://groups.google.com/groups?th=589c20eee24735de,
> http://groups.google.com/groups?th=2946a4c24dd295ae)
>
> Jan Gray, Gray Research LLC
>
>
>



Article: 41806
Subject: Re: hand placement
From: "Steve Casselman" <sc.nospam@vcc.com>
Date: Mon, 08 Apr 2002 18:15:09 GMT
Links: << >>  << T >>  << A >>
I hate to keep talking about my patents but... The first patent
http://www.delphion.com/details?pn10=US05684980
is about that. I call it the runtime generation patent. It is really an
exercise on how to put together and program a bunch of field programmable
gates to be a computer system.

Steve Casselman




"Jim Granville" <jim.granville@designtools.co.nz> wrote in message
news:3CACFBB3.1C73@designtools.co.nz...
> Steve Casselman wrote:
> >
> > I took the cost function put it in hardware and ran the database past it
> > several times. The cost function accounted for 30% of the placer
> > performance. That part of the placer took about 1/3 of a xc4010. From my
> > analysis I concluded that ppr could be speed up by 10x and would take
about
> > 50K gates. This holds to the normal 90/10 rule. Of course Xilinx was
moving
> > over to par at the time and they concluded that they didn't need the
> > speedup. After spending a lot of time with the code I'm convinced that
P&R
> > is a sure bet for acceleration. Now with the PPC and Virtex II I'm sure
that
> > over all speedups of 8-10x would be pretty straight forward. I estimate
> > about 2 man years of work and a design with 4-8 gig on board would do
it.
> >
> > Steve
>
>  If I have this right, you are talking about using a VirtexPRO as an
> engine to route VirtexPRO (et al) ?.
>
> This becomes the silicon equivalent of the 'compiler bootstrap' :-)
>
> Maybe it's also a problem, the 'solution of 4 PPCs' is looking for ?
>
> Xilinx could sell route-boxes, and it would make a pretty impressive
> product demonstrator...
>
> -jg



Article: 41807
Subject: Re: XST Synthesis tool
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 8 Apr 2002 20:34:27 +0200
Links: << >>  << T >>  << A >>
"gianzi" <zisis@mhl.tuc.gr> schrieb im Newsbeitrag
news:a8s6kj$7al$1@ulysses.noc.ntua.gr...
> Hi all,
> I am using ISE 4.1 and thought to try XST synthesis. While this tool is
> working fine with simple designs, It gives an error when i try to use  a
> tri-state.
> The message I get is :  ERROR:Xst:742 - Unexpected 'Z' expression found.
>                                     ERROR:Xst:746 - Failed to build
equation
> for signal <....<7>> in unit <....>.
> Anyone can tell if there is a way to configure XST to be able to
synthesize
> tri-states too?

Sure. Do you have the standard libraries included?

library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--
MfG
Falk




Article: 41808
Subject: Re: Xilinx programmer
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 8 Apr 2002 20:37:52 +0200
Links: << >>  << T >>  << A >>
"Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> schrieb
im Newsbeitrag news:a8rgu0$rep$1@newsreader.mailgate.org...

> No, I don't own an oscilloscope, and I am poor, so I cannot afford one.

And YOU call $60 for a simple download cable cheap??

--
MfG
Falk





Article: 41809
Subject: Re: How to probe internal signals from Xilinx netlist?
From: "Steve Casselman" <sc.nospam@vcc.com>
Date: Mon, 08 Apr 2002 18:45:33 GMT
Links: << >>  << T >>  << A >>
You put a block ram into your design (see app notes)  then you run the
signals you want to look at into the ram. into it. If  the software tries to
get rid of it (because there are no out puts) just wrap one of the outputs
into one in the inputs. The idea here is that there is no synthesis to be
done on a block ram so the names will stay the same each time you recompile
the design. Block rams are usually closer to your design than the I/Os so I
would think they would have less impact on the over all timings.

Steve Casselman



"freny" <wacky_me@rediffmail.com> wrote in message
news:446b88f2.0204062334.17cd5957@posting.google.com...
> > I think that chipscope gets inserted at the edif level. Why is it that
you
> > can't simulate it? Why not hook up the signals you want to look at and
run
> > them into a block ram?
>
> hey,
>
> how do u hook up the signals into the block ram
> tell me the actuall process



Article: 41810
Subject: Re: How to probe internal signals from Xilinx netlist?
From: "Steve Casselman" <sc.nospam@vcc.com>
Date: Mon, 08 Apr 2002 18:55:18 GMT
Links: << >>  << T >>  << A >>
I'm not sure if it still works this way (for VHDL) but in the past I/O had
to brought up the top of the hierarchy or you have to instantiate each I/O.
It seems that just plopping down a wide block ram would be less work (and
less messy) than instantiating each I/O. Unless of course you have a very
flat small design that makes it convenient to bring the I/O out at the top
level.

Steve Casselman


"Kelvin Xu Qijun" <qijun@okigrp.com.sg> wrote in message
news:3cb16efa@news.starhub.net.sg...
> block RAM would be even more messy, In the past i prefer to pull out the
> signals to
> primary output and try to make the code easy to comment out these redudant
> lines...
> Still feel this method very messy...
>
> --
> Best Regards,
> -----------------------------------------------------------------
> Xu Qijun
> Engineer
> OKI Techno Centre (S) Pte Ltd
> Tel: 770-7049 Fax: 779-1621
> Email: qijun@okigrp.com.sg
>
> "freny" <wacky_me@rediffmail.com> wrote in message
> news:446b88f2.0204062334.17cd5957@posting.google.com...
> > > I think that chipscope gets inserted at the edif level. Why is it that
> you
> > > can't simulate it? Why not hook up the signals you want to look at and
> run
> > > them into a block ram?
> >
> > hey,
> >
> > how do u hook up the signals into the block ram
> > tell me the actuall process
>
>



Article: 41811
Subject: W2000 HotFix Xilinx compatible?
From: "Steve" <pair@noid.com>
Date: Mon, 08 Apr 2002 19:15:17 GMT
Links: << >>  << T >>  << A >>
I just installed my latest W2000 Hotfix this morning and now I've had 2
Xilinx crashes!
The first was in constraints editor, the second was in timing analyzer.
Both came up with a FATAL_ERROR pop-up and the ap was gone.

I've seen bugs in these tools before, but the crashing is new ... today!

Anyone else see similar results?

I notice Microsoft left something in the Add/Remove programs area, so I'll
try backing out
the Hotfix ... wish me luck!


--
Steve




Article: 41812
Subject: Re: Xilinx programmer
From: "Steve Casselman" <sc.nospam@vcc.com>
Date: Mon, 08 Apr 2002 19:28:42 GMT
Links: << >>  << T >>  << A >>
haha can't resist.. oscilloscopes are for weenies I just never make a
mistake.
Really tools like simulation are there because they are useful during
development. You need the right tool for the right job some times its a
scope and sometimes it a simulator.

Steve



> I use an oscilloscope. Simulation? That's for weenies;)





Article: 41813
Subject: Re: W2000 HotFix Xilinx compatible?
From: "Steve" <pair@noid.com>
Date: Mon, 08 Apr 2002 19:30:19 GMT
Links: << >>  << T >>  << A >>
still fails
maybe overwrote dll?
reinstall tools?

forgot to mention: if you have any comments, please reply through this
        news group ... thanks

--
Steve
_______________________________________________________
"Steve" <pair@noid.com> wrote in message
news:9%ls8.34377$f4.3056085@news3.calgary.shaw.ca...
> I just installed my latest W2000 Hotfix this morning and now I've had 2
> Xilinx crashes!
> The first was in constraints editor, the second was in timing analyzer.
> Both came up with a FATAL_ERROR pop-up and the ap was gone.
>
> I've seen bugs in these tools before, but the crashing is new ... today!
>
> Anyone else see similar results?
>
> I notice Microsoft left something in the Add/Remove programs area, so I'll
> try backing out
> the Hotfix ... wish me luck!
>
>
> --
> Steve
>
>
>



Article: 41814
Subject: Re: 32 bit accumulator/comparator PWM?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 09 Apr 2002 07:36:49 +1200
Links: << >>  << T >>  << A >>
Patrick Robin wrote:
> 
> Jim Granville wrote:
> 
<snip>
> > That's correct for freq, but to apply a PWM compare to an accumulator
> > based
> > Freq generator is where I cannot see stable PWM out values.
> > Do you actually have this working in SW ?
> 
> Yes and cycle-cycle variation in on time-off time doesn't exceed the step size: 2% for
> 1MHZ frequency  and 50MHZ sample rate
> 
<paste>
> > I think you can get an 'energy average' by applying any compare value to
> > the accumulator,
> > but because the compare is fixed, and the accum adds by varying amounts
> > then cycle-cycle
> > errors can be very large.

 The 'mental example' I was using, was for a high % of Clock rate (
large Adder ),
which is not correct for this example.
 At a 50:1 ratio, you are correct, the short term jitter in PWM Slice
level is 2%
The frequency precison is better then this.


<snip
> > If you mean Sine Wave out, then Direct Digital Synthesis can do that,
> > with a Sine
> > ROM. Look for Direct Digital Synthesis devices from Analog Devices etc
> 
> It needs to produce a square wave only. I initially tried to find a DDS chip with a
> programmable wave table but couldn't find any. I believe that would work in my case
> since I could just load the square wave with needed duty cycle in the table and if the
> sample rate was fast enough, it would come out with correct precision.
> 
> But I couldn't find one so I decided to use the same principle but without the wave
> table since in a square wave the only information we are storing is a single transition
> point from on to off and that can be figured out by comparing the table pointer derived
> from the accumulator to a number:
> 
> if (accumulator > transition point )  put out 0
> else put out 1
> 
> The rest of the algorithm is identical to DDS as far as I can tell. ie, the frequency is
> defined by how fast the accumulator passes  FFFFFFFF and overflows and a new cycle
> starts.
> 
> Your method is new to me and I will have to look more into it if it allows greater
> precision in the same PLD chip.

 There are two precisions, Frequency and PWM. 
 If you tolerate 2% on PWM, then you do not need a 32 bit Latch/compare, 
and this can work off only the MSB's of the Adder.
 Even a single 8 bits MSB compare / 8 bit latch will define PWM to 0.4%, 
and have STJ 2% at 50:1, improveing to the define limit above 256:1

 Shortening the adder ( eg 24 bits ) will increase the speed, and reduce
the
resource in a PLD.

 It's an interesting problem, I will think some more about a 'mixed
scheme' 

 -jg

Article: 41815
Subject: Re: Xilinx programmer
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Mon, 08 Apr 2002 14:41:48 -0500
Links: << >>  << T >>  << A >>
Falk Brunner wrote:
> 
> "Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> schrieb
> im Newsbeitrag news:a8rgu0$rep$1@newsreader.mailgate.org...
> 
> > No, I don't own an oscilloscope, and I am poor, so I cannot afford one.
> 
> And YOU call $60 for a simple download cable cheap??
> 
> --
> MfG
> Falk


        Well, doesn't a 500MHz oscilloscope with 4-channels cost $8,000
to $10,000?
I can buy a small car for that much of money although I rather buy an
oscilloscope than a small car.
I always hear horror stories of people doing their own download cable
having problems.
I recently saw a posting by a guy who made his own Altera MasterBlaster
MV compatible cable having lots of problems.
It probably doesn't cost any more than $10 (maybe less than $5) to make
a Xilinx JTAG cable, but I rather not spend the time and effort on
making one because I have better ways to spend my time. (i.e.,
Developing my PCI IP core.)



Kevin Brace (In general, don't respond to me directly, and 
respond within the newsgroup.)

Article: 41816
Subject: Low-cost FPGA + processor board?
From: "Frank de Groot" <franciad@online.no>
Date: Mon, 08 Apr 2002 19:46:16 GMT
Links: << >>  << T >>  << A >>
Hi guru's,

I need an off-the-shelf PCI PC addin card that I can use to do some
specialized coprocessing.
BUT that board should not be move expensive than 500$.
Am I unrealistic? If not, could you give me a link, a brand name, a type
number?
Just the simplest FPGA and a processor, like a transputer or an ARM will do,
better would be an 80x86 processor.

Any other solutions? I need to do pattern matching and quite complex pattern
generation.
I might be able to do that without a CPU on the FPGA board maybe?
Is there another solution (like SPLD, CPLD, CSOS, TTL array) that may be
sufficient and would be cheaper? Should I opt for a CPU-only board instead?
Any websites that have specs & prices of coprocessor boards, FPGA boards?

Thanks very much for your help.

Frank de Groot
Oslo, Norway



Article: 41817
Subject: Re: XST Synthesis tool
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Mon, 8 Apr 2002 21:09:10 +0100
Links: << >>  << T >>  << A >>
Falk Brunner wrote

> Sure. Do you have the standard libraries included?
>
> library ieee;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;

Shame on you :-)  These are not standard libs, despite the names.

 library IEEE;
     use IEEE.std_logic_1164.all;
     use IEEE.numeric_std.all;




Article: 41818
Subject: Re: Modelsim from Altera vs Modelsim from Menthors
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 08 Apr 2002 13:45:46 -0700
Links: << >>  << T >>  << A >>
Itsaso Zuazua wrote:

> What canīt I do with Modelsim from
> Altera that I could do, with the complete Modelsim?

1. Run the linux version.
2. Waveform compares 
3. Code coverage functions.


Others have reported speed differences.
I did not notice any dramatic difference, but I did not 
measure it either.

   -- Mike Treseler

Article: 41819
Subject: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
From: "al" <a-ng7@ti.com>
Date: Mon, 8 Apr 2002 16:17:07 -0500
Links: << >>  << T >>  << A >>
We were using 3.1i and works fairly stable with no major problems. Last
week, we loaded up the 4.1i and decided to give it a try. We used the same
set of VHDL design files, UCF constraint and batch file. At first, tool
seems working fine -- we are able to save compile time by about 40% and all
timing constraints are meet. Well, not so happy yet -- the output binary
doesn't not work in our hardware, seems like there is some sort of timing
problem somewhere. We called up xilix hotline, this support guy by the name
of Justin have no idea of what he is talking about -- keep telling me to do
a post route timing simulation on my 1.6 million gate design. Anyway, bad
tool + bad support = unhappy customer.



Article: 41820
Subject: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 08 Apr 2002 14:32:24 -0700
Links: << >>  << T >>  << A >>
al,

Would you please provide me with the Case Number?

Thanks,

Austin

al wrote:

> We were using 3.1i and works fairly stable with no major problems. Last
> week, we loaded up the 4.1i and decided to give it a try. We used the same
> set of VHDL design files, UCF constraint and batch file. At first, tool
> seems working fine -- we are able to save compile time by about 40% and all
> timing constraints are meet. Well, not so happy yet -- the output binary
> doesn't not work in our hardware, seems like there is some sort of timing
> problem somewhere. We called up xilix hotline, this support guy by the name
> of Justin have no idea of what he is talking about -- keep telling me to do
> a post route timing simulation on my 1.6 million gate design. Anyway, bad
> tool + bad support = unhappy customer.


Article: 41821
Subject: Re: XST Synthesis tool
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 08 Apr 2002 14:36:32 -0700
Links: << >>  << T >>  << A >>
Falk Brunner wrote:

> Sure. Do you have the standard libraries included?
> 
> library ieee;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;

Those are the "standard" Synopsis libraries.
Some might prefer the standard IEEE libraries:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;



   -- Mike Treseler

Article: 41822
Subject: Re: XST Synthesis tool
From: Kamal Patel <kamal.patel@xilinx.com>
Date: Mon, 08 Apr 2002 15:47:03 -0600
Links: << >>  << T >>  << A >>
Gianzi,

Answer Record 12318 may help resolve the issue.
http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=12318

I hope this helps.

Regards,
Kamal

gianzi wrote:

> Hi all,
> I am using ISE 4.1 and thought to try XST synthesis. While this tool is
> working fine with simple designs, It gives an error when i try to use  a
> tri-state.
> The message I get is :  ERROR:Xst:742 - Unexpected 'Z' expression found.
>                                     ERROR:Xst:746 - Failed to build equation
> for signal <....<7>> in unit <....>.
> Anyone can tell if there is a way to configure XST to be able to synthesize
> tri-states too?
> 
> 
> 


Article: 41823
Subject: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
From: "al" <a-ng7@ti.com>
Date: Mon, 8 Apr 2002 16:54:43 -0500
Links: << >>  << T >>  << A >>
I don't have one -- was too upset and hang up the phone quickly. Likely to
go back 3.1i for now.

"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:3CB20C68.C8A3EEB2@xilinx.com...
> al,
>
> Would you please provide me with the Case Number?
>
> Thanks,
>
> Austin
>
> al wrote:
>
> > We were using 3.1i and works fairly stable with no major problems. Last
> > week, we loaded up the 4.1i and decided to give it a try. We used the
same
> > set of VHDL design files, UCF constraint and batch file. At first, tool
> > seems working fine -- we are able to save compile time by about 40% and
all
> > timing constraints are meet. Well, not so happy yet -- the output binary
> > doesn't not work in our hardware, seems like there is some sort of
timing
> > problem somewhere. We called up xilix hotline, this support guy by the
name
> > of Justin have no idea of what he is talking about -- keep telling me to
do
> > a post route timing simulation on my 1.6 million gate design. Anyway,
bad
> > tool + bad support = unhappy customer.
>



Article: 41824
Subject: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 08 Apr 2002 15:44:58 -0700
Links: << >>  << T >>  << A >>



al,

I apologize for any difficulties you may have had.  Next time, get the case
number, and have some patience.  The Global Services Group gets excellent
ratings for their work, and our customer satisfaction surveys do not point to
any shortcomings like you described.  If for any reason you are dissatisfied
with the level of service you are receiving, with the case number Peter or I can
find out what might have gone wrong, and improve the process.  There is always
room for improvement.  That is why we spend the time to correspond on this
newsgroup.

The world logic market is big enough that we are but a small player.  We can not
ignore the customer, nor is it in our culture to do so.  The first Xilinx shared
value is "Customer focus."

Besides the above corporate/employee value, Xilinx is committed to a positive
customer experience:  after all, you use our parts that provide the revenue for
all of our paychecks here.  It makes no sense what so ever to provide anything
but an excellent world class level of service.

The faster your design works, and gets to market, the more successful you are.
The more succesful you are, the more succesful Xilinx becomes.

Austin


al wrote:

> I don't have one -- was too upset and hang up the phone quickly. Likely to
> go back 3.1i for now.
>
> "Austin Lesea" <austin.lesea@xilinx.com> wrote in message
> news:3CB20C68.C8A3EEB2@xilinx.com...
> > al,
> >
> > Would you please provide me with the Case Number?
> >
> > Thanks,
> >
> > Austin
> >
> > al wrote:
> >
> > > We were using 3.1i and works fairly stable with no major problems. Last
> > > week, we loaded up the 4.1i and decided to give it a try. We used the
> same
> > > set of VHDL design files, UCF constraint and batch file. At first, tool
> > > seems working fine -- we are able to save compile time by about 40% and
> all
> > > timing constraints are meet. Well, not so happy yet -- the output binary
> > > doesn't not work in our hardware, seems like there is some sort of
> timing
> > > problem somewhere. We called up xilix hotline, this support guy by the
> name
> > > of Justin have no idea of what he is talking about -- keep telling me to
> do
> > > a post route timing simulation on my 1.6 million gate design. Anyway,
> bad
> > > tool + bad support = unhappy customer.
> >






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