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Messages from 42050

Article: 42050
Subject: Xilinx JTAG C Source
From: kevin@ehansen.com (Kevin Hansen)
Date: 13 Apr 2002 19:49:10 -0700
Links: << >>  << T >>  << A >>
A few months ago I downloaded some JTAG-programming C source code, from the 
Xilinx site, that could be modified for my application. I have misplaced 
the files and am looking for them again, but I haven't been able to find 
them. Can anyone point me to where they are?

Thank you,
Kevin Hansen

Article: 42051
Subject: Re: prototyping an ASIC
From: "John E. Derrick" <john-derrick@austin.rr.com>
Date: Sun, 14 Apr 2002 03:41:37 GMT
Links: << >>  << T >>  << A >>
Gil:

If your final target is a real ASIC technology I'd synthesize to that
concurrent with the FPGA work.  There are a lot of reasons, but in essence
you'll want to keep the focus on the final product.  The actual capacity
that you can map onto an FPGA is somewhat dependent on the logic type.  I'd
suggest that a Virtex 1600 is only worth a couple hundred gates (at most)
compared to an ASIC.  (Depends greatly on amount of register files, SRAMs,
etc..)  The good/bad news is that there are some very large FPGAs
available/they are very expensive.  I was quoted a price of over $5000 each
on a Virtex-E 2600 or Virtex-3200 (I don't remember which).

If you want contact me on my e-mail.
John


"Gil Herbeck" <gil@radix20.com> wrote in message
news:3CB6792B.3070409@radix20.com...
> Thanks.  It is starting to look like the performance is going to
> be a problem.  What is your sense regarding capacity?  (I'm using
> the TSMC 0.13um process, but I think I can correlate to your
> process.)  Can you comment on the comparison of your ASIC gate
> count (or square mm) to your FPGA implementation?
>
> What I'm trying to get a feel for is conversion of ASIC "gates"
> to FPGA "resources".  What was the size of the ASIC that corresponds
> to your 25-33MHz Virtex-E 1600?
>
> Gil
>
>
> John E. Derrick wrote:
>
> > First I must say I work at an IP Development company (Parthus
Technologies).
> >
> > With that said, my group develops hardware-based acceleration products
like
> > Hardware-based Java JIT compilers, Hardware based decompilers, and
various
> > other things.  I say that because you need to know what type of logic we
> > develop to guage how the FPGA speeds are running.  These designs run
> > comfortably at 200MHz in Low-Power TSMC 0.18um process.  In a Virtex-E
1600
> > they easily achieve 25MHz (with nominal tuning I'd say 33MHz).  To say
the
> > least you're not going to break any speed records here.  The
Hardware-based
> > acceleration products are called MachStream.
> >
> > We have a development board that includes an ARM9-based SoC (
InfoStream )
> > that is interfaced through the memory bus to the Virtex.  A serial cable
is
> > included for comunication to a PC.  You can read about InfoStream and
> > MachStream at http://www.parthus.com .  Though it is not generally sold
as a
> > development platform, if you would like more information about the board
and
> > other IP development efforts you'll want to contact me at work.  mailto:
> > john.derrick@parthus.com
> >
> > Thanks,
> > John Derrick
> >
> >
> > "Gil Herbeck" <gil@radix20.com> wrote in message
> > news:3CB61C7B.700@radix20.com...
> >
> >>I need to prototype an ASIC design and am looking for
> >>advice on type of FPGA and on FPGA board as well.
> >>
> >>The board needs to have an ARM9, external memory, an
> >>interface to a PC (serial is ok), the FPGA (or ASIC),
> >>and a header to plug in a daughter card with some pins
> >>routed to the FPGA.
> >>
> >>The ASIC will have between 100K and 500K ASIC Logic
> >>Gates.  It will run at about 150 MHz.  It needs about
> >>200 KB of internal RAM.  And it will have a lot of
> >>multipliers.  There will probably be some pipelining
> >>in the ASIC to meet speed - and probably deeper pipes
> >>in the FPGA.  We want to match the FPGA to the ASIC
> >>as closely as possible.
> >>
> >>I think the key factors in FPGA selection are:
> >>- Capacity.  We want to fit in one FPGA.
> >>- Performance.  We want to run at speed.
> >>- "ASIC-like" synthesis library (see below)?
> >>- Availability of board described above.
> >>
> >>"ASIC-like" synthesis library...  The datapath
> >>content on the ASIC may force us to use one of the
> >>datapath synthesis tools.  These tools don't support
> >>FPGA architectures directly.  I've heard that since
> >>the Actel architecture is "fine-grain" that it works
> >>best for these types of designs.
> >>
> >>Any advice will be much appreciated.
> >>
> >>Thanks,
> >>Gil
> >>
> >>
> >
> >
>



Article: 42052
Subject: Odd problem shows on post XST/translate simulation
From: Jon Schneider <jschneider@cix.ceeowe.ewekay>
Date: Sun, 14 Apr 2002 09:18:42 +0100
Links: << >>  << T >>  << A >>
I have a very simple piece of functionality that is failing. I had
simulated the complicated stuff on the PnR model but not this.

The XC2S30 outputs a magic number on udata when the micro reads from
register 0. It then knows configuration is complete.

reg [7:0] udata_reg;
   always @(uadr)
    case (uadr)
       0: udata_reg = 8'ha1; // a magic number
       .
       .
     endcase

   assign udata = uadr<=3 && ucs ? udata_reg : 8'bz; // This is the real
bidir output

which is fine but read on.

There are also writeable registers

reg [31:0] config;

  always @(negedge ucs)
    case (uadr)
      4: config [7:0] = udata;
      5: config [15:8] = udata;
 	.
	.
  endcase

Iff I connect my flashing lights to a config register...

output [5:0] led;
.
.
.
assign led = config[31:26];

I no longer get that A1 out when reading register 0 (as noticed in
real-life first). In fact a post-translate simulation shows that
udata_reg is X when it should be A1. Latest Webpack. Any ideas ?

Jon

Article: 42053
Subject: Re: Xilinx JTAG C Source
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sun, 14 Apr 2002 11:02:05 +0200
Links: << >>  << T >>  << A >>
"Kevin Hansen" <kevin@ehansen.com> schrieb im Newsbeitrag
news:91EFCE8B5kevinehansen@216.227.56.89...
> A few months ago I downloaded some JTAG-programming C source code, from
the
> Xilinx site, that could be modified for my application. I have misplaced
> the files and am looking for them again, but I haven't been able to find
> them. Can anyone point me to where they are?

Look for xapp58

--
MfG
Falk





Article: 42054
Subject: Re: FPGA eval/dev boards with *serial* interface?
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sun, 14 Apr 2002 11:23:28 +0200
Links: << >>  << T >>  << A >>
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag
news:3CB7AE4F.6E009C80@andraka.com...
> If you can find one, the old xchecker cable is serial.  I don't
> think it is supported by the 4.x software though.  Probably the
> best solution is to run out to your local computer shop and buy
> one of those $15 parallel port boards and plug it into your
> system.

There is also a USB version of the Multilinx cable.

--
MfG
Falk





Article: 42055
Subject: Re: DLL property control in UCF
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sun, 14 Apr 2002 11:41:05 +0200
Links: << >>  << T >>  << A >>
"Norman Yang" <norman@zh.t2-design.com> schrieb im Newsbeitrag
news:a98pf7$5b6$1@news.cz.js.cn...
> Hello everyone:
> I meet a problem in controlling VertexE DLL property in UCF file. I don't
> know how to control the  Clock Divide Property of DLL in UCF. XILINX

INST my_dll_inst_name clkdv_divide=8;        # divide by 8

See also Xilinx Constaints guide, chapter C.

--
MfG
Falk





Article: 42056
Subject: Re: FPGA config without boot PROM???
From: "steve synakowski" <srs@twcny.rr.com>
Date: Sun, 14 Apr 2002 14:27:49 GMT
Links: << >>  << T >>  << A >>
The coolrunner and most CPLD's/PALs/GALs don't need to boot up. They are
just programmed with the connections required using some type of EEPROM or
FLASH cells. I haven't noticed FPGA's that don't need boot PROMs  but I
haven't had the need to look yet, so I could be wrong.
If the design will fit is the question. I see that CPLD's seem to have fewer
gates than FPGA's, so if it is complex, it might not fit into a CPLD.
Steve
"Thomas" <tpmanakkil@iprimus.com.au> wrote in message
news:d72b1b1c.0204070441.1201a289@posting.google.com...
> Is it true the CPLD's like coolrunner from Xilinx contain flash inside
> which can boot by itself?..May be i miss-Interpret the information i
> recieved.please
> provide me the facts..By the way is my design based on Spartan2 FPGA
> can be transformed to a Coolrunner without much complexity?.Which is
> ecomoical? CPLD's like coolrunner or FPGA..IS there any Industrial
> equvalent to Coolrunner from other chip manufactures?/..sorry.. is
> this topic is drifting away.../?
>
>
>
> "Ulf Samuelsson" <ulf@atmel.REMOVE.com> wrote in message
news:<553q8.1528$tI1.4298@nntpserver.swip.net>...
> > "Chris Wilkson" <cwilkson@mit.edu> skrev i meddelandet
> > news:ee75da9.-1@WebX.sUN8CHnE...
> > > I'm looking for an FPGA family that doesn't require a separate boot
> > > PROM.  (I can't afford the board space for the second chip.)
> > >
> > > Does anyone have any suggestions?
> > > Please respond by email as I don't regularly read this forum.
> > >
> > > Thanks!
> > > -Chris
> >
> > The AT94S Family (S for Secure) is available with
> > the FPGA and Configurator in a single BGA package.
> > The FPGA also contains the AVR micro, SRAM and AVR peripherals.



Article: 42057
Subject: Re: FPGA config without boot PROM???
From: "Gregory C. Read" <readgc@xxxhotmail.com>
Date: Sun, 14 Apr 2002 15:05:35 GMT
Links: << >>  << T >>  << A >>
Actel et al, make anti-fuse FPGA's that are permanently programmed and do
not use an external ROM nor require a boot up.

--
Greg
readgc@xxxhotmail.com
(Remove the 'xxx' to send Email)


"steve synakowski" <srs@twcny.rr.com> wrote in message
news:Flgu8.127058$GF1.16205589@typhoon.nyroc.rr.com...
> The coolrunner and most CPLD's/PALs/GALs don't need to boot up. They are
> just programmed with the connections required using some type of EEPROM or
> FLASH cells. I haven't noticed FPGA's that don't need boot PROMs  but I
> haven't had the need to look yet, so I could be wrong.
> If the design will fit is the question. I see that CPLD's seem to have
fewer
> gates than FPGA's, so if it is complex, it might not fit into a CPLD.
> Steve



Article: 42058
Subject: Re: Odd problem shows on post XST/translate simulation
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Sun, 14 Apr 2002 16:04:07 -0500
Links: << >>  << T >>  << A >>
I don't usually use a case statement in combinational parts, so I am not
sure, but I heard that if you don't define all the possible outcomes in
a case statement, what can happen is that the synthesis tool might infer
a latch secretly.
I am sure someone else who is more familiar with this issue can explain
better than what I can, so hopefully, someone else can clarify what I am
saying.
To prevent a secret inference of a latch, you should define all the
possible outcomes, including a don't care case.

default: begin
     udata_reg <= 8'hxx;

end



You might also want to select "Full-Parallel" for Case Implementation
Style option. (Synthesize -> Properties -> Synthesis Options -> Case
Implementation Style)
        Another possibility might be that I have seen XST somehow
screwing up synthesis when "Complex Clock Enable Extraction" option is
checked.
You may want to uncheck that.
A while ago, when I first fired up my own PCI IP core for the first
time, some parts of it worked fine, but the other parts didn't, and
crashed the computer immediately when I accessed that part.
Even after doing extensive RTL simulation, somehow the problem wasn't
going away, and I was getting desperate.
I found a Xilinx application note that explained how to do a post P&R
simulation, so I tried that, and yes, when I accessed the part that
wasn't working, some of the control signals were going undefined.
I turned off bunch of synthesis options, and the problem went away, and
the PCI card no longer crashed the computer.
Later I learned that "Complex Clock Enable Extraction" was causing the
problem, but lately, I haven't seen any problems even when the option is
turned on, but that can be because of architecture changes I made.
Anyhow, ever since that bad experience that cost me two weeks to figure
it out, I always do a post P&R simulation before burning a Configuration
PROM, but I have to admit, this type of problem can be caught by doing a
post translate (gate level) simulation.
However, an option to do post translate simulation wasn't available in
WebPACK ISE 3.3WP8.0, so all I could do was a post P&R simulation back
then.
Regardless, I think it is not a practice to burn a Configuration PROM,
and fire it up to see what happens without doing an RTL and at least a
post translate simulation.
I think it is more desirable to do a post P&R simulation, but takes far
more time to finish than a post translate simulation, so I guess doing a
post translate simulation is a good compromise.
When the synthesis tool doesn't mess up the synthesis, usually the
results you will get from an RTL simulation and a post translate will be
pretty much the same besides some gate delays.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)




Jon Schneider wrote:
> 
> I have a very simple piece of functionality that is failing. I had
> simulated the complicated stuff on the PnR model but not this.
> 
> The XC2S30 outputs a magic number on udata when the micro reads from
> register 0. It then knows configuration is complete.
> 
> reg [7:0] udata_reg;
>    always @(uadr)
>     case (uadr)
>        0: udata_reg = 8'ha1; // a magic number
>        .
>        .
>      endcase
> 
>    assign udata = uadr<=3 && ucs ? udata_reg : 8'bz; // This is the real
> bidir output
> 
> which is fine but read on.
> 
> There are also writeable registers
> 
> reg [31:0] config;
> 
>   always @(negedge ucs)
>     case (uadr)
>       4: config [7:0] = udata;
>       5: config [15:8] = udata;
>         .
>         .
>   endcase
> 
> Iff I connect my flashing lights to a config register...
> 
> output [5:0] led;
> .
> .
> .
> assign led = config[31:26];
> 
> I no longer get that A1 out when reading register 0 (as noticed in
> real-life first). In fact a post-translate simulation shows that
> udata_reg is X when it should be A1. Latest Webpack. Any ideas ?
> 
> Jon

Article: 42059
Subject: Re: virtex2 bufgce or not bufgce
From: jeff@mock.com (Jeff Mock)
Date: 14 Apr 2002 14:42:58 -0700
Links: << >>  << T >>  << A >>
I think I know part of the answer.  bufgce and bufg are both 
macros that use the bufgmux primitive.  The output of bufgmux
drives a global clock net on the virtex2.  For your example, the ungated
clock source would drive the I0 input of two bufgmux's.  One of the bufgmux's
would have something fancy connected to the S input to do clock gating
and the other bufgmux would function like a bufg to distribute the ungated
clock.

With this I think I can rephrase your question to something like: "Is 
there guaranteed skew between two different bufgmux's that have the 
same "I0" input and drive different global clock nets?"

I don't know the answer to this, but I suspect the answer might
be "no" since in addition to process variation, the loading on
the two clock nets (gated clock, ungated clock) might be very 
different.

A little warning, if you mess around with bufgmux and try to do
something fancy with it, make sure the I0 input to bufgmux always
has a signal.  If I0 is left at a DC level the clock gating function
doesn't always work, bufgmux is not a simple 2:1 mux, there's extra stuff
in there to help prevent glitches on clock gating.  I got stuck
by this once.  It works fine in simulation, but the actual hardware
behaves differently (at least with 3.3i sim models).

[insert general religious statement that it's better to not gate
clocks at all...]

jeff 

Lasse Langwadt Christensen <langwadt@ieee.org> wrote in message news:<3CB8C185.86A96534@ieee.org>...
> Hi, 
> 
> I'm working on a design in a Virtex2 that uses both gated and 
> ungated clk's i.e. a clk is distributed to modules in the 
> design and some of them internally gate the clk to some of the logic. 
> 
> Can I just do the gating with a bufgce and run logic 
> of both system clk and some of a gated version of that clk, 
> or will there be so much skew between the two clks it's unsafe?
> 
> Or, will I have to change the code to run all clk's through 
> a bufgce to have them aligned? 
> 
> thanks,
> 
> -Lasse
> -- Lasse Langwadt Christensen, 
> -- Aalborg, Denmark

Article: 42060
Subject: Re: FPGA config without boot PROM???
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Sun, 14 Apr 2002 17:41:44 -0500
Links: << >>  << T >>  << A >>
You forgot Actel's ProASIC which is a flash-based FPGA.
I haven't used it myself, but sounds like an interesting part.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)



steve synakowski wrote:
> 
> The coolrunner and most CPLD's/PALs/GALs don't need to boot up. They are
> just programmed with the connections required using some type of EEPROM or
> FLASH cells. I haven't noticed FPGA's that don't need boot PROMs  but I
> haven't had the need to look yet, so I could be wrong.
> If the design will fit is the question. I see that CPLD's seem to have fewer
> gates than FPGA's, so if it is complex, it might not fit into a CPLD.
> Steve

Article: 42061
Subject: Re: FPGA eval/dev boards with *serial* interface?
From: Tom Loredo <loredo@astro.cornell.edu>
Date: Sun, 14 Apr 2002 19:10:22 -0400
Links: << >>  << T >>  << A >>
In article <3CB73557.8BCF1E34@xilinx.com>, anna.acevedo@xilinx.com wrote:

> Take a look at  http://www.digilentinc.com/Products/products.html
> 

Thanks, Anna, but their boards are all programmed via the parallel
port.  They have serial ports, but they are connected directly
to the FPGA for use by the FPGA once it's programmed.  I understand
the choice---with JTAG on the chips, it makes sense to use the
parallel port rather than have to decode a serial signal on
the dev board.  But I only have serial.

Unfortunately I don't have a "real" PC; I'm running VirtualPC
on a PowerMac G4.  It has served me well for several years,
running a variety of EDA software and controlling some 8 bit
microcontroller boards via serial.  But VirtualPC doesn't
support parallel ports, so adding a USB converter isn't
an option, nor is adding a PC card (since it's a Mac!).

So far it looks like I'm out of luck...  8-(  I may need
to get a cheap PC if I go the FPGA route, but is motivating
me to just use a faster microcontroller for the product
and do everything in firmware.  We'll see....

-Tom

Article: 42062
Subject: Re: FPGA config without boot PROM???
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Mon, 15 Apr 2002 12:35:44 +1200
Links: << >>  << T >>  << A >>
Thomas wrote:
> 
> Is it true the CPLD's like coolrunner from Xilinx contain flash inside
> which can boot by itself?

Yes

> Which is ecomoical? CPLD's like coolrunner or FPGA

 An open ended question, generally the smallest device that will do the
job.
FPGA come much larger than CPLD.

> Is there any Industrial equvalent to Coolrunner from other chip manufactures?

 We have used Atmel ATF150x family to replace Coolrunners. They come in
industrial specs, and have lower static Icc than coolrunner, but higher
mA/MHz.
 Coolrunner is more of a 'moving target', as Xilinx keep shrinking the
device, it looses pin & voltage compatability with earlier models.
 Atmel would be a better choice for a long design life product.

-jg

Article: 42063
Subject: Using SRL16E Xilinx primitive.
From: andrew.bridger@paragon.co.nz (Andrew Bridger)
Date: 14 Apr 2002 20:42:05 -0700
Links: << >>  << T >>  << A >>
Hi,
This is my first attempt at instaintiating Xilinx primatives in my
VHDL and I am having trouble getting it to work on a real FPGA.  It
works fine in functional simulation.

I have instantiated a single SRL16E, with Q fed back to D, and an INIT
attribute of "0001" to create a very compact divide by 16.
When I test in real life I always see a logic low level at the Q
output.  Its almost like the init attribute is not being recognised. 
Is there a way I can check that 4.2i is applying the attribute to my
SRL16E? Any ideas?

Prior to the begin statement in my archtecture I have,

attribute init : string;
attribute init of test_srl16e : label is "0001";

--SRL16E
component srl16e
    generic(
	init : bit_vector(15 downto 0) := X"0001");
    port (
        d       : in std_logic;
        ce	: in std_logic;
        clk     : in std_logic;
        a0	: in std_logic;
        a1	: in std_logic;
        a2	: in std_logic;
        a3	: in std_logic;
        q       : out std_logic
    	);
end component;

Then I instantiate it after the begin statement in the arch.

test_srl16e: srl16e
    generic map(
	init => X"0001")
    port map (
        d       => connect_dq,
        ce	=> '1',	
        clk     => clk,
        a0	=> '1',	
        a1	=> '1',		
        a2	=> '1',		
        a3	=> '1',		
        q	=> connect_dq   
    	);

Regards
Andrew

Article: 42064
Subject: Re: DLL property control in UCF
From: "Norman Yang" <norman@zh.t2-design.com>
Date: Mon, 15 Apr 2002 11:43:54 +0800
Links: << >>  << T >>  << A >>
Thanks!
I wonder if I could add some constriant in verilog source code and affect
its simulation behavior.

Norman


--
Best regards.
Norman
norman@zh.t2-design.com

Falk Brunner <Falk.Brunner@gmx.de> wrote in message
news:a9bkkd$1k92t$3@ID-84877.news.dfncis.de...
> "Norman Yang" <norman@zh.t2-design.com> schrieb im Newsbeitrag
> news:a98pf7$5b6$1@news.cz.js.cn...
> > Hello everyone:
> > I meet a problem in controlling VertexE DLL property in UCF file. I
don't
> > know how to control the  Clock Divide Property of DLL in UCF. XILINX
>
> INST my_dll_inst_name clkdv_divide=8;        # divide by 8
>
> See also Xilinx Constaints guide, chapter C.
>
> --
> MfG
> Falk
>
>
>
>



Article: 42065
Subject: Re: "free" tools ... ?
From: Phil Hays <SpamPostmaster@attbi.com>
Date: Mon, 15 Apr 2002 05:27:25 GMT
Links: << >>  << T >>  << A >>
akhar wrote:
 
> are there any cheap HLL to program FPGA's? I have found information on
> Handel C yet either I get a crippled 30 day version or have to pay 35 000$
> (from what I've read in a press release). The Galadriel/nenya java compiler
> is .. inexistant. Is there something I can use for less than 200 $
> (including FPGA if possible)? the major vendors aren't quite clear on what
> they sell as HLL solutions.

You might try Xilinx "Forge" (java).  It's free for now, and Xilinx
states that they hope to be selling it this summer, but I don't know
what happens to old copies then.  Anyone from Xilinx care to comment? 
Also, if you are attached to a University, perhaps you may get a special
deal from one of the vendors: costs nothing to ask.

Basic tools for FPGA development are free (meaning funded by the
hardware companies), as the hardware vendors want to sell parts.  Basic
tools are just that.  Basic.  Will do the job, but supports a subset of
parts, mostly the smaller ones.  Lacks features that may save lots of
time.

Tools beyond basic are not cheap, as the population of FPGA designers
using such tools is fairly small.  For example, a fairly complete
version of the best of the VHDL synthesizers (Tool for VHDL translating
to netlist of primitives.) is around US$ 10,000.  This is not the most
expensive tool.  ASIC development tools are even pricier.

HLL tools for FPGAs are not currently aimed at the budget market. 
Perhaps they will be in the next decade: I think that the need for such
tools will grow in the future.  This might lead to a few good HLL tool
vendors and free HLL tools from the hardware vendors.  But this could
clearly could be wrong.  The future is rarely certain.


-- 
Phil Hays

Article: 42066
Subject: Re: FPGA eval/dev boards with *serial* interface?
From: "Felix Bertram" <fbertram@emagic.de>
Date: Mon, 15 Apr 2002 07:42:25 +0200
Links: << >>  << T >>  << A >>
Tom,

we just introduced our new Spartan-IIe development board. It is especially
well suited to develop FPGA-centric processor applications. The board is
powered and configured from USB. A summary may be found here:
http://www.trenz-electronic.de/prod/proden10.htm

The board will be priced 499.00EUR which is approximately 435.00USD. We are
prepared to begin shipping in 10 days.

Best regards

Felix
_____
Dipl.-Ing. Felix Bertram
Trenz Electronic
Duenner Kirchweg 77
D - 32257 Buende
Tel.: +49 (0) 5223 4939755
Fax.: +49 (0) 5223 48945
Mailto:f.bertram@trenz-electronic.de
http://www.trenz-electronic.de


"Tom Loredo" <loredo@astro.cornell.edu> schrieb im Newsbeitrag
news:3CB7372D.4A9430AE@astro.cornell.edu...
>
> Hi-
>
> I'm experienced with 8-bit microcontrollers, but a complete
> newbie to FPGAs.  I'm considering them for an upcoming
> project, and a factor in my choice is availability of
> an affordable evaluation/development board with a *serial*
> interface.  So far I've been looking at parts from Xilinx
> and Atmel, but the eval boards I've come across all use
> the parallel port on the PC.  I only have a serial or USB
> port, so these are not suitable.  Any leads/suggesions
> are appreciated.
>
> Thanks!
> Tom Loredo





Article: 42067
Subject: Re: virtex2 bufgce or not bufgce
From: Lasse Langwadt Christensen <langwadt@ieee.org>
Date: Mon, 15 Apr 2002 01:14:05 -0700
Links: << >>  << T >>  << A >>
Jeff Mock wrote:
> 

Hi, Jeff

> I think I know part of the answer.  bufgce and bufg are both
> macros that use the bufgmux primitive.  The output of bufgmux
> drives a global clock net on the virtex2.  For your example, the ungated
> clock source would drive the I0 input of two bufgmux's.  One of the bufgmux's
> would have something fancy connected to the S input to do clock gating
> and the other bufgmux would function like a bufg to distribute the ungated
> clock.
> 
> With this I think I can rephrase your question to something like: "Is
> there guaranteed skew between two different bufgmux's that have the
> same "I0" input and drive different global clock nets?"
> 
> I don't know the answer to this, but I suspect the answer might
> be "no" since in addition to process variation, the loading on
> the two clock nets (gated clock, ungated clock) might be very
> different.

I've been told the skew between the outputs of bufgmux's should 
be very small. What I want to do is slightly different, I want to
run logic of both a BUFG'd system clk and that system clk BUFGCE'd

thus, some of the logic runs of a clk that is BUFG'd, some of it of
a clk that is BUFG'd then BUFGCE'd, i.e.

clk ----bufg----+----------> continues clk
                |
                +--bufgce--> gated clk

I could change the design to some thing like this: 

clk ----bufg----+--bufgce--> continues clk
                |
                +--bufgce--> gated clk

But that means I'll have to change the design and not just replace 
modules, and I'd rather not 

snip
> 
> [insert general religious statement that it's better to not gate
> clocks at all...]

yeah, I know, but it'll go into an ASIC, and there it works just fine :) 

-Lasse
-- Lasse Langwadt Christensen, 
-- Aalborg, Denmark

Article: 42068
Subject: Re: Attributes *and* generics!?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 15 Apr 2002 09:33:30 +0100
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> writes:

> That sounds like new behavior for synplicity if true.  Synplicity used to
> complain if you had generics on black boxes, and those did not get passed to the
> netlist Generics were originally intended to control the synthesis, and still
> often does so putting them on black boxes hadn't made much sense.  Now where
> they are used as initialization attributes it makes a lot more sense, but
> caution must be taken to avoid including a generic that controls the
> elaboration.
> 

I've had this behaviour since 5.3ish, which is when I started using
it.  Now, they are used to control the synthesis, as the LPMs are
synthesised by the Altera place and route tool, so you can
parameterise the length/width of ROMs for example, as well as
controlling the speed/area tradeoff, amount of pipelining allowed etc.

What do you mean by a generic that controls the elaboration?

Cheers,
Martin

<snip>

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 42069
Subject: Re: Attributes *and* generics!?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 15 Apr 2002 09:34:32 +0100
Links: << >>  << T >>  << A >>
Mike Treseler <mike.treseler@flukenetworks.com> writes:

> Martin Thompson wrote:
> 
> > Without wishing to ignite anything - the Altera LPMs use the generics
> > for simulation, which Synplify passes through the EDIF netlist on the
> > blackboxes and then the P&R tool deals with it from there.  Any chance
> > of Xilinx imitating this?
> 
> The best thing about the Altera LPMs is that they are open source.
> If you ignore the schematic string interface, you get a 
> synthesizable template for useful hardware blocks that work
> for both brands A and X through the EDIF netlist. 
> Of course the coverage for brand A is better, since
> they wrote it.
> 

Hear hear!  Then i could port all my Altera code straight across to
Xilinx and start using their chips straight away :-)

Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 42070
Subject: Re: DLL property control in UCF
From: "H.L" <alphaboran@yahoo.no-spam.com>
Date: Mon, 15 Apr 2002 12:59:12 +0300
Links: << >>  << T >>  << A >>
Hi Falk,
can you also change the DLL's divide ratio from the FPGA editor? Please
correct me if I am wrong..

Greetings ,
Harris

"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:a9bkkd$1k92t$3@ID-84877.news.dfncis.de...
> "Norman Yang" <norman@zh.t2-design.com> schrieb im Newsbeitrag
> news:a98pf7$5b6$1@news.cz.js.cn...
> > Hello everyone:
> > I meet a problem in controlling VertexE DLL property in UCF file. I
don't
> > know how to control the  Clock Divide Property of DLL in UCF. XILINX
>
> INST my_dll_inst_name clkdv_divide=8;        # divide by 8
>
> See also Xilinx Constaints guide, chapter C.
>
> --
> MfG
> Falk
>
>
>
>



Article: 42071
Subject: Re: FPGA eval/dev boards with *serial* interface?
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Mon, 15 Apr 2002 15:15:14 +0200
Links: << >>  << T >>  << A >>
Tom,
you could use the board that comes with the Altera NIOS core. The ordering
code for the board alone at Altera is NIOS-DEVBOARD and it sells for US-$
795,-. By the way the complete kit with softcore 16-/32-bit CPU builder,
peripherals, licenses, compiler, linker, debugger and Quartus II limited
edition sells for US-$ 995,-.

The board has a serial interface and in the FPGA it has a NIOS CPU that
boots a little monitor programm called GERMS. Through the serial interface
and the monitor program you can program the on-board FLASH. If there's
content at a certain location of the on-board FLASH the FPGA will be
programmed from this location upon power-up. If you want to re-program after
you've downloaded your first applicaton you can implement a connection from
serial to FLASH in your own application or by setting a jumper you can force
the FPGA to boot from the original factory design with the CPU/monitor
program.

Hope this helps
- Wolfgang
http://www.elca.de

"Tom Loredo" <loredo@astro.cornell.edu> schrieb im Newsbeitrag
news:3CB7372D.4A9430AE@astro.cornell.edu...
>
> Hi-
>
> I'm experienced with 8-bit microcontrollers, but a complete
> newbie to FPGAs.  I'm considering them for an upcoming
> project, and a factor in my choice is availability of
> an affordable evaluation/development board with a *serial*
> interface.  So far I've been looking at parts from Xilinx
> and Atmel, but the eval boards I've come across all use
> the parallel port on the PC.  I only have a serial or USB
> port, so these are not suitable.  Any leads/suggesions
> are appreciated.
>
> Thanks!
> Tom Loredo



Article: 42072
Subject: Re: iMPACT FPGA detection error
From: MICHAEL ALEX <michaelalex@attbi.com>
Date: Mon, 15 Apr 2002 13:16:24 GMT
Links: << >>  << T >>  << A >>
Stefano -

     As you may have been told already, you can probably safely ignore
the differences.  I have a Spartan IIE board from NuHorizons and I had
the same issue when I tried to program it for the very first time.  But
now, iMPACT always "sees" the XC2S200 part correctly.  I also moved up
to WebPACK 4.2, which may have helped.  

     However, no matter what I do, Program Verify ALWAYS fails, with
hundreds of thousands of differences, but my program works fine.  Even
my local Xilinx FAE couldn't get Verify to work. However, with an
extremely complex program, I am not sure how to confirm programming.  

Good luck,
Michael



Stefano M wrote:
> 
> Hi all,
> i'm trying to download a simple code on Spartan II Demo Board
> (by Insight) via JTAG cable.
> The problem is that iMPACT detects a xcv100 instead of
> xc2s100, warns me and if i go ahead and try to program
> i receive a lot of difference.
> This is the log (if it can be helpful...):
> 
> Checking for System Ace MPM device...
> ----------------------------------------------------------------------
> Position PartName           Version  FileName
> 1        xc18v01            0        NOT YET ASSIGNED
> 2        xcv100             3        NOT YET ASSIGNED
> ----------------------------------------------------------------------
> 
> Validating chain...
> Boundary-scan chain validated successfully.
> '2': IDCODE is '00110000011000010100000010010011'
> '2': IDCODE is '30614093' (in hex).
> 
> Can someone help me to solve ?
> Thanks a lot,
> regards
> --
> Stefano Mora
> email: stefano.mora@*libero.it
> (remove *)

Article: 42073
Subject: JTAG cable and iMPACT
From: vlad@comsys.ntu-kpi.kiev.ua
Date: Mon, 15 Apr 2002 16:26:58 +0300
Links: << >>  << T >>  << A >>
Hi All
I made JTAG cable and it works normally on Foundation 3.3i in GUI JTAG
programmer 
but when I tried configure device with  iMPACT tool from WEB PACK 4.2
then cable is not detected ("Cable connection failed") . Where is
problem ?
Thank in advance.
Vladislav Vasilenko.

Article: 42074
Subject: Configuring XIlinx XL Fpga with no XL PROM.
From: NOSPAMingzampa77@yahoo.com (Frank Zampa)
Date: Mon, 15 Apr 2002 14:02:25 GMT
Links: << >>  << T >>  << A >>
Hi, can I use a 5V prom (XC17S05) to configure a Spartan XL (XCS05XL)?
The logic levels seems compatible.

Thanks, Frank.



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