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Messages from 42075

Article: 42075
Subject: Re: Using SRL16E Xilinx primitive.
From: Jonathan Swift <jonathan.swift@xilinx.com>
Date: Mon, 15 Apr 2002 15:13:03 +0100
Links: << >>  << T >>  << A >>

Hi Andrew,

Have you checked the contents of the LUT in FPGA Editor to ensure that the
INIT value has been applied correctly?
You can see the INIT attributes for every component using this.

As to your code, everything looks fine and you should be able to
initialise the contents of the SRL using this.

Hope this helps,

Cheers,

Jonathan

Andrew Bridger wrote:

> Hi,
> This is my first attempt at instaintiating Xilinx primatives in my
> VHDL and I am having trouble getting it to work on a real FPGA.  It
> works fine in functional simulation.
>
> I have instantiated a single SRL16E, with Q fed back to D, and an INIT
> attribute of "0001" to create a very compact divide by 16.
> When I test in real life I always see a logic low level at the Q
> output.  Its almost like the init attribute is not being recognised.
> Is there a way I can check that 4.2i is applying the attribute to my
> SRL16E? Any ideas?
>
> Prior to the begin statement in my archtecture I have,
>
> attribute init : string;
> attribute init of test_srl16e : label is "0001";
>
> --SRL16E
> component srl16e
>     generic(
>         init : bit_vector(15 downto 0) := X"0001");
>     port (
>         d       : in std_logic;
>         ce      : in std_logic;
>         clk     : in std_logic;
>         a0      : in std_logic;
>         a1      : in std_logic;
>         a2      : in std_logic;
>         a3      : in std_logic;
>         q       : out std_logic
>         );
> end component;
>
> Then I instantiate it after the begin statement in the arch.
>
> test_srl16e: srl16e
>     generic map(
>         init => X"0001")
>     port map (
>         d       => connect_dq,
>         ce      => '1',
>         clk     => clk,
>         a0      => '1',
>         a1      => '1',
>         a2      => '1',
>         a3      => '1',
>         q       => connect_dq
>         );
>
> Regards
> Andrew



Article: 42076
Subject: Re: Configuring XIlinx XL Fpga with no XL PROM.
From: Jonathan Swift <jonathan.swift@xilinx.com>
Date: Mon, 15 Apr 2002 15:19:13 +0100
Links: << >>  << T >>  << A >>


Hi Frank,

You'll need to use the xc17s05xl to configure this part, the xc17s05 is
not large enough for the Spartan-XL bitstream.

Cheers,

Jonathan

Frank Zampa wrote:

> Hi, can I use a 5V prom (XC17S05) to configure a Spartan XL (XCS05XL)?
> The logic levels seems compatible.
>
> Thanks, Frank.



Article: 42077
Subject: Xilinx BSCAN_SPARTAN2 component
From: koziar.pete@orbital.com (Pete Koziar)
Date: 15 Apr 2002 08:42:16 -0700
Links: << >>  << T >>  << A >>
Anybody use the BSCAN_SPARTAN2 component? I'm trying to use it to
implement a "cold loader" for our flash chip. The component isn't
exactly well-documented.

My assumptions are that:

o RESET is active high on start-up and whenever the JTAG state machine
is in the Reset state.

o Shift is active high and is asserted when data is to be shifted into
my register.

o The USER1 instruction should be loaded first into the IR, then the
associated data should be loaded into the DR.

o UPDATE is active high and is asserted for one clock transition after
the last bit is clocked in (the UPDATE-DR state). It is valid before
the falling edge of the JTAG clock.

Are these valid assumptions? Are there any war stories that can be
shared?

I'd appreciate any comments.

- Pete Koziar
  Principle Engineer
  VLU-120 Project
  Orbital Sciences/TMS

Article: 42078
Subject: Re: virtex2 bufgce or not bufgce
From: John_H <johnhandwork@mail.com>
Date: Mon, 15 Apr 2002 15:47:46 GMT
Links: << >>  << T >>  << A >>
Isn't the first bufg in your illustrated trees unnecessary?  The signal that would
drive that bufg should drive both global clock elements.  The bufg and the bufgce
should both use the same bufgmux structure giving you good matching but - as you've
been warned - watch out for skews.  The skews should be known through the timing
analyzer.

Lasse Langwadt Christensen wrote:

> I've been told the skew between the outputs of bufgmux's should
> be very small. What I want to do is slightly different, I want to
> run logic of both a BUFG'd system clk and that system clk BUFGCE'd
>
> thus, some of the logic runs of a clk that is BUFG'd, some of it of
> a clk that is BUFG'd then BUFGCE'd, i.e.
>
> clk ----bufg----+----------> continues clk
>                 |
>                 +--bufgce--> gated clk
>
> I could change the design to some thing like this:
>
> clk ----bufg----+--bufgce--> continues clk
>                 |
>                 +--bufgce--> gated clk
>
> But that means I'll have to change the design and not just replace
> modules, and I'd rather not


Article: 42079
Subject: Re: FPGA config without boot PROM???
From: koziar.pete@orbital.com (Pete Koziar)
Date: 15 Apr 2002 08:49:03 -0700
Links: << >>  << T >>  << A >>
"Chris Wilkson" <cwilkson@mit.edu> wrote in message news:<ee75da9.-1@WebX.sUN8CHnE>...
> I'm looking for an FPGA family that doesn't require a separate boot
> PROM.  (I can't afford the board space for the second chip.)
> 
> Does anyone have any suggestions?
> Please respond by email as I don't regularly read this forum.
> 
> Thanks!
> -Chris

We boot up the Spartan II from the same flash chip that holds the
firmware via logic in the CPLD that handles address decoding for the
flash.

- Pete Koziar
  Principle Engineer
  VLU-120 Project
  Orbital Sciences/TMS

Article: 42080
Subject: Re: new to fpga's need insight
From: koziar.pete@orbital.com (Pete Koziar)
Date: 15 Apr 2002 08:57:14 -0700
Links: << >>  << T >>  << A >>
I'd start with something a lot simpler than an ANN! Even though the
syntax you'd be dealing with is "C", you're not programming in "C" but
using "C" syntax to specify an electronic circuit. In particular, you
won't have an arithmetic logic unit unless you design one in. ANNs
require multiplies and adds, as well as (at least an approximation to)
the sigmoid function. All of these are non-trivial to implement in an
FPGA.

A good place to start is attending one of Xilinx's (or whomever's)
classes on FPGAs.

- Pete Koziar
  Principle Engineer
  VLU-120 Project
  Orbital Sciences/TMS

"akhar" <akhar@videotron.ca> wrote in message news:<NN_t8.42057$jD4.1370492@weber.videotron.net>...
> I am more concerned about optimising Neural network performances, so I think
> I will use one of the HLL's. It is the pulsed neural networks that interest
> me and since , from what I understand FPGA's are highly parrallel, they
> should be a match made in heaven. But in order to mmaximise performances I
> have to know a bit about how they work and what to do and not do. Basically
> my concerns are : storing values and changing then, and timing the
> computations. What I want to do is :
> - input the values in the first layer get a spike train (relative to time )
> - feed it in the second layer and get a spike train
> -this is more sequential
> or try to emulate real neurons which would fire when ever they reached their
> treshold (ie neurons in the second layer can fire even if processing in the
> first layer hasn't been completed).
> 
> You mention that the Xilinx java compiler will be free up til summer will
> the compiler "expire"?
> 
> Many thanks for your help
> 
> Stephane
> "Phil Hays" <SpamPostmaster@attbi.com> wrote in message
> news:3CB870BC.91689545@attbi.com...
> > akhar wrote:
> >
> > > Thanks for the pointers,
> > > I looked up Handel C and found a lot of article talking about it but no
> > > official web site?
> >
> > http://www.celoxica.com/home.htm
> >
> >
> > > is there one or is hcc the only compiler ?
> >
> > Synopsys and Forte have SystemC to Verilog or VHDL compilers.  SystemC
> > is a "standard" library of C++ classes.  Xilinx has a Java to Verilog
> > compiler that is "freeware" until this summer:
> >
> > http://www.xilinx.com/ise/advanced/forge.htm
> >
> > http://www.synopsys.com/cgi-bin/sld/ltl1.cgi#f2
> >
> > http://www.forteds.com/products/cynthesizer.html
> >
> >
> > > What sites do
> > > you recommend for learning how to program the FPGA's ?
> >
> > To do what?  If you want high speed digital signal processing in the
> > lowest cost possible FPGA, you may need different tools, attitudes and
> > skills than if you want to emulate a ASIC, or emulate obsolete hardware,
> > or communications equipment, or any of the various and sundry uses that
> > FPGAs are put to.  Some of the tools are useful for a narrow range of
> > types of designs.  For freeware tools, both Xilinx and Altera have
> > fairly nice packages for starting with VHDL or Verilog:
> >
> > http://www.altera.com/products/software/sfw-quarwebmain.html
> >
> > http://www.xilinx.com/webpack/index.html
> >
> >
> > > - Are there limits to what I can program?
> >
> > Of course.  Large FPGAs have ten's of thousands of slices and hundreds
> > of pins, and these limit the computation than can be done in a clock
> > cycle and the amount of data than be input or output in a clock cycle.
> >
> >
> > >(I would like to use them to program neural networks)
> >
> > Are you more interesting in learning about FPGAs, in learning about
> > neural networks or is there an application of neural networks you are
> > interested in?  Also, is this learning or for a real product?  If you
> > are mostly interested in an application of neural nets, you have a need
> > to speed it up relative to a software implementation, but don't need a
> > fully optimized design, you might want to look at one of the
> > HLL(HandelC, SystemC, Java).  If you want to learn lots about FPGAs, you
> > might want to start with a much lower level of abstraction (schematic or
> > VHDL physical netlist) and learn about primitives, placement and other
> > basics of FPGA design.
> >
> >
> > > - what is the best recommended starter kit (altera's or xilinx's)
> >
> > I'd say Xilinx is somewhat ahead in general, this week.  Altera is
> > competitive, and has some advantages.
> >
> >
> > > - how do I know the number of gates I'll need for a project/application
> >
> > Don't look at gate counts.  The devices don't have "gates".  The devices
> > have small 4 input "Look Up Tables" LUTS, carry chains, multipliers and
> > other special purpose logic, and larger memories, and some of these can
> > be used for other purposes.  The published gate counts make the
> > assumption that you can use some large fraction of all of these: and
> > real designs don't.  I do estimation by trying to identify the resource
> > that will be most used, and plan for the part that has enough of that
> > resource.  It's not easy.  Usually, however, the design will be limited
> > by internal memory or by LUTs.  In Xilinx speak, one slice = 1 LUT + 1
> > flipflop (single bit storage).
> >
> >
> > --
> > Phil Hays

Article: 42081
Subject: Re: Xilinx FPGA load - XAPP 502
From: Mark Ng <mark.ng@xilinx.com>
Date: Mon, 15 Apr 2002 10:37:51 -0700
Links: << >>  << T >>  << A >>
Both the Verilog and VHDL code already exist in the XAPP502.zip file...

Best Regards,
Mark

Digital EE wrote:

> Xilinx's XAPP 502 points you to Xilinx's web site where you can download
> Verilog and C code for interfacing a MicroP to a CPLD to program an FPGA.
> The Verilog code is what is compiled into the CPLD.
>
> My question - has anyone ported the Verilog code to VHDL, and if so, where
> can I get a hold of it?
>
> Thanks!
>
> To reply by email, remove the period and everything after it up to the @
> sign.


Article: 42082
Subject: XilinX Jtag Cable available in UK.
From: "Craig Ward" <ccward@waitrose.com>
Date: Mon, 15 Apr 2002 18:55:34 +0100
Links: << >>  << T >>  << A >>
Available on Ebay.

go to ebay.co.uk and search for xilinx.

Cheers
Craig



Article: 42083
Subject: Re: Using SRL16E Xilinx primitive.
From: cablow@yahoo.com (Carlton Blow)
Date: 15 Apr 2002 11:46:11 -0700
Links: << >>  << T >>  << A >>
Hi Andrew,

The problem you are experiencing lies in the transfer of
generic/attribute information of the primitives from the VHDL code
over into the Xilinx tools. Essentially, your generic/attribute
information is being ignored somewhere during your implementation
flow. Most likely during synthesis (check the resulting EDIF output
file to confirm).

Your syntax appears correct. However from past experience I have found
that sometimes the attribute(s) supported by the synthesis tool are
not always recognized by the Xilinx tools. I have also found that
direct manipulation of the primitive generic values to values other
than the default result in implementations that differ from the
results observed during a functional simulation.

It should also be mentioned that this "problem" you are having is not
limited to just the SRL16E's. You may also see a similar situation if
for example, you instantiated LUT based or block based memory
primitives with initialization values that differ from the default
(all zeros).

With all that being said, I would propose to you the following:

1 - Do not manipulate the generic default values of the primitives
directly. For a functional simulation, manipulate them instead by
using a configuration statement(s).

Thus the init generic would stay at the default value of "0000",
however the configuration statement(s) would override this to set it
at your desired value of "0001" for the functional simulation.

If the problem is with the direct manipulation of the generics, your
attribute should then pass through the implementation flow and the
initialization value would then be correctly processed by the Xilinx
tools.

2 - If (1) does not work, then also remove the init attribute.
Instead, add the desired initialization value(s) into the accompanying
UCF file of your design.

For details on adding the initialization info into the design's UCF
file, refer to the Xilinx support section of the Xilinx website. There
is an app-note or other detailing how to perform this function.

Regards,

Carlton

Jonathan Swift <jonathan.swift@xilinx.com> wrote in message news:<3CBADFEF.F81723D5@xilinx.com>...
> Hi Andrew,
> 
> Have you checked the contents of the LUT in FPGA Editor to ensure that the
> INIT value has been applied correctly?
> You can see the INIT attributes for every component using this.
> 
> As to your code, everything looks fine and you should be able to
> initialise the contents of the SRL using this.
> 
> Hope this helps,
> 
> Cheers,
> 
> Jonathan
> 
> Andrew Bridger wrote:
> 
> > Hi,
> > This is my first attempt at instaintiating Xilinx primatives in my
> > VHDL and I am having trouble getting it to work on a real FPGA.  It
> > works fine in functional simulation.
> >
> > I have instantiated a single SRL16E, with Q fed back to D, and an INIT
> > attribute of "0001" to create a very compact divide by 16.
> > When I test in real life I always see a logic low level at the Q
> > output.  Its almost like the init attribute is not being recognised.
> > Is there a way I can check that 4.2i is applying the attribute to my
> > SRL16E? Any ideas?
> >
> > Prior to the begin statement in my archtecture I have,
> >
> > attribute init : string;
> > attribute init of test_srl16e : label is "0001";
> >
> > --SRL16E
> > component srl16e
> >     generic(
> >         init : bit_vector(15 downto 0) := X"0001");
> >     port (
> >         d       : in std_logic;
> >         ce      : in std_logic;
> >         clk     : in std_logic;
> >         a0      : in std_logic;
> >         a1      : in std_logic;
> >         a2      : in std_logic;
> >         a3      : in std_logic;
> >         q       : out std_logic
> >         );
> > end component;
> >
> > Then I instantiate it after the begin statement in the arch.
> >
> > test_srl16e: srl16e
> >     generic map(
> >         init => X"0001")
> >     port map (
> >         d       => connect_dq,
> >         ce      => '1',
> >         clk     => clk,
> >         a0      => '1',
> >         a1      => '1',
> >         a2      => '1',
> >         a3      => '1',
> >         q       => connect_dq
> >         );
> >
> > Regards
> > Andrew
> 
> --

Article: 42084
Subject: FPGA parameters
From: "Jim Raynor" <chris@ultrasonix.com>
Date: Mon, 15 Apr 2002 18:50:55 GMT
Links: << >>  << T >>  << A >>
hi,

    I found there are too much different parameters for the FPGA.  I could
only understand half of them and it creates some difficulties for me to
select which is the right one to use.  I am wondering if there is any
document online that explain those parameters in detail?

    Parameters like CLB, Slice, LUT, Logic Cells,  System Gates, CLB
Array....etc.

    Thanks


    Jim



Article: 42085
Subject: Re: DLL property control in UCF
From: cablow@yahoo.com (Carlton Blow)
Date: 15 Apr 2002 11:59:59 -0700
Links: << >>  << T >>  << A >>
Hi Norman,

For situations where you desire the DLL's divider output to differ
from that of the default, you would do the following:

1 - Instantiate the DLL primitive of the UNISIM library as is. Do not
manipulate the default here. It will functionally work but not be
implementable.

2 - For functional simulation, override the default divide value by
using a configuration statement(s). This is only necessary for the
functional simulation. For example:

CONFIGURATION cfg_divby1p5 OF cddaststr IS
   FOR testbench
      FOR FPGA : an7829t 
          USE ENTITY an7829t.an7829t(structure);
          FOR structure
              FOR dll3 : clkdll
                  USE ENTITY UNISIM.clkdll(clkdll_v)
                  GENERIC MAP (
                               clkdv_divide => 1.5
                              );
              END FOR;
          END FOR;
      END FOR;
   END FOR;
END cfg_divby1p5;

3 - For implementation, override the default value via the UCF file.
For example say it is desired to divide by 1.5:

INST "DLL3" clkdv_divide = 1.5;

Regards,

Carlton

"H.L" <alphaboran@yahoo.no-spam.com> wrote in message news:<a9e8ap$2165$1@ulysses.noc.ntua.gr>...
> Hi Falk,
> can you also change the DLL's divide ratio from the FPGA editor? Please
> correct me if I am wrong..
> 
> Greetings ,
> Harris
> 
> "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
> news:a9bkkd$1k92t$3@ID-84877.news.dfncis.de...
> > "Norman Yang" <norman@zh.t2-design.com> schrieb im Newsbeitrag
> > news:a98pf7$5b6$1@news.cz.js.cn...
> > > Hello everyone:
> > > I meet a problem in controlling VertexE DLL property in UCF file. I
>  don't
> > > know how to control the  Clock Divide Property of DLL in UCF. XILINX
> >
> > INST my_dll_inst_name clkdv_divide=8;        # divide by 8
> >
> > See also Xilinx Constaints guide, chapter C.
> >
> > --
> > MfG
> > Falk
> >
> >
> >
> >

Article: 42086
Subject: Re: JTAG cable and iMPACT
From: koziar.pete@orbital.com (Pete Koziar)
Date: 15 Apr 2002 12:15:19 -0700
Links: << >>  << T >>  << A >>
What operating system (Windows 95, 98, 2000) are you running on in the PC?

- Pete Koziar
  Principal Engineer,
  Orbital Sciences/TMS
  Columbia, MD, USA

vlad@comsys.ntu-kpi.kiev.ua wrote in message news:<3CBAD522.3A7155E4@comsys.ntu-kpi.kiev.ua>...
> Hi All
> I made JTAG cable and it works normally on Foundation 3.3i in GUI JTAG
> programmer 
> but when I tried configure device with  iMPACT tool from WEB PACK 4.2
> then cable is not detected ("Cable connection failed") . Where is
> problem ?
> Thank in advance.
> Vladislav Vasilenko.

Article: 42087
Subject: Re: FPGA parameters
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Mon, 15 Apr 2002 12:16:39 -0700
Links: << >>  << T >>  << A >>


Jim Raynor wrote:

> hi,
>
>     I found there are too much different parameters for the FPGA.  I could
> only understand half of them and it creates some difficulties for me to
> select which is the right one to use.  I am wondering if there is any
> document online that explain those parameters in detail?
>
>     Parameters like CLB, Slice, LUT, Logic Cells,  System Gates, CLB
> Array....etc.

Well, these devices are complex, but we still try our best to explain the
functionality, and indirectly also the TLAs (Three-letter acronymns ), in the
architecture description at the front of the data sheet. With the
newest-generation devices, there is a ( deplorable) tendency to assume that the
reader already knows something about the simpler devices.

In practical terms, you might want to glance at the older data sheets ( like
XC4000XL) to get a feel for the architecture, before you get overwhelmed by all
the new goodies in Virtex-II and Virtex-II Pro.

But the newer parts offer much more performance and functionality.

Peter Alfke


Article: 42088
Subject: Re: new to fpga's need insight
From: Phil James-Roxby <phil.james-roxby@xilinx.com>
Date: Mon, 15 Apr 2002 13:32:35 -0600
Links: << >>  << T >>  << A >>
akhar wrote:
> 
> I am more concerned about optimising Neural network performances, so I think
> I will use one of the HLL's. It is the pulsed neural networks that interest
> me and since , from what I understand FPGA's are highly parrallel, they
> should be a match made in heaven. But in order to mmaximise performances I
> have to know a bit about how they work and what to do and not do. Basically
> my concerns are : storing values and changing then, and timing the
> computations. What I want to do is :
> - input the values in the first layer get a spike train (relative to time )
> - feed it in the second layer and get a spike train
> -this is more sequential
> or try to emulate real neurons which would fire when ever they reached their
> treshold (ie neurons in the second layer can fire even if processing in the
> first layer hasn't been completed).
> 
> You mention that the Xilinx java compiler will be free up til summer will
> the compiler "expire"?
> 
> Many thanks for your help

I still don't really understand what you want to do on the FPGA, but I
will guess, state my assumption and make observations.
You want to speed up the execution of a neural network over a software
implementation.  FPGA's are indeed parallel, so if you can fit it on a
chip, and keep it fed with representative data, and consume the results,
you are on a winner.  I did exactly this many years ago using an Actel
device - don't tell my current employers :-) Unsuprisingly, I/O costs
swamped the speed up I got from parallel execution.  So ask yourself the
tough question, can I keep this super-hungry creature fed and deal with
his droppings, or should I just do a software model.
"Storing values and changing them" - what exactly do you mean here? 
Weights of some 
description?  Similarly, timing the computation?  From memory, the time
between pulses in these types of networks is what determines the
activity level - is this what you mean?  Getting activity levels from a
bit stream? 
When you finally get the structure you need, and are to integrate it in
a system with I/O, then think FPGA.  For now, I would model the
behavior.
Phil

-- 
------------------------------------------------------------
 __
/ /\/ Dr Phil James-Roxby          Direct Dial: 303.544.5545
\ \   Sr. Staff Software Engineer  Fax        : 303.442.0198
/ /   Reconfigurable Logic Group 
\_\/\ Xilinx Labs @ Boulder, CO  Phil.James-Roxby@xilinx.com 
              
------------------------------------------------------------

Article: 42089
Subject: Re: FPGA eval/dev boards with *serial* interface?
From: Tom Loredo <loredo@astro.cornell.edu>
Date: Mon, 15 Apr 2002 15:38:57 -0400
Links: << >>  << T >>  << A >>

Thanks, Felix and Wolfgang, for the very useful leads!

-Tom

Article: 42090
Subject: Re: DLL property control in UCF
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 15 Apr 2002 22:16:32 +0200
Links: << >>  << T >>  << A >>
"H.L" <alphaboran@yahoo.no-spam.com> schrieb im Newsbeitrag
news:a9e8ap$2165$1@ulysses.noc.ntua.gr...
> Hi Falk,
> can you also change the DLL's divide ratio from the FPGA editor? Please
> correct me if I am wrong..

You can. But this can only be done by hand, not in the automated design
flow.

--
MfG
Falk

BTW. Iam not sure if it makes much sense to simulate the DLL. It is prooven
that the DLL works. So you can simply apply a test pattern to your circuit
instead of using the DLL model. The really bad effects of the DLL (skew on
clock buffers due to much different clock loading) cant be simulated at all.
You have to know them (and counteract) yourself.





Article: 42091
Subject: Re: FPGA parameters
From: "Kevin Neilson" <kevin_neilson@removethis-yahoo.com>
Date: Mon, 15 Apr 2002 21:06:03 GMT
Links: << >>  << T >>  << A >>
If it were easy, it would be software!

"Jim Raynor" <chris@ultrasonix.com> wrote in message
news:jiFu8.5663$UH1.599933@news2.telusplanet.net...
> hi,
>
>     I found there are too much different parameters for the FPGA.  I could
> only understand half of them and it creates some difficulties for me to
> select which is the right one to use.  I am wondering if there is any
> document online that explain those parameters in detail?
>
>     Parameters like CLB, Slice, LUT, Logic Cells,  System Gates, CLB
> Array....etc.
>
>     Thanks
>
>
>     Jim
>
>



Article: 42092
Subject: Re: problems with Nios 2.0
From: kempaj@yahoo.com (Jesse Kempa)
Date: 15 Apr 2002 14:37:57 -0700
Links: << >>  << T >>  << A >>
Hi,

I don't believe Win 98 is a supported operating system for Nios. I
have seen it work on 98, but like many other applications out there
things are allot less stable than on Windows NT/2000/XP.

Someone told me that the root of the problem was in fact the
Cygwin/GNU tools do not support Win 95/98, and that is what causes the
Nios generation errors (during SDK generation, the GNU tools are
called to generate your SDK, build header files, compile libraries,
etc.).

- Jesse


"Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message news:<3cb69b58$0$227$cc9e4d1f@news.dial.pipex.com>...
> "Matjaz Finc" <matjaz.finc@fe.uni-lj.si> wrote in message
> news:a961r4$o9$1@planja.arnes.si...
> > Hello!
> >
> > Has anyone experienced any problems with Nios 2.0 (build 224) in Quartus
>  II
> > 2.0? I can't generate it with SOPC builder - it always terminates with an
> > error. Even Altera representatives and their official support were of no
> > help (!?) until recently - they said it will be fixed in next update. My
>  OS:
> > win98.
> 
> Though I can't help with the specifics, I have found that all of the tools
> run far more smoothly under windows 2k. I used to dual-boot, but frankly I
> don't bother with win9x now.
> 
> Another tip is to make sure all tools run from paths with no spaces. The
> batch command line scripts etc have a habit of sometimes not working with
> spaces. (e.g. Leonardo integration etc)
> 
> Paul

Article: 42093
Subject: Re: Xilinx BSCAN_SPARTAN2 component
From: Mike <none@null.net>
Date: Mon, 15 Apr 2002 14:08:28 -0800
Links: << >>  << T >>  << A >>
Pete,

Check out this solution record (you'll also get it if you search for BSCAN_VIRTEX on support.xilinx.com):

http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10703

Mike

Article: 42094
Subject: Re: FPGA parameters
From: cablow@yahoo.com (Carlton Blow)
Date: 15 Apr 2002 16:17:58 -0700
Links: << >>  << T >>  << A >>
Hi Jim,

Yes there are many different "parameters" as you call them. Too many
to discuss all at once in a single newsgroup reply.

The information you desire can be found in the datasheets and
app-notes for a particular given FPGA vendor. Simply check out the
web-site for each of the FPGA vendors. There's only a handful of
vendors so information mining should be fairly easy. Print a few out,
spend an afternnon to compare and contrast.

If after reading through the material, you are still uncertain,
contact the FAE(s) of the FPGA vendor(s) you are interested in. In
addition to the information they directly know, they may also have
additional information which can help you sort things out.

In addition, the FPGA vendors hold informal seminars either locally,
on-site, or even via the web. Some of the seminars discuss the very
information you are trying to sort out. Again contact your local
vendor FAE for details.

If after all that you still have questions, post it up on the
newsgroup. That's what it's for !

And finally, relax, there are a lot of parameters, but it's not as bad
as it looks. Many are redundant or very similar. A lot of it (but not
all) is simply a buzzword marketing game. Over time you will begin to
see the big picture and thus adapt accordingly.

Once you do narrow down to a vendor or two, have a few datasheets,
app-notes, or seminar notes kicking around so you can reference them
as needed to further your understanding.

Regards,

Carlton

"Jim Raynor" <chris@ultrasonix.com> wrote in message news:<jiFu8.5663$UH1.599933@news2.telusplanet.net>...
> hi,
> 
>     I found there are too much different parameters for the FPGA.  I could
> only understand half of them and it creates some difficulties for me to
> select which is the right one to use.  I am wondering if there is any
> document online that explain those parameters in detail?
> 
>     Parameters like CLB, Slice, LUT, Logic Cells,  System Gates, CLB
> Array....etc.
> 
>     Thanks
> 
> 
>     Jim

Article: 42095
Subject: Re: JTAG cable and iMPACT
From: Michol Bauer <micholba@xilinx.com>
Date: Mon, 15 Apr 2002 18:07:35 -0600
Links: << >>  << T >>  << A >>
Vladislav,

Check your XRAY file for 4.2 to make sure the that
the fileset.txt shows the parallel driver was installed
"summary=Parallel Cable III Driver".

(NOTE: W95 is not supported.)

Regards,
Michol Bauer

vlad@comsys.ntu-kpi.kiev.ua wrote:

> Hi All
> I made JTAG cable and it works normally on Foundation 3.3i in GUI JTAG
> programmer
> but when I tried configure device with  iMPACT tool from WEB PACK 4.2
> then cable is not detected ("Cable connection failed") . Where is
> problem ?
> Thank in advance.
> Vladislav Vasilenko.


Article: 42096
Subject: JTAG 1532 BSDL Files for xc95xxxxl
From: kevin@ehansen.com (Kevin Hansen)
Date: 15 Apr 2002 17:32:30 -0700
Links: << >>  << T >>  << A >>
I want to be able to use JDrive to program my 95xxx devices, but I don't 
see any "1532" JTAG BSDL files for that family amoung the other "1532" BSDL 
files. Am I overlooking them?

Thank you,
Kevin Hansen

Article: 42097
Subject: Looking for SpartanXL demo board
From: spam_hater_7@email.com (Spam Hater)
Date: Tue, 16 Apr 2002 02:10:05 GMT
Links: << >>  << T >>  << A >>
Hi,

I'm looking for a SpartanXL demo board.  Any good ones out there?

Something I can download with my XChecker cable, and get at all the
pins.

TIA

Article: 42098
Subject: Re: Looking for SpartanXL demo board
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Mon, 15 Apr 2002 21:52:55 -0500
Links: << >>  << T >>  << A >>
Why not go with a Spartan-II demo board?
It seems more readily avaiable.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)



Spam Hater wrote:
> 
> Hi,
> 
> I'm looking for a SpartanXL demo board.  Any good ones out there?
> 
> Something I can download with my XChecker cable, and get at all the
> pins.
> 
> TIA

Article: 42099
Subject: why does my counter pause while its enable signal is still active?
From: lunaris_s@yahoo.com (mm)
Date: 15 Apr 2002 19:54:36 -0700
Links: << >>  << T >>  << A >>
hi,folk
    I'm now debuging my design with XCV100E,and much puzzled by the
 strange waves i've got at logic analyzer.
    See,I have a counter in one of my blocks.It works well if i only
 implement this block or half of my design into the fpga.Normally it
 will keep counting if enable signal is high.But after i implement all
 the design into that fpga,the counter will pause during operation
 though its enable signal is still active according to the wave i
watched
 on logic analyzer.
    The design only take up 20% resources of that fpga.Guess the only
 unusual thing I have in that design is two "big" fifo with the width
 of 75bits and depth of 256.
    I've once replaced XCV100E with XCV300E,but still the same
thing.And I've checked the timing report,it can run much higher than
requirement.
    Is it possible that it is some disturb source of the board that
causes the strange thing?After the pause of the counter I did find
some odd pulses on some of my internal signals which are supposed to
be flat for there is no trigger at all.
    Really don't know what's up with that fgpa.Have anyone ever
encountered with such thing?any suggestion?thx in advance.
 regards
 mm



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