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Messages from 42175

Article: 42175
Subject: Re: Problems with Nios 2.0
From: crob714@yahoo.com (crob)
Date: 17 Apr 2002 15:19:19 -0700
Links: << >>  << T >>  << A >>
I think I might know what your problems are:

For the first issue, I have heard that this may be caused by being in
the wrong directory.  For some reason, Quartus remembers the last
directory opened and starts from there.  A simple workaround is to
open a file from Quartus in the same directory that your Nios system
resides in.  It should have the correct path to the SDK directory
after this.

The second one is simple.  For Nios 2.0, you don't use the Bash shell
anymore.  You would use the Nios SDK Shell, located in your start menu
Programs>Altera>Excalibur Nios 2.0> Nios SDK Shell.

Hope that helps,

c-rob

izuazua@ikerlan.es (Itsaso Zuazua) wrote in message news:<709383e9.0204170625.2224c4ab@posting.google.com>...
> Hi,
> 
>   I have several problems with the Nios 2.0:
> 
>     1-When I want to generate a Nios system module with the
> SOPC_BUILDER it gives me errors saying that:"doesīnt find boot
> monitor, uname:unknown, grep:unknown...
>     2-On the other hand, when I try to run the bash shell I have also
> problems.It says me that 'bash.exe:canīt find /tmp file;create one'
> 
>    Iīm thinking that I havenīt installed the NDK (HDK and SDK) tool
> properly, despite the fact that I have installed it step by step as
> itīs described in the documentation. Should I consider some
> environment variables as PATH,TMP_DIR...? Is important the path where
> I install the cygwin software? Should this path be the same or
> relative to the SDKīs path?
> Could anybody help me, please? 
> 
>    Thanks a lot,
> 
>       ITSASO

Article: 42176
Subject: Re: problem installing xilinx foundation 3.1 on a P4
From: Vaggelis Tripolitakis <tripol@mhl.tuc.gr>
Date: Thu, 18 Apr 2002 01:54:06 +0300
Links: << >>  << T >>  << A >>
Hello Harry and thanks for your cooperation :

I followed the guide in the link you gave and eventually Foundation 3.1
was correctly installed. Unfortunately I need to use "Core Generator"
generated components which are part of a design used in my thesis.
After the installation I started from Foundation the Core Generator with
no success..It just didn't start . I also tried to start the program
from the start menu and I got the error :

"Core Generator has abnormally terminated"
"Application messages have been logged and displayed below:"

Unfortunately there was an empty text box underneath the error message.

Are there any suggestions on that ?


Thanks in advance

Vaggelis Tripolitakis
Undergraduate Student
Microelectronics & Hardware Lab
Technical University of Crete
Greece


P.S. The target design is a virtex 1000 family fpga so I can't use tools
such webpack ISE and similar to that.... :-(


------------------------------------------------------------------------


Hari Devanath wrote:

> VAggelis,
> Pentium 4 Processors were not available when Foundation 3.1i Software
> was released, and this solution has not been fully tested by Xilinx.
> Please refer this Answer for a work around:
> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10634
> 
> Hope this helps,
> Hari.
> 
> Vaggelis Tripolitakis wrote:
> 
> 
>>Hello ppl ,
>>
>>I 'm trying to install Xilinx Foundation 3.1 (Licensed version) on a
>>P4 machine and during the installation it crashed repeatedly showing
>>the following error :
>>
>>"java.exe Application error...."
>>
>>I tried to install Foundation 4.1 and it worked OK but I don't have
>>a license version...So anyone can help ?
>>
>>Thanks in advance
>>
>>Vaggelis Tripolitakis
>>Undergraduate Student
>>Microelectronics & Hardware Lab
>>Technical University of Crete
>>Greece
>>
> 


Article: 42177
Subject: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
From: "Martin E." <0_0_0_0_@pacbell.net>
Date: Wed, 17 Apr 2002 23:07:28 GMT
Links: << >>  << T >>  << A >>
> Just thought I'd put up a short review of this book as well. I bought it
on
> the strength of the review (below) posted in these newsgroups

My frustration (as a beginer trying to get a job done) with the books I have
(a half dozen+) is that they are either a listing of language structures
with very little hands-on or that they completely neglect to tell the whole
story.

The most blantant (and it really got me angry) example, is "Verilog HDL
Synthesis. A Practical Primer" by J. Bhasker.  He goes along and introduces
a number of topics.  Then there's a chapter (3) titled "Modeling Examples".
Nice incremental examples ... building blocks.  Towards the end of the
chapter he presents a "synthesizable UART model".  As I was reading the book
I though: Great!  A real device!  This is where he puts it together.  To my
disappointment he devotes all of five pages to this example.  He presents
three out of at least five modules required to make the device and never
even discusses actually making a device (as in assigning IO's etc.).  Also,
absolutely no comments anywhere in the code.  Which brings me to another
question:

What is it with HDL programmers?  Is there a fobia for commenting code?  I
mean, huge app notes for things like synthesizable DDR RAM code and
virtually not a single comment to be found!  As a software and hardware
(pre-HDL) guy, I am absolutely amazed that this seems to be prevalent.  I
consider comments an essential part of coding, whether it is HDL or
software.  I've had to go back to very large projects years later and all of
my work commenting the code was the only thing that allowed me to get back
on the subject quickly.


> somewhat, but at the end of the day I'd much prefer to give you a list of
> seven or eight app notes/articles that are freely available that provide a
> similar amount of content.

What are they?  Links?

What I would like to see in a book is simple:  Take five or six projects of
increasing complexity and have a chapter or set of chapters taking each one
from inception to completion.  This means from generating specifications, to
choosing the chip, writing the code, fitting it to the chip, making changes
and programming the chip.  That would be a very useful book.  There are a
million books and online references for language syntax and constructs.
Devoting the front half a book to this is kind of silly any more.  A
hands-on, practical, "this is how you do this" book would be of value to
beginners and advanced HDL programmers alike.  I'd pay $150 for a book like
that.  The example projects would have to be good, no fluff.  I've wasted
more than that in time trying to find ansers to problems in other books
and/or online.


--
Martin E.

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 42178
Subject: Re: Reconfiguring Spartan II after boot-up
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 17 Apr 2002 16:13:02 -0700
Links: << >>  << T >>  << A >>
The chip can initiate its own reconfiguration, by pulling PROG Low. Somebody might consider this a risky
timing issue, but it is not. The reprogramming process is triggered by PROG, so once initiated it is
unstoppable.

I have explained this with the classical suicide problem: How can one carry it through when one is half
dead ? That's why candidates use a gun or jump from high buildings...
Sorry for the macabre analogy.

Peter Alfke
=============
rickman wrote:

>  In fact, I don't think you
> can pulse PROGRAM- low by the FPGA itself.  The output will go tristate
> before you can pull it up again.  You will need an external pullup
> resistor to do that.
>
> I


Article: 42179
Subject: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
From: William Meyer <wmhmeyer@earthlink.net>
Date: Thu, 18 Apr 2002 00:39:38 GMT
Links: << >>  << T >>  << A >>
In article <Qenv8.1602$gP4.741952581@newssvr14.news.prodigy.com>, 0_0_0_
0_@pacbell.net says...
> 
> What I would like to see in a book is simple:  Take five or six projects of
> increasing complexity and have a chapter or set of chapters taking each one
> from inception to completion.  This means from generating specifications, to
> choosing the chip, writing the code, fitting it to the chip, making changes
> and programming the chip.  That would be a very useful book.  There are a
> million books and online references for language syntax and constructs.
> Devoting the front half a book to this is kind of silly any more.  A
> hands-on, practical, "this is how you do this" book would be of value to
> beginners and advanced HDL programmers alike.  I'd pay $150 for a book like
> that.  The example projects would have to be good, no fluff.  I've wasted
> more than that in time trying to find ansers to problems in other books
> and/or online.

I agree completely. The book that comes with Cypress Warp starts out 
well, but then moves directly from low-level logic to a very brief 
treatment of a FIFO design, and then a chapter on state machines. The 
first design example is the 2901 bit-slice, which seems just a tad over 
the top.

Along the way, it failed to present some of the fundamentals of the 
syntax in a form useful to me in attempting a real design. I then dove 
into my own work, and found help here from Clyde Shappee, and with a few 
exchanges of messages, he had saved me hours of frustration, and greatly 
increased my understanding.

I'd love to find a thorough book which presents from square one and 
proceeds methodically with practical examples on a reasonable gradient 
of difficulty. If it were $150, $200, or even $300, I would buy it 
happily.

Bill

Article: 42180
Subject: Re: GND Outputs being optimized out using FPGA Express 3.6.1 in ISE4.2.01
From: "William L Hunter Jr" <wlhunterjr@attbi.com>
Date: Thu, 18 Apr 2002 00:52:55 GMT
Links: << >>  << T >>  << A >>


Austin

I can understand this for inputs but don't agree on outputs.  Inputs may not be 
required to implement a desired function and therefore be optimized out.  But 
setting a output to logic0 (i.e. output<=3D'0') should also work.

Thanks
Bill
  "Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3CBDA28C.8496D40F@xilinx.com...
  William, 
  See: 

   http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=3D1&iCountryID=3D1&getPagePath=3D9780 

  For how to "keep" and "don't touch" instantiations so the tools don't rip them out.... 

  Austin 

  William L Hunter Jr wrote: 

    Hi 
    I am doing a Virtex-II design using ISE 4.2.01 and FPGA Express 3.6.1.  I 
    have a few pins on my top level entity configured as outputs which are used 
    to set the address of some external devices.  In my architecture, I assign 
    these outputs a '0'.  FPGA express is optimizing out this connection.  If I 
    look at the synthesis optimized schematic viewer the connection to gnd and 
    output pad are missing.  How do you connect outputs to GND in VHDL?  I have 
    always assigned them a '0' in the VHDL and this always worked.  Any ideas on 
    what could be wrong?? 

    Thanks in advance 
    Bill




Article: 42181
Subject: Re: FPGA Timing Problem
From: Ray Andraka <ray@andraka.com>
Date: Thu, 18 Apr 2002 01:25:22 GMT
Links: << >>  << T >>  << A >>
Sunday paper???  You clearly have way too much time on your hands if you
get to read that ;-)

Spam Hater wrote:

> They have this thing called "a life".
>
> I read about it in the Sunday paper once.  Always wondered what it
> was, but none of them ever stayed late enough for me to ask them.
>
> On Tue, 16 Apr 2002 19:32:04 -0700, John  Larkin
> <jjlarkin@highlandSNIPTHIStechnology.com> wrote:
>
> >
> >Why is it that all the production people like to get to work real
> >early and then leave early, while the engineers arrive late and work
> >late, so that when you really need a big chip replaced there's nobody
> >around to do it for you?
> >
> >John
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 42182
Subject: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
From: "Chuck Woodring" <c.woodring@worldnet.att.net>
Date: Thu, 18 Apr 2002 01:42:40 GMT
Links: << >>  << T >>  << A >>
I thought the XESS corrp. tutororials for the Xilinx Webpack were a step in
the right direction but someone could take this approach a bit further.

m2cents

cTW



Article: 42183
Subject: Re: FPGA Partioning
From: akash.rai@st.com (Akash Rai)
Date: 17 Apr 2002 21:20:41 -0700
Links: << >>  << T >>  << A >>
Hi ,
    You can find quite some material on Chip Partitioners at the
following site (http://nexus6.cs.ucla.edu/software/PDtools/) , you can
download a freeware (UCLA/ABKgroup Physical Design Tools) that also
comprises of a partitioner (MLPart) . If you have any new information
regarding circuit partitioners I would be interested .

RGDS
Akash Rai

Article: 42184
Subject: Re: Telecom Bus info
From: "sweir" <weirsp@yahoo.com>
Date: Thu, 18 Apr 2002 07:00:09 GMT
Links: << >>  << T >>  << A >>
PMC is happy to supply Verilog / VHDL models under NDA.  Contact your FAE.
You may be able to glean sufficient information from the specifications of
any of their chips that interface to it.  It is relatively straight-forward.

Regards,
"VP" <lucky_hero@yahoo.com> wrote in message
news:529a044.0204161325.1f0f0892@posting.google.com...
> Hi,
>
> I am looking for spec/details on Telecom Bus (TelecomBus). I searched
> on the web and all I could get is a number of links to PMC Sierra
> which  offers Telecom bus bridges, converters, serializers etc but
> does not offer much details about Telecom bus protocol. Neither could
> I find anything on the IEEE standards website.
>
> I am designing an ATM Cell Processor in FPGA which has Telecom bus
> interface. I would greatly appreciate if someone can point me to
> relevant info on Telecom Bus.
>
> Thanks



Article: 42185
Subject: problems with Nios 2.0
From: izuazua@ikerlan.es (Itsaso Zuazua)
Date: 18 Apr 2002 01:15:35 -0700
Links: << >>  << T >>  << A >>
Hi,

  Thanks you very much, both James and crob for your help. I have
solved my problem. The solution has been "In a *Windows* command
prompt,
unmount / with "umount /" then remount e.g. "mount E:\\Altera\\CygWin
/", as James has adviced me, i.e, the two problems were related to an
incorrect install of CygWin.

   THANK YOU VERY MUCH!!!!!!!!

                     ITSASO

Article: 42186
Subject: Re: JTAG cable and iMPACT
From: jon@axisREmilMOVEton.ltd.uk (Jon Schneider)
Date: Thu, 18 Apr 2002 09:17 +0100 (BST)
Links: << >>  << T >>  << A >>
In article <3CBD3589.5C8F7FAA@attbi.com>, michaelalex@attbi.com (MICHAEL 
ALEX) wrote:

>      Make sure nothing is stealing the parallel port without your
> knowledge.  Even if BIOS is set up fine, something else in Windows may
> take it without being too obvious ....

I don't think so as that port has long been used for programming things 
(including Altera, AVR ISP, my own PIII type cable, SA1100 JTAG).

	Jon


Article: 42187
Subject: FPGA limitation
From: Sujatha Sriram <sujathasriram@yahoo.com>
Date: Thu, 18 Apr 2002 14:26:42 +0530
Links: << >>  << T >>  << A >>
I have read that there is a limitation to the number of adjacent output
drivers that can switch at the same time in an FPGA. There are rules
stated in terms of SSO(simultaneous switching outputs) pads between
power/gnd pins. Can anyone please elaborate on that..
 In such a case, consider a RTL written for ASIC, and say it has to be
prototyped. Tools are used to partition the design into multiple FPGA's.

How is this condition taken care of by the tool. Does it place the
interface signals taking the limitation into account? or does the
designer have to take care of it manually..


Article: 42188
Subject: fpga limitation
From: Sujatha Sriram <sujathasriram@yahoo.com>
Date: Thu, 18 Apr 2002 14:27:29 +0530
Links: << >>  << T >>  << A >>
I have read that there is a limitation to the number of adjacent output
drivers that can switch at the same time in an FPGA. There are rules
stated in terms of SSO(simultaneous switching outputs) pads between
power/gnd pins. Can anyone please elaborate on that..
 In such a case, consider a RTL written for ASIC, and say it has to be
prototyped. Tools are used to partition the design into multiple FPGA's.
How is this condition taken care of by the tool. Does it place the
interface signals taking the limitation into account? or does the
designer have to take care of it manually..


>


Article: 42189
Subject: 8051 Core for Motor Electronics
From: "Steffen Thieringer" <steffen.thieringer@nmb.co.uk>
Date: Thu, 18 Apr 2002 11:07:55 +0200
Links: << >>  << T >>  << A >>
Hello newsgroup!
I am looking for a 8051 Core to implement in an Xilinx Spartan2 FPGA.
The task for it is a control of a sensorless brushless DC motor.
The software for the processor is already done but needs to be speeded up.
So i need pwm, capture/compare units, several timers ans so on...
I have several in my mind but not yet found 'the one'.
I am not looking for freeware, but if there are some out there, please let
me know:-)

Thanks in advance

Steffen Thieringer



Article: 42190
Subject: Bidirectionnal bus...multiple sources driving the same signal...
From: "Eric Kral" <eric.kral@planetinternet.be>
Date: Thu, 18 Apr 2002 11:20:34 +0200
Links: << >>  << T >>  << A >>
Hi,

I am trying to realize a bidirectionnal bus between two components. It seems
to work (I can synthesize the design but the simulation doesn't work
properly, moreover I cannot implement the design and I can find the
problem(s)).
My synthesis tool is the latest version of the Webpack from Xilinx.
The idea of the design is to enable a fast communication between several
FPGA. The target FPGA is a Virtex-E from Xilinx. The TDM entity is to enable
the fast communication (TDM stands for time division multiplexing).
The SRAM is the interface for the SelectRam+ which is a blackbox in the
virtex-E (RAM of 4096 bits)
Finally the COMP entity should be the top design implemented in the FPGA.
----------------------------------------------------------------------------
-----------------------------------------
The error messages are:

ERROR:MapLib:115 - TBUF srampad_I4_0 is sharing enable signal with another
TBUF
   (tdmpad_I26) on the same bus. To allow the design to pass with this
   configuration, please set environment variable
XVK_MAP_ALLOW_BUS_CONTENTION.
   This error will become a warning if the environment variable is set.
----------------------------------------------------------------------------
-----------------------------------------
Here is my VHDL source:

library ieee;
use ieee.std_logic_1164.all;
package conversion is
 constant ADDRESS_SIZE : positive := 9;
 constant DATA_SIZE : positive := 8;
   constant TDM_SIZE : positive := 3;
 function DIV_BY_2 (DATA_SIZE : in positive) return positive;
end conversion;

package body conversion is
 function DIV_BY_2 (DATA_SIZE : in positive) return positive is
  variable TDM_SIZE_COMPUTED : positive;
 begin
  if (DATA_SIZE mod 2) /= 0 then
   TDM_SIZE_COMPUTED := (DATA_SIZE/2) + 1;
  else
    TDM_SIZE_COMPUTED := (DATA_SIZE/2);
  end if;
  return TDM_SIZE_COMPUTED;
 end DIV_BY_2;
end conversion;
----------------------------------------------------------------------------
------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conversion.all;
-- pragma translate_off
library unisim;
use unisim.vcomponents.all;
-- pragma translate_on

entity SRAM is
  port( CLK0, WE, EN,GRST : in std_logic;
        ADDR_BUS   : in std_logic_vector ((ADDRESS_SIZE - 2) downto 0);
        DATA_BUS   : inout std_logic_vector((DATA_SIZE - 1 ) downto 0));
end SRAM;

architecture BEHAVE of SRAM is
 component RAMB4_S8
   port( WE, EN, RST, CLK : in std_logic;
    ADDR         : in std_logic_vector (8 downto 0);
    DI        : in std_logic_vector (7 downto 0);
    DO           : out std_logic_vector (7 downto 0));
 end component;

 signal DIN, DOUT : std_logic_vector((DATA_SIZE - 1 ) downto 0);
 signal LOGIC0 : std_logic;

begin

 MEMORY : RAMB4_S8
 port map (WE=>WE, EN=>EN, RST=>GRST, CLK=>CLK0, ADDR(ADDRESS_SIZE -
1)=>LOGIC0,
          ADDR((ADDRESS_SIZE - 2) downto 0)=>ADDR_BUS, DI=>DIN, DO=>DOUT);

 BI_DIR : process (WE, EN, DATA_BUS, DOUT)
 begin
  if (EN ='1') then
   if (WE = '1') then
    DIN <= DATA_BUS;
   elsif (WE = '0') then
    DATA_BUS <= DOUT;
   end if;
  else
   DIN <= (others =>'Z');
   DATA_BUS <= (others =>'Z');
  end if;
 end process;
 LOGIC0  <= '0';
end BEHAVE;
----------------------------------------------------------------------------
------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conversion.all;

entity TDM is
port ( CLK2X, ENABLE, WE    : in std_logic;
   CLK0,D_OUT      : out std_logic;
   SYNC_DATA       : inout std_logic_vector (TDM_SIZE downto 0);
   SYNC_ADDR      : in std_logic_vector (TDM_SIZE downto 0);
   ADDR_BUS       : out std_logic_vector ((ADDRESS_SIZE - 2) downto 0);
   DATA_BUS       : inout std_logic_vector ((DATA_SIZE - 1) downto 0));
end TDM;

architecture BEHAVIOURAL of TDM is
 signal Q_TMP, D   : std_logic;
 signal EN     : std_logic;
begin
 EN <= ENABLE;
 CLK0 <= Q_TMP;


 D_FF : process (CLK2X, EN, D, Q_TMP)
 begin
  if EN = '0' then
   D <= '0';
  else
   if (CLK2X = '1' and CLK2X'event) then
   Q_TMP <= D;
   end if;
  end if;
  D <= NOT Q_TMP;
 end process;
  D_OUT <= D;
 SYNCHRO : process (CLK2X, Q_TMP, EN, SYNC_ADDR, SYNC_DATA,DATA_BUS,
WE) --(DATA_SIZE)=8
 begin
  if (EN ='1') then
   if (CLK2X = '1' and CLK2X'event) then
    if (WE = '0') then
     if (Q_TMP = '0') then
      SYNC_DATA(TDM_SIZE downto 0) <= DATA_BUS((DIV_BY_2(DATA_SIZE) - 1)
downto 0);
     elsif (Q_TMP = '1') then
      SYNC_DATA(TDM_SIZE downto 0) <= DATA_BUS((DATA_SIZE - 1) downto
(DIV_BY_2(DATA_SIZE)));
     end if;
    elsif (WE = '1') then
     if (Q_TMP = '0') then
      ADDR_BUS((DIV_BY_2(DATA_SIZE) - 1) downto 0) <= SYNC_ADDR(TDM_SIZE
downto 0);
      DATA_BUS((DIV_BY_2(DATA_SIZE) - 1) downto 0) <= SYNC_DATA(TDM_SIZE
downto 0);
     elsif (Q_TMP = '1') then
      ADDR_BUS((DATA_SIZE - 1) downto (DIV_BY_2(DATA_SIZE))) <=
SYNC_ADDR(TDM_SIZE downto 0);
      DATA_BUS((DATA_SIZE - 1) downto (DIV_BY_2(DATA_SIZE))) <=
SYNC_DATA(TDM_SIZE downto 0);
     end if;
    end if;
   end if;
  else
   DATA_BUS <= (others =>'Z');
   SYNC_DATA <= (others =>'Z');
   ADDR_BUS <= (others =>'Z');
  end if;
 end process;

end BEHAVIOURAL;
----------------------------------------------------------------------------
------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conversion.all;

entity COMP is
port ( D_OUT        : out std_logic;
   CLK2X, GRST, EN, WE   : in std_logic;
   SYNC_ADDR      : in std_logic_vector (TDM_SIZE downto 0);
   SYNC_DATA       : inout std_logic_vector (TDM_SIZE downto 0));
end COMP;

architecture BEHAVIOURAL of COMP is

 component TDM
  port( CLK2X, ENABLE, WE    : in std_logic;
    CLK0,D_OUT      : out std_logic;
    SYNC_DATA       : inout std_logic_vector (TDM_SIZE downto 0);
    SYNC_ADDR      : in std_logic_vector (TDM_SIZE downto 0);
    ADDR_BUS       : out std_logic_vector ((ADDRESS_SIZE - 2) downto 0);
    DATA_BUS       : inout std_logic_vector ((DATA_SIZE - 1) downto 0));
 end component;
 component SRAM
  port( CLK0, WE, EN,GRST   : in std_logic;
        ADDR_BUS      : in std_logic_vector ((ADDRESS_SIZE - 2) downto 0);
        DATA_BUS      : inout std_logic_vector ((DATA_SIZE - 1 ) downto 0));
 end component;

 signal  ADDR_TMP     : std_logic_vector ((DATA_SIZE - 1 ) downto 0);
 signal  DATA_TMP     : std_logic_vector ((DATA_SIZE - 1 ) downto 0);
 signal  CLK_TMP          : std_logic;

begin
 TDMPAD : TDM port map (CLK2X=>CLK2X, ENABLE=>EN, WE=>WE,
CLK0=>CLK_TMP,D_OUT=>D_OUT, SYNC_ADDR=>SYNC_ADDR,
    SYNC_DATA=>SYNC_DATA, ADDR_BUS=>ADDR_TMP, DATA_BUS=>DATA_TMP);
 SRAMPAD : SRAM port map (CLK0=>CLK_TMP, WE=>WE, EN=>EN, GRST=>GRST,
ADDR_BUS=>ADDR_TMP, DATA_BUS=>DATA_TMP);

end BEHAVIOURAL;
----------------------------------------------------------------------------
------------------------------------------





Article: 42191
Subject: Re: fpga limitation
From: Russell <rjshaw@iprimus.com.au>
Date: Thu, 18 Apr 2002 10:00:13 GMT
Links: << >>  << T >>  << A >>
Sujatha Sriram wrote:
> 
> I have read that there is a limitation to the number of adjacent output
> drivers that can switch at the same time in an FPGA. There are rules
> stated in terms of SSO(simultaneous switching outputs) pads between
> power/gnd pins. Can anyone please elaborate on that..

When lots of outputs switch, spikes of capacitive current flow thru
the power and ground pins/bond-wires. This causes the chip base to
momentarily float or bounce around 0V, which induces spikes onto
other pins. It reduces the noise margin of the system. The problem
is mainly due to lead/bond-wire inductance.

>  In such a case, consider a RTL written for ASIC, and say it has to be
> prototyped. Tools are used to partition the design into multiple FPGA's.
> How is this condition taken care of by the tool. Does it place the
> interface signals taking the limitation into account? or does the
> designer have to take care of it manually..

Article: 42192
Subject: Re: 8051 Core for Motor Electronics
From: Russell <rjshaw@iprimus.com.au>
Date: Thu, 18 Apr 2002 10:03:00 GMT
Links: << >>  << T >>  << A >>
Steffen Thieringer wrote:
> 
> Hello newsgroup!
> I am looking for a 8051 Core to implement in an Xilinx Spartan2 FPGA.
> The task for it is a control of a sensorless brushless DC motor.
> The software for the processor is already done but needs to be speeded up.
> So i need pwm, capture/compare units, several timers ans so on...
> I have several in my mind but not yet found 'the one'.
> I am not looking for freeware, but if there are some out there, please let
> me know:-)

How about just using a smaller fpga as a dedicated pwm/timer peripheral
for a cpu. Better still, a motor control dsp.

Article: 42193
Subject: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
From: "Paul Baxter" <pauljnospambaxter@hotnospammail.com>
Date: Thu, 18 Apr 2002 12:07:24 +0100
Links: << >>  << T >>  << A >>
<lots of valid argument about the lack of decent examples and lack of code
documentation snipped>

Don't you get fed up with another book whose only example is a
microprocessor. They use this as an excuse to spend ages detailing their
instruction set and how a processor works and publish lots of repetitive
code.

 IMHO many little examples would have been a lot better.

"Martin E." <0_0_0_0_@pacbell.net> wrote in message news:Qenv8.1602>
> > somewhat, but at the end of the day I'd much prefer to give you a list
of
> > seven or eight app notes/articles that are freely available that provide
a
> > similar amount of content.
>
> What are they?  Links?

Writing from a VHDL perspective:
You could do a lot worse than the following..

The VHDL FAQ (in particular the first part when it outlines common
mistakes - has a fair few typos but it is extremely helpful). Probably a
verilog equivalent over on comp.lang.verilog

www.opencores.org and have a browse of their VHDL/Verilog projects. Also
take a look at their coding guidelines (though I disagree with some :) )
Some of the projects are very well documented.

www.free-ip.com - looks like its been frozen for sometime, but nevertheless
there are some good projects worthy of examination if you like learning by
example.

www.altera.com and look in literature at applications notes. Lots of useful
info there even if you don't have an altera bias. While your there get the
Leonardo synthesis tool and spend time reading the Leonardo for Altera HDL
synthesis manual - lots of excellent basic advice for VHDL design and
Verilog design.

www.xilinx.com same procedure. Also look at the design articles/ideas for
some useful extras like the flancter synchronisation between asynchronous
domains. The FIFO app notes are quite informative (I like xapp175 for dual
clock fifos, but just look at apps titles.)

www.aldec.com take a look at ActiveHDL and the free trial. Ideally get a CD
from your local distributor as this contains a wealth of HTML help that's
invaluable. (Not sure if the download version contains this).
The VHDL reference area is worth its weight in gold; its open on my desktop
all the time :)

ActiveHDL may be too expensive for you if you are just starting out, but the
simulator is good and considerably more user friendly than Modelsim. It also
has schematic/FSM entry and various auxiliary tools such as Code2graphics. I
tried something like the free Altera SDRAM core and running it through
code2graphics gives you an excellent starting point for a block diagram.
A warning that applies to Altera integration with ActiveHDL, it looks pretty
good until you try and do anything complex or start wanting to specify
pinouts etc then the tool integration falls down somewhat. It also
integrates with Xilinx and many other tools, so you may find integration
with your favourite synthesis/PAR tool to be better.

There are whole sites devoted to links in HDL. It is very difficult to
pinpoint a good relevant set of links for everyone because each person wants
to know something different.



Another area I'd love to see web info about is tools information. It is
difficult to find so everyone has the aggravating learning curve:
[Aside]
It took me lots of grief with Altera tools to discover that I should never
use Quartus2 for synthesis as not only are its results poor, but it really
sucks whenever it finds an error. Usually crashes or exits after politely
telling you there might be a syntax error. Also you can't use generics
(except on Altera megafunctions), any sort of usable while loop etc etc etc
(long list) unless you host your design in Leonardo (having to reset all
your project settings every time it loads up, sigh) and just use Q2 for PAR.

Of course you probably want to set constraints (not just pin info but
cliques etc) so you are better off doing this in quartus....etc but that
means Leonardo shouldn't have 'write vendor constraints file' ticked (and it
ticks itself when you're not watching :) ) Lots of hoops to jump through to
get the software to work.

Creating block diagrams to convert to VHDL? Well maybe Q2 if you don't use
generics (or add them afterwards), maybe Emacs, maybe if you are richer
Active-HDL.

Best VHDL editor hmmm, I really like AHDL's because as well as syntax
highlighting it can colour blocks dependent on their meaning and fold/expand
the code. (Emacs probably does this for free, but I found it difficult to
get up and running on Windows)

Now this info SHOULDN'T be in books as its so changeable, but one day
someone will provide some insight into tool 'issues' if you want practical
results. (Sometimes the answer of spending Ģ20k isn't an option)

Sorry I had to get that off my chest... A four month project has taken 8
months and counting over many awkward issues I've had to learn the hard way.




Article: 42194
Subject: 1000 I/O Pins -- What is cheapest FPGA?
From: "UK Gary" <deton8@aol.com>
Date: Thu, 18 Apr 2002 11:08:49 +0000 (UTC)
Links: << >>  << T >>  << A >>
I need to design something where the FPGA must have about 1000 I/O pins.
What is my cheapest option?  The design must fit into a single FPGA, but
apart from that and the pin count I don't have any special requirements.

--

Guerre



Article: 42195
Subject: Re: 1000 I/O Pins -- What is cheapest FPGA?
From: "Paul Baxter" <pauljnospambaxter@hotnospammail.com>
Date: Thu, 18 Apr 2002 12:21:25 +0100
Links: << >>  << T >>  << A >>
"UK Gary" <deton8@aol.com> wrote in message
news:a9m9g1$28d$1@helle.btinternet.com...
> I need to design something where the FPGA must have about 1000 I/O pins.
> What is my cheapest option?  The design must fit into a single FPGA, but
> apart from that and the pin count I don't have any special requirements.

Firstly, I'm not sure you'll have any luck with 1000 I/O on one chip. There
are a few 1000+ pin chips out there, but I think these have less than 1000
i/o usable e.g 20k1500E can have 808 i/o pins

Secondly, why the single chip requirement? Is it a space issue? Because a
two chip mounted on either side of a board would probably take less space
and allow you to have far cheaper chips.



Article: 42196
Subject: Re: iMPACT FPGA detection error
From: "Stefano M" <stefano.mora@antispam.libero.it>
Date: Thu, 18 Apr 2002 14:34:52 +0200
Links: << >>  << T >>  << A >>
Thanks to all,
somebody send me a link to a Xilinx 'Answers Database'
where is explained that some Spartan-II production
(AFP series) does not support Verify !

Thanks again !
--
Stefano Mora
email: stefano.mora@*libero.it
(remove *)




Article: 42197
Subject: Schematic editor and module descriptions
From: "Stefano M" <stefano.mora@antispam.libero.it>
Date: Thu, 18 Apr 2002 14:40:47 +0200
Links: << >>  << T >>  << A >>
Hi everybody,
i'm using WebPack by Xilinx and in particular the
Schematic Editor.
How can i draw (and how can i specify) grafically
a 4-bits vector starting from a 8-bits vector ?

Where i can find a description of some library
modules ? Example: what's the difference between
CC8CE and CB8CE counters ?

Thanks a lot !
Bye
--
Stefano Mora
email: stefano.mora@*libero.it
(remove *)



Article: 42198
Subject: Re: 8051 Core for Motor Electronics
From: "Steffen Thieringer" <steffen.thieringer@nmb.co.uk>
Date: Thu, 18 Apr 2002 14:41:32 +0200
Links: << >>  << T >>  << A >>

"Russell" <rjshaw@iprimus.com.au> wrote

> How about just using a smaller fpga as a dedicated pwm/timer peripheral
> for a cpu. Better still, a motor control dsp.

sure, a motor control dsp solution is better, but not done in 10 minutes.
i need a driver now, and for the changeover (8051-hardware to dsp-hardware)
i want to go for the 8051 software.

the way to go for a speeded up 8051 ip-core is for using a program which has
done the job very well on 8051 hardware, but became obsolete because of
speed.

Any suggestions? ;-)

Tnx



Article: 42199
Subject: Re: 1000 I/O Pins -- What is cheapest FPGA?
From: "Steffen Thieringer" <steffen.thieringer@nmb.co.uk>
Date: Thu, 18 Apr 2002 14:46:24 +0200
Links: << >>  << T >>  << A >>

"UK Gary" <deton8@aol.com> schrieb im Newsbeitrag
news:a9m9g1$28d$1@helle.btinternet.com...
> I need to design something where the FPGA must have about 1000 I/O pins.
> What is my cheapest option?  The design must fit into a single FPGA, but
> apart from that and the pin count I don't have any special requirements.

Upcoming Altera Stratix devices do have more than 1000 I/O (up to 1310)!

http://www.altera.com/products/devices/stratix/overview/stx-overview.html

Have phun to design that ;->>>>

Steffen




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