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Messages from 42300

Article: 42300
Subject: Re: Xilinx Easypath- Selling parts with known defects
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Fri, 19 Apr 2002 13:33:52 -0700
Links: << >>  << T >>  << A >>
Jay,

Not so fast....

The devices have a custom test program that assures the part will meet all
requirements at speed for the intended application.

Who bothers to look for the bits that don't get used by the application?
That would be really hard to do, and cost a lot of money, and take a lot
of time.

Austin

Jay wrote:

> I was wondering when someone was going to do this.  Correct me if I'm
> wrong but basically the way this works is Xilinx screens parts at
> wafer probe with known defects against a particular design's P&R to
> see if it's fucntion would be adversly effected.  If it isn't, then
> the part can be delivered and guaranteed to work for this particular
> design.  Xilinx gets to sell silicon that would otherwise be discarded
> (or sold as engineering versions with an erratta sheet) and the
> customer gets some cost break on his mature application.
>
> I guess you still have to use the config parts as always, and you've
> given up the field upgradability benefits touted for FPGA based
> designs but for some applications this could really work.
>
> As an extension of this program, I'd like to these parts made
> available for sale in small quantity without the NRE charges and an
> RLOC file that goes with the serial number of the part or something
> like that to be included in the P&R to work around.  The chips can be
> like diamonds where the price varies depending on the amount of
> defects from "flawless", to "slight inclusions".  You buy what you
> need.


Article: 42301
Subject: Re: 1000 I/O Pins -- What is cheapest FPGA?
From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver)
Date: Fri, 19 Apr 2002 20:38:44 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <a9poom$5dgo4$1@ID-84877.news.dfncis.de>,
Falk Brunner <Falk.Brunner@gmx.de> wrote:
>"Georg Acher" <acher@in.tum.de> schrieb im Newsbeitrag
>news:a9pal7$fao$2@sunsystem5.informatik.tu-muenchen.de...
>
>> I wonder how this can be done (technically)... How do you permanently
>program
>> the chips? I remember vaguely a similar offer for the XC4k-series a while
>ago...
>
>AFAIK they dont. They just test the parts (LUTs/BRAM/interconnects) used by
>the design and leave the rest untested. Saves a lot of money.

The other option is having the defect detection process (using
effectively BIST strategies) produce a defect map, and you use the
parts who's defect map is compatable.

-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 42302
Subject: Re: Xilinx Easypath- Selling parts with known defects
From: "Steve Casselman" <sc.nospam@vcc.com>
Date: Fri, 19 Apr 2002 20:46:55 GMT
Links: << >>  << T >>  << A >>
What they need is a little ROM like purge map that they laser burn at the
factory. They find some defects they just need to list them in the purge map
and have a download cable read that info out.  This would allow Xilinx to
sell the really large parts for a really low price. Bitstreams developed for
a flawed part would run a perfect chip because it is a subset.


Steve Casselman
www.vcc.com
Try Hotman - The Internet bitstream deployment tool.



> As an extension of this program, I'd like to these parts made
> available for sale in small quantity without the NRE charges and an
> RLOC file that goes with the serial number of the part or something
> like that to be included in the P&R to work around.  The chips can be
> like diamonds where the price varies depending on the amount of
> defects from "flawless", to "slight inclusions".  You buy what you
> need.



Article: 42303
Subject: Re: 1000 I/O Pins -- What is cheapest FPGA?
From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver)
Date: Fri, 19 Apr 2002 20:49:00 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3CC028CE.2CEBCABC@xilinx.com>,
Austin Lesea  <austin.lesea@xilinx.com> wrote:

>   easy path does not map around 'bad logic'.  You send us your
> stable design, and we send you chips marked just as ASICs are marked
> that are 100% good at speed for your application.  That is why it is
> so easy!  Customer does nothing, except make a committment to buy X
> units, non-refundable, non-returnable....hey just like an ASIC.  The
> big difference?  About a million $ for the NRE for the ASIC,
> compared with our NRE for the test program, supply management, and
> marking.  Oh, and no time delay, and no risk.

Err, damn, that's what I MEANT to say.  But I'd rahter have a defect
mapped part, and map around my design.  :)
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 42304
Subject: A new experiment
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 19 Apr 2002 22:50:14 +0200
Links: << >>  << T >>  << A >>
Power network measurement made easy

digital.burned-fuses.de


--
MfG
Falk




Article: 42305
Subject: Re: Xilinx Easypath- Selling parts with known defects
From: Johann Glaser <Johann.Glaser@gmx.at>
Date: Fri, 19 Apr 2002 23:53:01 +0200
Links: << >>  << T >>  << A >>
Hi!

> As an extension of this program, I'd like to these parts made available
> for sale in small quantity without the NRE charges and an RLOC file that
> goes with the serial number of the part or something like that to be
> included in the P&R to work around.  The chips can be like diamonds
> where the price varies depending on the amount of defects from
> "flawless", to "slight inclusions".  You buy what you need.

Would it be possible to offer medium size and large size parts (like
XC2S200, ...) for hobbyists, prototyping (or even production) at a really
low price, but with some small errors. E.g. that one or several (of the
many available) CLBs are defect.

For hobbyists it is not a problem if they can't use one of these, but the
high prices are a problem.

Without first knowing the design to test the parts against it. Only
specify parts' errors and then sell them (or give them to the sample
department :-) ).

Is it worth the additional effort on testing to sell cheap parts?

Bye
  Hansi

Article: 42306
Subject: Re: 1000 I/O Pins -- What is cheapest FPGA?. What about Route and place needs
From: =?iso-8859-1?Q?Cyrille_de_Br=E9bisson?= <cyrille_de-brebisson@hp.com>
Date: Fri, 19 Apr 2002 16:20:44 -0600
Links: << >>  << T >>  << A >>


Hello,

As we are talking about really big FPGA here, I have a question related to that. 
How much memory is needed on the computer that will run the place and route algo 
to handle a 4/5Mgates design in a 6Mgates FPGA? If I ask if I can use my PC, will 
I get laugh at? what configuration should I have to do that?

regards, Cyrille


  "Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3CBF331E.4BA38EE5@xilinx.com...
  Nicholas, 
  Don't forget about the EasyPath program:  up to 70% off for a part that does exactly what you want it to do. 

  For details: 

   http://www.xilinx.com/prs_rls/silicon_vir/0248easypath.html 

  As for commenting on yield, that is considered Proprietary and Confidential. 

  I will say that in 12" fab, in a few months, the yield will be much improved (from 
  whatever it is today - 'good' or 'bad' - do not assume anything, as it is nothing 
  but idle speculation, or unfounded rumors from disgruntled competitors). 

  Intel already announced that fab in 12" resulted in better gross margins.  No secret here. 

  That is why it is always a safe bet to wager that the present technology will be the 
  least expensive in time. 

  Otherwise, why would we be so hell-bent on shrinking geometries? 

  Check out the finanical news for Xilinx for last quarter:  that will give some 
  insight into the comments above. 

  Austin 
    
    

  Nicholas Weaver wrote: 

    In article <1019161867.29969.0.nnrp-13.9e9832fa@news.demon.co.uk>, 
    Tim <tim@rockylogic.com.nooospam.com> wrote: 
    >Jay wrote: 
    > 
    >> So you're talking basically about an XC2V6000.  We've been paying 
    >> several thousand dollars each for these. 
    > 
    >Somewhere around $2000?  Is anyone using these in volume? 
    > 
    >Does anyone have a projection on when these parts go below 
    >$1000 (in hundreds, not thousands)?  How about $500? 
    Probably never, those things are BIG. 

    According to what I've heard, if xilinx can yield 3/wafer, they have 
    customers who'd buy them.  Which, by delidding the largest chip, gives 
    you an idea of the defect density of the process they are using. 

    At a few thousand $$$/wafer for just manufacturing, I doubt you will 
    ever get the parts to drop THAT much in price, even in large volume. 
    -- 
    Nicholas C. Weaver                                 nweaver@cs.berkeley.edu




Article: 42307
Subject: Re: ModelSim closes for unknown reason
From: kayrock66@yahoo.com (Jay)
Date: 19 Apr 2002 15:57:45 -0700
Links: << >>  << T >>  << A >>
In 5.4 of Modelsim PE I had similar behaviour that ended up being
caused by improper port connections.  Try loading your design starting
with a lower level of heirarchy and keep moving up untill it crashs,
then check ports.

Regards

"Phil Connor" <p.connorXXX@optionYYY.com> wrote in message news:<a535fee1911fb52170c541c52125287d.58911@mygate.mailgate.org>...
> I'm using ModelSim XE. 
> 
> On starting the simulation it goes through all the loading up 
> process OK and then closes with the message below :-
> 
> 
> Internal error : bad pointer access ........... Closing vsim
> vsim is exiting with code 11
> Trouble with peer processes (0), exiting.
> 
> Anybody seen/solved this one.
> 
> Maybe my design is to big for XE at 27k statements??? Would it
> bomb out in this way?
> 
> Thanks !
> 
> Phil
> 
> PS.
> 
> Why don't software packages give a website reference to a list
> of error messages with a longer and less cryptic explantation
> of what the error message means.
> 
> eg.  "Error Code 1175 see www.mentor....."

Article: 42308
Subject: Re: 1000 I/O Pins -- What is cheapest FPGA?. What about Route and place
From: John_H <johnhandwork@mail.com>
Date: Fri, 19 Apr 2002 23:09:36 GMT
Links: << >>  << T >>  << A >>
If you don't have a care about the thousands of dollars for a single
device, why are you concerned about the development system cost?

Is this perhaps a quantity one design?

And wasn't the logic utilization almost a non-issue, all you needed was
pin count?  If so, you should only need a few 100kgates to get done what
you need done, right?


Article: 42309
Subject: Re: Source code for a NIOS instruction set simulator?
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Sat, 20 Apr 2002 01:10:25 +0100
Links: << >>  << T >>  << A >>
Mark Aaldering wrote
>
> For what it's worth - the Xilinx MicroBlaze development kit *does*
> include a cycle accurate instruction set simulator.
> Thus cycles, and user designated Hz (0 to 150Mhz), yields real clock time.

At 0Hz.  Impressive :-)




Article: 42310
Subject: Re: fpga limitation
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Sat, 20 Apr 2002 01:13:38 +0100
Links: << >>  << T >>  << A >>
Jay wrote
> How do you take this into account in your IOB's?  In an ASIC you can
> ripple the timing of the outputs so they don't all slam all at once
> but more of a cascade fashion.  The whole point of the FPGA output
> flop in the IOB is to reduce "clock to out" time and this a constant
> in an FPGA for a particular output configuration.

Even if they are not quite as represented in the CAD tools,
I guess the clock paths do run along the edges, giving a timing
'ripple' of a crucial few ps.





Article: 42311
Subject: Re: Xilinx Programmable World 2002 - Review
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Sat, 20 Apr 2002 01:22:15 +0100
Links: << >>  << T >>  << A >>
Austin Lesea wrote

> Remote locations vs. the main sites?  We reached ~ 10,000 people,
> and I have to believe some of them are on this newsgroup.

No use for either Colorado Springs or the UK.  Still, it does
not sound as if much was missed.  Now if X only had the consultants'
briefings of old...

BTW, could you pls post a pointer to a recent X paper on power
dissipation in VirtexII.  I saw a mention of it in EETimes around
a month ago.  The conclusion was along the lines of 'routing burns
more than logic'






Article: 42312
Subject: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Sat, 20 Apr 2002 01:25:47 +0100
Links: << >>  << T >>  << A >>
Hi Ben

Could you experiment with cross-posting to c.l.VHDL,
c.l.Verilog, c.a.fpga, rather than three posts to be downloaded
and scanned.

VhdlCohen wrote <lots, trimmed>




Article: 42313
Subject: Re: Source code for a NIOS instruction set simulator?
From: crob714@yahoo.com (crob)
Date: 19 Apr 2002 17:31:27 -0700
Links: << >>  << T >>  << A >>
Mark,

How can you get "real clock time"  when your peripherals are not taken
into account in the simulation?  Are you saying they don't affect
system performance?

This is the key feature of using Modelsim to simulate your whole
system, peripherals and software are siumulated together, showing how
each affects the other.

c-rob


Mark Aaldering <Mark.Aaldering@xilinx.com> wrote in message news:<3CC0684E.24473151@xilinx.com>...
> For what it's worth - the Xilinx MicroBlaze development kit *does* include a cycle accurate
> instruction set simulator.
> Thus cycles, and user designated Hz (0 to 150Mhz), yields real clock time.
> 
> Of course you may also use Model Tech - but you are not forced to do this to get the real execution
> time of your program.
> 
> Matthew Mahr wrote:
> 
> > The instruction set simulator has no awareness of the actual hardware
> > environment, and thus does not give you an accurate idea how long your
> > code takes to execute in real hardware.
> >
> > Matthew
> >

Article: 42314
Subject: was: NIOS ISS, MicroBlaze Cycle Accurate ISS
From: Mark Aaldering <Mark.Aaldering@xilinx.com>
Date: Fri, 19 Apr 2002 18:19:51 -0700
Links: << >>  << T >>  << A >>
C-rob,

Hmmmm - Peripherals don't by default cause the processor pipeline to stall....unless I'm missing
something about nios.

They could be: Polled, Interrupt Driven, DMA oriented, Share Dual port with semaphores, etc, etc.

Having done Processors before PLDs in my career - it is occasionally important to software developers to
know how fast the code will run - especially if there is a critical code section. And running a hardware
simulator is clearly slower than a cycle accurate ISS, and probably a tad less intuitive to a software
developer than using GDB with the cycle accurate simulator to get a fix on Real Time.

That all said - with the MicroBlaze MDK, you do get the ability to do both - so if for some reason you've
built your system to stall when data from a peripheral is not ready - you can figure that out too.

- Mark

crob wrote:

> Mark,
>
> How can you get "real clock time"  when your peripherals are not taken
> into account in the simulation?  Are you saying they don't affect
> system performance?
>
> This is the key feature of using Modelsim to simulate your whole
> system, peripherals and software are siumulated together, showing how
> each affects the other.
>
> c-rob
>
> Mark Aaldering <Mark.Aaldering@xilinx.com> wrote in message news:<3CC0684E.24473151@xilinx.com>...
> > For what it's worth - the Xilinx MicroBlaze development kit *does* include a cycle accurate
> > instruction set simulator.
> > Thus cycles, and user designated Hz (0 to 150Mhz), yields real clock time.
> >
> > Of course you may also use Model Tech - but you are not forced to do this to get the real execution
> > time of your program.
> >
> > Matthew Mahr wrote:
> >
> > > The instruction set simulator has no awareness of the actual hardware
> > > environment, and thus does not give you an accurate idea how long your
> > > code takes to execute in real hardware.
> > >
> > > Matthew
> > >

--
Mark Aaldering
Sr. Director IP Solutions Division
Xilinx.com



Article: 42315
Subject: Re: Xilinx Programmable World 2002 - Review
From: "MatrixGear" <replytogroup@nodamnspam.please.org>
Date: Sat, 20 Apr 2002 01:55:25 GMT
Links: << >>  << T >>  << A >>
Hi,

I as well did not find the presentations technical enough, luckily you guys
have another event coming up next month that promises to be more technical
(Xfest). I will definitely attend this.

Regardless, I had a fun time at the event and came away convinced that FPGAs
are the way to go for systems design.

My favorite speaker of the day was Howard Charney from Cisco, his speech
made me very excited about what I do for a living. He was a very powerful
speaker.

I am looking forward to designing with the Virtex-II Pro.

Michael




Article: 42316
Subject: Announce: non_overlapping_clocks script for TimingAnalyzer
From: d2fabrizio@aol.com (D2fabrizio)
Date: 20 Apr 2002 04:14:19 GMT
Links: << >>  << T >>  << A >>
Hi,

non_overlapping_clocks.bsh, a script program
for the TimingAnalyzer program shows how to
add Delays from a script.

It draws 2 phase non-overlapping clocks which
are commonly described in VLSI Design texts.

Look under scripting examples, of course at:

http://members.aol.com/d2fabrizio

Regards,
Dan Fabrizio



Article: 42317
Subject: Re: Source code for a NIOS instruction set simulator?
From: "Mats Brorsson" <Mats.Brorsson@imit.kth.se>
Date: Sat, 20 Apr 2002 06:00:25 GMT
Links: << >>  << T >>  << A >>
Thanks all who answered this, privately as well as to the group.

I found what I was looking for in the source code for the GNUPrpo toolkit
for Nios. To use a full-fledged simulation model and Modelsim would of
course give me all the timing I need, but I only need a functional simulator
that the students can use to functionally verify their programs. Remember,
I'm bot doing this for a hardware design course, but for a computer
organization course which includes some assembler programming.

I will need to complement the instruction set simulator with something that
functionally simulates our hardware platform, including peripherals.
However, I've done that before so that should be simple. I could have
written the ISS also, but if there were some source code out there, as it
turned out, I could just as well use it.

Best regards

    Mats

"Matthew Mahr" <mmahr@altera.com> wrote in message
news:439a43f3.0204190951.322627ff@posting.google.com...
> > would then like to have an instruction set
> > simulator for this processor. With the Altera Excalibur NIOS development
kit
> > there is a simulator, but I can't find the source code for it.
>
> I have two suggestions:
>
> 1) The source for the GNUPro toolkit for Nios is at ftp.altera.com.
> Login as "doc", password "degree".  You'll find the files easily.
>
> 2) I highly recommend using the simulation features provided by SOPC
> Builder.  SOPC Builder outputs HDL (ie- a full simulation model) for
> your Nios system, it automatically generates a testbench to initialize
> your memories & stimulate your Nios system, and it automatically
> generates a ModelSim project environment.  There is no learning curve
> to get a basic simulation of your real Nios system booting code in
> ModelSim.  See Altera's App Note 189 for complete documentation.
>
> The instruction set simulator has no awareness of the actual hardware
> environment, and thus does not give you an accurate idea how long your
> code takes to execute in real hardware.  If that's what you need, then
> great.  On the other hand, a simulation in ModelSim will tell you
> EXACTLY how your hardware will behave, as well as how many clock
> cycles it takes your software to execute.  You can watch the
> instruction stream for your software issue through the CPU, and see
> all data transfered between processor and peripherals.
>
> Of course, you'll need ModelSim.  If you purchase a subscription to
> Quartus II, then you already have a license for ModelSim Altera
> Edition, and you're ready to go.
>
> Hope this helps.
>
> Matthew
>
>
>
> "Mats Brorsson" <Mats.Brorsson@imit.kth.se> wrote in message
news:<a9gnr5$3f7$1@news.kth.se>...
> > Hi,
> >
> > I'm considering using the NIOS processor from Altera for lab exercises
in a
> > computer organization course and would then like to have an instruction
set
> > simulator for this processor. With the Altera Excalibur NIOS development
kit
> > there is a simulator, but I can't find the source code for it. Anyone
knows
> > of another simulator for this architecture?
> >
> > Please respond by email since I do not regularly read the news groups.
> >
> > Regards
> >
> > Mats Brorsson
> > Mats.Brorsson@imit.kth.se



Article: 42318
Subject: Re: Xilinx Programmable World 2002 - Review
From: remi-seglie@infonie.fr (RS)
Date: 19 Apr 2002 23:17:04 -0700
Links: << >>  << T >>  << A >>
I attend to PW2002 in Paris. I quite agree with Greg and the feeling I
had, is that it was a bit too a "marketing show". I'd appreciated to
have more "technical" info. However I had interesting informations and
perhaps the most interesting was to meet Xilinx people
(distributor/rep/FAE) and others people who have common questions, to
learn a bit about their methods, etc.
I've preferred the day in november 2000 (at Versailles, France) where
technical people ask about our needs, what we think about their new
products... Yes it's "marketing" to learn about client feeling, but I
think I learn more things.

Rémi.

Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3CC03E94.88E21D74@xilinx.com>...
> Greg,
> 
> Thank you for your honest comments.
> 
> Anyone else out there wish to provide us with some feedback?  Too techie?  Too
> marketing?  To Rah Rah Rah?
> 
> Just because some of us are wildly excited doesn't mean that others are.  I
> understand that.  In fact, since I have been working on Virtex II Pro for more than a
> year now (old news for me), I was a more than a little suprised by the numbers
> attending, and the success of the event.  In retrospect, I realize the revolutionary
> product that it is, and I am exciting about its future.
> 
> Remote locations vs. the main sites?  We reached ~ 10,000 people, and I have to
> believe some of them are on this newsgroup.
> 
> If you feel that you do not want your comments in the public eye, I will respect
> that, and you can send them to Peter or myself directly.
> 
> We are likely to do this again, and we strive to always be improving.
> 
> Thanks,
> 
> Austin
> 
> 
> 
> Greg Neff wrote:
> 
> > On Thu, 18 Apr 2002 16:57:21 -0700, Peter Alfke
> > <peter.alfke@xilinx.com> wrote:
> >
> > (snip)
> > >Within Xilinx, I am known to be the harshest critic of marketing BS in public
> > >seminars, and I have ( successfully?) fought for more and more technical "meat".
> > >
> > >Originally, I had been concerned about PW2002, therefore I attended in San
> > >Jose.  And I came away excited, happy, and even proud.
> >
> > In San Jose you could pick and choose which technical training tracks
> > to attend.  In Toronto we were shown four preselected videos.  The
> > rational for this is obvious, but it results in my experience being
> > much different than your experience.
> >
> > Also, you have to put yourself in the shoes of an engineer that has
> > little or no knowledge of VirtexII Pro.  If you were in this position,
> > how much would you have learned at PW2002?  If you have not yet seen
> > the IBM (C1) track then I suggest you do.  I think you will appreciate
> > my frustration with this presentation.
> >
> > (snip)
> > >Having won the attention, and perhaps even the hearts and minds of most design
> > >engineers, we now face a new challenge: We have to convince engineering and
> > >corporate management to change their mindset, to adopt multi-gigabit
> > >transceivers and on-chip PowerPC for their next-generation designs.  Or to give
> > >up on ASICs. And in the larger companies, such decisions are usually not made at
> > >the design engineer's level. So we have to sell our capabilities higher up  the
> > >corporate ladder.
> > >FPGAs are not glue-logic anymore, they are now part of high-impact
> > >architectural, system-level, and business decisions. So we have to change the
> > >tone of our story, to appeal to a new audience.
> >
> > As I said, it was clear that the target has shifted away from the
> > engineer.  If that's what Xilinx wants to do then that's fine, but
> > this reduces the value of the presentation to me, since I am concerned
> > with the technical aspects.  Since Xilinx listed engineers in the "who
> > should attend" list, I expected the same level of technical content as
> > was in previous seminars.
> >
> > >
> > >We still have lots of detailed technical info, app notes, cores, books and CDs
> > >and also training sessions and FAEs, ready to explore the finer details; and
> > >many of these details are really utilized by the software automatically.
> >
> > I agree whole-heartedly.  My issue here is only with PW2002.
> >
> > >
> > >So, please, keep coming to our Seminars and Events, but also use all the other
> > >ways to inform yourself about Xilinx products and solutions. The era of FPGAs
> > >has just begun...
> >
> > Maybe Xilinx needs to have two different seminars.  Something like
> > PW2002 for managers, and then in-depth technical presentations for
> > engineers.
> >
> > >
> > >BTW, we just finished a great quarter, increasing our sales 20%
> > >quarter-to-quarter, thanks to satisfied customers, like the ones in this
> > >newsgroup. We weathered the storm without any lay-offs, just with
> > >belt-tightening.  That's something to be proud of, and thankful to you, our
> > >customers.
> >
> > I have always liked Xilinx technology, and I have no desire to change.
> > Xilinx competitors are always knocking on our door, and we always turn
> > them away.
> >
> > PW2002 rubbed me the wrong way, and I heard other attendees grumble as
> > well.  Xilinx should know this, and that's why I posted my review.
> >
> > (snip)
> >
> > ===================================
> > Greg Neff
> > VP Engineering
> > *Microsym* Computers Inc.
> > greg@guesswhichwordgoeshere.com

Article: 42319
Subject: Re: ModelSim closes for unknown reason
From: prasadkdnvs@rediffmail.com (K PRASAD)
Date: 19 Apr 2002 23:18:50 -0700
Links: << >>  << T >>  << A >>
kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0204191457.116c47fb@posting.google.com>...
> In 5.4 of Modelsim PE I had similar behaviour that ended up being
> caused by improper port connections.  Try loading your design starting
> with a lower level of heirarchy and keep moving up untill it crashs,
> then check ports.
> 
> Regards
> 
> "Phil Connor" <p.connorXXX@optionYYY.com> wrote in message news:<a535fee1911fb52170c541c52125287d.58911@mygate.mailgate.org>...
> > I'm using ModelSim XE. 
> > 
> > On starting the simulation it goes through all the loading up 
> > process OK and then closes with the message below :-
> > 
> > 
> > Internal error : bad pointer access ........... Closing vsim
> > vsim is exiting with code 11
> > Trouble with peer processes (0), exiting.

> > 
> > Anybody seen/solved this one.
> > 
> > Maybe my design is to big for XE at 27k statements??? Would it
> > bomb out in this way?
> > 
> > Thanks !
> > 
> > Phil
> > 
> > PS.
> > 
> > Why don't software packages give a website reference to a list
> > of error messages with a longer and less cryptic explantation
> > of what the error message means.
> > 
> > eg.  "Error Code 1175 see www.mentor....."

Hai even i am facing the same problem.
sometimes when i simulate the model and try 
to open the source window then the error bad pointer acess comes and 
when i click o.k then the modelsim window will be terminated.
then i will open the wizard again and do the simulation.
can any one help me in this.

regards 
prasad

Article: 42320
Subject: Re: 1000 I/O Pins -- What is cheapest FPGA?
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Sat, 20 Apr 2002 07:52:45 -0000
Links: << >>  << T >>  << A >>
Interesting discussion.  Thanks.  Somehow I missed the initial
announcement.

Of course, I've never worked on any stable designs so I don't see
how to take advantage of this yet.

I wonder how much of the cost reduction is due to increaded yield
and how much is due to reduced time on the tester.



>The other option is having the defect detection process (using
>effectively BIST strategies) produce a defect map, and you use the
>parts who's defect map is compatable.

Keeping track of defects at too fine a grain seems like an invitation
for piles of buggy software.

What fraction of the defects are within a CLB as compared to in the
routing?  Or perhaps what fraction are within a CLB and the routing
dedicated to that CLB?  If it's reasonable to identify a CLB or few
of them, then I think such chips would be very interesting for
hobby/experimenting.  Just tell the placer to reserve those CLBs
or force some dummy logic there...

[I'm assuming the dead CLBs would be listed in a ROM that would
be updated by laser during testing, or something similar.]

They might even be useful for production.  Suppose you get chips
that have 1 dead CLB and it is located randomly.  If your design
uses 75% of the CLBs, then you could get away with 4 different
bit patterns to load - just let the update software pick the right
one.  (It might be easier to get complete coverage by making 10
designs rather than trying to squeze things into 4.)

Note that this works for field upgrades as well as factory loading
the flash - as long as the upgrade software can find out where
the dead CLBs are.

Things get more complicated if you have 2 dead CLBs on a chip.  But
it might work for projects that have very low utilization.  (But
why would anybody do that?  There is always something useful that
you can toss into that empty space. :)

Multiple dead CLBs would work for very low volume applications,
say special lab equipment.  Just keep track of the dead CLBs in
each chip and run the placer/router again for each one.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 42321
Subject: Re: fpga limitation
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Sat, 20 Apr 2002 08:06:11 -0000
Links: << >>  << T >>  << A >>
> The reverse geometry is better, and the inter-digitated
> caps are even better.

Both are expensive.  Any indeas on how to get good bypassing
at good costs?


This brings up a question I've been meaning to ask...  Some big BGAs
have a hole in the center.  From a board layout viewpoint, that
leaves a great place to put bypass caps.  Assuming I need x pins,
how does a BGA with a hole compare with a dense BGA after it gets
on the board and we add bypass caps? (and everything else that
real designs need)

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 42322
Subject: 4.2 Webpack error
From: Russell <rjshaw@iprimus.com.au>
Date: Sat, 20 Apr 2002 11:54:31 GMT
Links: << >>  << T >>  << A >>
Hi,

When i 'synthesize' the attached vhdl code in xilinx webpack, why
do i get this error? :

Compiling vhdl file C:/Wave/globals.vhd in Library work.
ERROR:HDLParsers:340 - C:/Wave/globals.vhd Entity <globals> does not
exist in library <work>.

Is there a free leonardo version for xilinx devices?


library	ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

package globals is
  function Log2( n:natural ) return natural;
end globals;


LIBRARY	ieee;
USE ieee.numeric_std.all;
use ieee.std_logic_1164.all;

package body globals is

-- purpose: computes the minimum number "m" of
-- bits that can store an unsigned number "n".
function log2(n : natural) return natural is
variable m, p : integer;
begin
 m := 0;
 p := 1;
 for i in 0 to n loop
   if p < n then
     m := m + 1;
     p := p * 2;
   end if;
 end loop;
return m;
end log2;

end globals;

Article: 42323
Subject: Some Questions about Pci configuration.
From: liandongzhang@hotmail.com (liandongzhang)
Date: 20 Apr 2002 05:22:20 -0700
Links: << >>  << T >>  << A >>
Here below is some of my opinions about pci:
pci bios will enumerate all the pci device(include bridges)after reset
or power on, and store the information(a device information tree)about
the pci device and bridge in somewhere of memory(Where ?? the address
is ??)

Then into the second phase i call it configuation. in this second
phase resources(i/o , memory,irq)is allocated to each devie,and the
information tree about pci device and bridge is used in this second
phase.This is done by system not automatically done by bios,but bios
certainly provide all the routines (pci bios (can be called in
protected mode))which are necessary to do these things.

But Linux abandon bios to the maxium degree in order to accommondate
more HaredWare.Though bios has finished device enumeration after power
on, Linux do it itself again in the pci_init()and linux does not use
the bios routines or information in the memory already there,Of course
Linux do The second phase (configuation )too.

Article: 42324
Subject: Re: Xilinx Easypath- Selling parts with known defects
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sat, 20 Apr 2002 14:42:52 +0200
Links: << >>  << T >>  << A >>
"Johann Glaser" <Johann.Glaser@gmx.at> schrieb im Newsbeitrag
news:a9q3it$5enur$1@ID-115042.news.dfncis.de...

> Would it be possible to offer medium size and large size parts (like
> XC2S200, ...) for hobbyists, prototyping (or even production) at a really
> low price, but with some small errors. E.g. that one or several (of the
> many available) CLBs are defect.

Come on, the Spartan-II(E)s are really cheap, have a look at

www.nuhorizons.com

even a poor student can afford them. So I really DONT like to play with a
just partly functioning IC, especially NOT for development. Debugging you
own mistakes is hard enough..

 --
MfG
Falk

P.S. There is no real possibility to get single quantities of the fine
Xilinx parts in germany (for hobby stuff) :-(








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