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Messages from 42400

Article: 42400
Subject: Re: Is the following Spartan-II FG456 package LogiCORE PCI pinout
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Mon, 22 Apr 2002 19:26:01 -0500
Links: << >>  << T >>  << A >>


Russell wrote:
> 
> 
> Out of curiosity, do you need much test gear for doing
> a PCI core? How hard is it to verify it's working right
> in windows?


        I am sure having a logic analyzer or an oscilloscope is
desirable, but there is no way I can afford them now, so all I got is
one prototype card (Insight Electronics Spartan-II PCI card with
XC2S150), ISE WebPACK 4.x, and ModelSim XE-Starter.
Because I don't have neither a logic analyzer nor an oscilloscope, I
have to rely heavily on simulation before firing up the PCI IP core.
Most of the testing I do will be in RTL, but before burning a
Configuration PROM, I always do a post P&R simulation to make sure the
synthesis tool didn't mess up the synthesis.
I do test my PCI IP core against possible cycles that can happen in the
real world, but I also do testing on cycles that may not happen, but are
legal behavior.
So far, when the PCI IP core simulated correctly during a post P&R
simulation, it always worked correctly in all the computers (Only two
though.) I tested it.
However, all the above real world testing was done on DOS, but not on
Windows directly.
It is probably desirable to have at least a logic analyzer, and possibly
a PCI bus exerciser that runs on Windows, but how many people can afford
them if your company doesn't provide them to you?
In my case, I used the free design tools from Xilinx, the PCI card even
with various options cost less than $400, and various books and
specifications cost about $400, so in total, it cost me less than $1,000
to do a working PCI IP core.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 42401
(removed)


Article: 42402
Subject: Re: Post-synthesis simulation
From: ralph <newsbrowser@newsbrowser.net>
Date: Tue, 23 Apr 2002 03:35:08 GMT
Links: << >>  << T >>  << A >>
Itsaso Zuazua wrote:
> Hi, 
> 
>  I have problems when I want to do a post-synthesis pre-place and
> route simulation in Modelsim. I have synthetized a VHDL design in a
> apex20ke (an FPGA family of Altera), and I have obtained another VHDL
> design which is an FPGA-independent netlist ready for place and
> route.This post-synthesis design exported from the synthesis tool give
> me errors when I simulate it. Should I compile another library in my
> work directory,first?Where could I find the entity´s architectures,
> wich are instantiated in this vhdl design?
> 
> 
>       Thanks, a lot.
>                      Itsaso Zuazua

To do post synthesis simulation you need to compile the device
with vendor specific tool and pull out a post synthesis VHDL file
(or maybe edif) along with a timing file (forgot the type of File) anyway
you need to pull both of these files into modelsim to simulate. If
you did your design right, the top level names will not change and
you will be able to pull out alot of the lower level signals. If you
did the design wrong, well everything will change and you will have
to figure out how things are working by looking at the postcompilation
code. You may have to do this anyway. But, some of the internal signals
you named may be embedded in some sort of crazy syntax.



-- 
Return E-Mail address modified for anti-spamming measures

ralphwat-dot-home=at=excite=dot=com


Article: 42403
Subject: Re: Xilinx Easypath- Selling parts with known defects
From: kayrock66@yahoo.com (Jay)
Date: 22 Apr 2002 21:26:01 -0700
Links: << >>  << T >>  << A >>
Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3CC423B5.F1DD9AE0@xilinx.com>...
> Jay,

[snip]

> With EasyPath, there is little reason to ASIC prototype.  How could you justify
> it to your boss?
> 
> Austin

How could I justify it? Easy- A couple reason from a recent project
1) Recurring part cost needs to be $60-$80
2) Contains more random logic than the largest Xilinx can hold
3) Contains more ram than the largest Xilinx has
3) Needs to operate CPU at >100MHz (Xilinx factory numbers exact same
processor is 40MHz)

But Easypath has many excellent applications, just not this one.  Its
really a measure of Xilinx as an innovator to introduce this program
and I will keep it mind when evaluating solutions in the future.

Article: 42404
Subject: Re: Prototyping Boards for Hobbyist CPU/System Designs
From: Thorsten Trenz <ng@trenz-electronic.de>
Date: Tue, 23 Apr 2002 08:46:54 +0200
Links: << >>  << T >>  << A >>
Micheal,

> Can anyone comment, correct, recommend, etc? 

have a look at our new 300k Spartan IIE Development platform.

The board is especially handy for educational purposes, as it is powered 
from and configured via Universal Serial Bus. In addition to the FPGA, 
the board features SRAM and FLASH memory, an LCD display, RS232 and VGA 
ports, as well as about 100 pins for custom expansion.

Besides use in a lab setup, the board is suitable for industrial control
applications. It fits nicely into standard 19" racks, as it comes in the
well-known 160x100mm "Euro" form factor with VG96 connector.

The Spartan-IIe family of devices is supported by the WebPACK software,
which greatly reduces the cost for an appropriate design environment.
Further information on the product may be found here:

http://www.trenz-electronic.de/prod/proden10.htm

Thorsten

-- 
Dipl.-Ing. Thorsten Trenz, Trenz Electronic
Tel.: +49 (0) 5223 41652, Fax.: +49 (0) 5223 48945
Mailto:ng@trenz-electronic.de
http://www.trenz-electronic.de





Article: 42405
Subject: DCM off chip deskew
From: Patrik Eriksson <patrik.eriksson@netinsight.net>
Date: Tue, 23 Apr 2002 07:55:00 GMT
Links: << >>  << T >>  << A >>
My question was/is:

I'm using an DCM to deskew an external clock relative to an internal
clock. The feedback signal is connected through an global clock input
pad. How does the input delay of the feedback signal affect the skew 
between the internal and external clock?

Device: xc2v1500-4FG676C

Xilinx support answered the following:

The return delay to the DLL must be equal to the dealy to the other chip.
If the delay is not the same then the external clock will not appear to 
be deskew.

The delay that the input buffers introduce must be monitored as well.

In a board-level clock deskew; when two different I/O Standard IBUFGs 
for the CLKIN and the CLKFB, the DCM will not lock.

This happens because the maximum phase difference allowed for the DCM to 
work correctly between CLKIN and CLKFB is 100 ps. If the CLKFB and CLKIN 
are using two different I/O standards that introduce a differential 
delay greater than 100 ps, the CLKDLL will not lock or function correctly.

One example is using an IBUFG_LVPECL for the CLKIN and IBUFG for the 
CLKFB. The differential delay in this case is 150 ps; therefore, the DCM 
will not work.

To prevent this, ensure that the maximum phase difference between CLKFB 
and CLKIN is less than 100 ps.


Can anyone help me understand the answer? If the phase difference 
between CLKFB and CLKIN is less than 100 ps I don't need to deskew the 
signals ;-()

Thanks in advance

Patrik Eriksson

-- 
Patrik Eriksson              |  patrik.eriksson@netinsight.net
Net Insight AB               |  phone:  +46 8 685 04 89
Västberga Allé 9             |  fax:    +46 8 685 04 20
SE-126 30 STOCKHOLM, Sweden  |  http://www.netinsight.net


Article: 42406
Subject: Re: Simulating Unisim
From: prv3299@yahoo.com (Paulo Valentim)
Date: 23 Apr 2002 01:03:33 -0700
Links: << >>  << T >>  << A >>
I already got this to work. Thanks for all your help. It turns out it
was a problem totally unrelated. Because I was using FPGA Advantage I
wasn't compiling in microsim. But now it works just fine. Thanks.

    - Paulo

prv3299@yahoo.com (Paulo Valentim) wrote in message news:<5ed45146.0204190606.15737b20@posting.google.com>...
> I am having a tough time trying to simulate the following which was
> coded for the VIRTEX-E:
> 
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
> USE ieee.std_logic_arith.all;
> 
> -- pragma translate_off
> library unisim;
> use unisim.vcomponents.all;
> -- pragma translate_on
> 
> ENTITY clock_4x IS
> -- Declarations
>   port (clk : in std_logic;
>         clk_4x : out std_logic);
> END clock_4x ;
> 
> -- hds interface_end
> ARCHITECTURE rtl OF clock_4x IS
> component BUFG port (I: in std_logic; O: out std_logic);
> end component;
> 
> component CLKDLL port (
>   CLKIN, CLKFB, RST : in std_logic;
>   CLK2X, CLKDV, LOCKED : out std_logic);
> end component;
> 
> component SRL16 port (
>   D, A0, A1, A2, A3, CLK : in std_logic;
>   Q : out std_logic);
> end component;
> 
> signal clk_2x, clk_4xi, clk_4xo, locked, q, q_rst, vcc, gd :
> std_logic;
> BEGIN
>   q_rst <= not(q);
>   vcc <= '1';
>   gd<='0';
>   U0 : BUFG port map (I=>clk_4xi, O=>clk_4xo);
>   U1 : CLKDLL port map(
>     CLKIN=>clk,
>     RST=>gd,
>     CLKFB=>clk_2x,
>     CLK2X=>clk_2x,
>     LOCKED=>locked);
>   U2 : SRL16 port map(
>     D=>locked,
>     CLK=>clk_2x,
>     A0=>vcc,
>     A1=>vcc,
>     A2=>vcc,
>     A3=>vcc,
>     Q=>q);
>   U3 : CLKDLL port map(
>     CLKIN=>clk_2x,
>     RST=>q_rst,
>     CLKFB=>clk_4xo,
>     CLK2X=>clk_4xi,
>     LOCKED=>clk_4x);
> END rtl;
> 
> 
> I cannot use CLKDLLE because Leonardo Spectrum does not support it.
> But anyways, I cannot simulate this. I have compiled the unisim files
> for modelsim SE using the xilinx_lib_4.tcl script with no problems.
> But still when I load the code into Modelsim, it gives me "component
> not bound" warnings and the simluation doesn't work. HELP!!!
> 
>               - Paulo

Article: 42407
Subject: Re: clock management in Virtex-E (DLL)
From: "H.L" <alphaboran@yahoo.no-spam.com>
Date: Tue, 23 Apr 2002 11:27:12 +0300
Links: << >>  << T >>  << A >>

"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:aa116b$6uqfs$1@ID-84877.news.dfncis.de...
> "H.L" <alphaboran@yahoo.com> schrieb im Newsbeitrag
> news:a9ut0b$ne9$1@ulysses.noc.ntua.gr...
>
> > The fast clock has fanout=82 while the divided by 2 clock has
fanout=397,
> > this means that the slow clock has almost 5 times the load of the fast
> > clock? If yes is this very bad? (Timing analyzer reports no timing
errors)
>
> I dont know how strong the buffers (and the net behind) are. From the
first
> sight I would say, that there is a possibility of skew problems, but this
is
> just a rough estimate. Ray Andraka reported problems with skew of ~500ps.
> If you want to transfer data between the clock nets, use a asynchronous
> FIFO, this makes the transfer bullet proof. If you have to transfer
control
> signals, use the opposite clock edge.
>
> > A question for the second DLL you suggested me to remove: how can I
> > eliminate the divided clock's skew if I dont use a DLL to control it?
>
> Good question. I dont know, since AFAIK the DLL cant deskew a divided
clock
> (just a x1 and x2)
>
> > You wrote thay the delay noticed in my post-MAP (and PAR) simulations is
> > owing to the bufg delay (6.44-4=2.4 ns), the 4 in the equation
represents
> > what?
>
> The 4 ns of delay you noted.
>
> > And the last question to clarify things, you say that clk0 and clkdv are
> > (should be) in phase. You mean that despite of the simulation phase
> > difference, in my FPGA these 2 clocks are in phase? Is this delay owing
to
>
> Hmm, If I got you drawing right (better use a fixed font without tabs next
> time), you compare the phase og the 155MHz internal clock BEHIND the clock
> buffer to the CLKDV output of the DLL. This can hardly work, since there
is
> lot of delay in the buffer.

 I cant find out how to send a nice figure :(
the port map of the dll is
clock_dll1 : CLKDLLHF
  port map (CLKIN      => clk155_p,  --the external clock
                 CLKFB      => clk155_int,
                 RST            => GND,
                CLK0          => CLK0,
                LOCKED     => LOCKED,
               CLKDV         => clk2,
               CLK180        => OPEN
              );


clock_feed : BUFG
  port map (I => CLK0,
                 O => CLK155_int  --the internal clk155 clock and the
feedback
           );

clock_div : BUFG
 port map (I => CLK2,
                O => CLK2_INT
                );
The clk155_int (output of the bufg) I want to be in phase with the
clk155_p..in timing simulation these clocks are in phase when I am not using
the SDF file..the clk2_int is phase shifted but that is ok as you explained
me.
When I am using the SDF file I get that the clk155_int has larger phase
difference with the clk155_p than clk2_int !! That is something that I think
is strange

>
> > the way the simulator handles the FPGA delays and not an implementation
> > "problem"?
> > What about the post-PAR simulation I want to run to verify the correct
> > operation of the FPGA, if I have a phase difference between the 2 clocks
> how
> > can I simulate my FPGA correct?
>
> You could leave out the DLL and create the skewed clock on your own.
>
> --
> MfG
> Falk
>
>
>



Article: 42408
Subject: Maximum Usage in a Virtex FPGA
From: "Jock" <ian.mcneil@uk.thalesgroup.com>
Date: Tue, 23 Apr 2002 10:16:30 +0100
Links: << >>  << T >>  << A >>
What is the recommended maximum usage in a Virtex FPGA. I've heard on the
grapevine that more than 80% full will give sub-optimal timing in a typical
design.

I'm using an XCV50 which various between being 99% and 103% of slices being
used (about 20% of these having unrelated logic), depending on how I set
options such as resource sharing, etc.

When I change one function, I find a completely unrelated function will stop
working.




Article: 42409
Subject: Altera error: non-locally static bounds are not supported
From: Buddy Smith <nullset@dookie.net>
Date: Tue, 23 Apr 2002 13:44:26 +0000 (UTC)
Links: << >>  << T >>  << A >>
Has anyone seen this error before?

I'm trying to do something like this:

Signal foo(NUM_UNITS*FOO_SIZE);

foo(unit_num*FOO_SIZE-1 downto FOO_SIZE*(unit_num-1)) <= foo_in;

Assume unit_num is an input.

Is there a way to do something similar?

For now, i've decided to replace foo() with an asynchronous 
lpm_ram_dq...this is for an Altera FP70k board.

Any suggestions?

Thanks,
--buddy
 

Article: 42410
Subject: Re: logic does not work at higher frequency
From: yatiks@yahoo.com (Kumar)
Date: 23 Apr 2002 06:49:48 -0700
Links: << >>  << T >>  << A >>
Phil Hays <SpamPostmaster@attbi.com> wrote in message news:<3CC17DB2.408EB227@attbi.com>...
> Kumar wrote:
> 
> >                   if ( reset = '0' )
>  Missing "then"                         ^^^^^^
> >                       counter <= ( others => '0' );
> >                       output <= '0' ;
> >                   elsif ( enable_pos = '1' ) then
> >                       counter <= data_in ;
> Did you really want to load the counter regardless of clock? 
> Asynchronous load timing is tricky at best.  Unless you really need this
> I'd suggest:
> 
> **********************************
>                   if ( reset = '0' ) then
>                       counter <= ( others => '0' );  
>                       output <= '0' ; 
>                   elsif (clk'event and clk ='0' ) then
>                       if ( enable_pos = '1' ) then
>                           counter <= data_in ; 
>                       elsif ( counter > 0 ) then
>                           counter <= counter -1 ;  
>                       end if ;
> ****************************************
> 
> 
> > The above counter logic works fine for 32 MHz clock frequency .But it
> > doesnot work for64 Mhz clk . 
> 
> How are you testing this?
> 
> 
> > The chip slected is spartan2 series
> > (xc2s30 -5 speed grade ) .I am using FPGA express for impimenting and
> > ModelSim for place and route simulation .
> 
> Using the free XST Web pack I get 8.713 ns clock period and less than 4
> ns setup time, with the suggested modifications to the design.  This is
> using the static timing analyser.

thanks for ur suggesions . I am testing using B5 spartan2  board (
xc2s200 -5pq 208) .The logic works fine for 125 Mhz after place and
route simulation .

regards 
Yathish

Article: 42411
Subject: Factor of 2 problem while using xilinx multiplier core
From: yatiks@yahoo.com (Kumar)
Date: 23 Apr 2002 07:37:18 -0700
Links: << >>  << T >>  << A >>
I am using Core generator from Xilinx ver 4.1 for multiplication of
two
numbers ( 16 bits each) .I am using the core for spartan2 device .
The selection details for generating the core is  as fallows........
Multiplier .......
1)sequencial
2) registered inputs , port A and B width 16 unsighned
3) output hold register (chech box is marked ). clk cycles per input 4
port A input as parallel.
4) output registered hand shake signals all are using (chech box is
marked ).
5)maximum pipelining and asynchronus clear and clk enable .

Then used in the project and I got a factor of 2 problem after
multiplication
i.e; 4 * 4 = 8  or 2 * 2 = 2 etc after  the behavioural  simulation  .

and reults are not coming properly for clk frequency greater than 38
mhz ( observed after place and route simulation )
for clk frequency less than 35 Mhz results are coming as mentioned
above

Can anybody tell me what is happenning ? and also upto what clk
frequency the multiplier
core works properly for spartan2 devices ?

regard 
yathish

Article: 42412
Subject: Re: Xilinx Easypath- Selling parts with known defects
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 23 Apr 2002 08:00:18 -0700
Links: << >>  << T >>  << A >>
Jay,

How much RAM is enough?

Is the 405PPC core in Virtex II Pro fast enough (>300 MHz)?

How much random logic is required?

EasyPath will be there for Virtex II Pro.  We are looking to the future, and answers to these
questions will help us decide future family members.  More data points the better.

Thanks for your comments,

Austin


Jay wrote:

> Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3CC423B5.F1DD9AE0@xilinx.com>...
> > Jay,
>
> [snip]
>
> > With EasyPath, there is little reason to ASIC prototype.  How could you justify
> > it to your boss?
> >
> > Austin
>
> How could I justify it? Easy- A couple reason from a recent project
> 1) Recurring part cost needs to be $60-$80
> 2) Contains more random logic than the largest Xilinx can hold
> 3) Contains more ram than the largest Xilinx has
> 3) Needs to operate CPU at >100MHz (Xilinx factory numbers exact same
> processor is 40MHz)
>
> But Easypath has many excellent applications, just not this one.  Its
> really a measure of Xilinx as an innovator to introduce this program
> and I will keep it mind when evaluating solutions in the future.


Article: 42413
Subject: Re: FPGA Express problems
From: Sasa Bremec <sasa@i-tech.si>
Date: Tue, 23 Apr 2002 17:14:40 +0200
Links: << >>  << T >>  << A >>

Thanks Mike!

I found the answer to my problem, it was a configuration problem the CLK 
pin was connected to standart IO pin, it should be on GCLK pin.


Sash




Article: 42414
Subject: Re: Factor of 2 problem while using xilinx multiplier core
From: acher@in.tum.de (Georg Acher)
Date: 23 Apr 2002 15:27:08 GMT
Links: << >>  << T >>  << A >>
In article <b479edf8.0204230637.7ed6bdf5@posting.google.com>,
 yatiks@yahoo.com (Kumar) writes:
|> I am using Core generator from Xilinx ver 4.1 for multiplication of
|> two
|> numbers ( 16 bits each) .I am using the core for spartan2 device .
|> The selection details for generating the core is  as fallows........
|> Multiplier .......
|> 1)sequencial
|> 2) registered inputs , port A and B width 16 unsighned
|> 3) output hold register (chech box is marked ). clk cycles per input 4
|> port A input as parallel.
|> 4) output registered hand shake signals all are using (chech box is
|> marked ).
|> 5)maximum pipelining and asynchronus clear and clk enable .
|> 
|> Then used in the project and I got a factor of 2 problem after
|> multiplication
|> i.e; 4 * 4 = 8  or 2 * 2 = 2 etc after  the behavioural  simulation  .

What is 1*1? The bit has to be somewhere...

|> and reults are not coming properly for clk frequency greater than 38
|> mhz ( observed after place and route simulation )
|> for clk frequency less than 35 Mhz results are coming as mentioned
|> above
|> 
|> Can anybody tell me what is happenning ? 

I have used a 18*18 parallel signed multiplier and had no problems (except that
you only get a 35bit result due to the two sign bits).

|>and also upto what clk frequency the multiplier
|> core works properly for spartan2 devices ?

The signed 18*18 parallel MUL with maximum pipelining and without the handshaking
options runs easily at 133MHz in an 2s200-6. I used four of them without any RPM
or floorplaing in a FFT (ie. add the RAMs, adders and control logic to these
ressources...). For sequencial, I assume even faster clock rates.

I was really impressed. With that you can build really nice FFT cores on your own
(32768-point complex FFT in about 2.3ms :-)

-- 
         Georg Acher, acher@in.tum.de         
         http://www.in.tum.de/~acher/
          "Oh no, not again !" The bowl of petunias          

Article: 42415
Subject: Floorplanning
From: rjshaw@iprimus.com.au (russell)
Date: 23 Apr 2002 08:31:04 -0700
Links: << >>  << T >>  << A >>
Hi,

Trying to floorplan a hierarchial design done in XST VHDL,
i couldn't really get the hang of, because of the tedious
net names. Previous messages have mentioned that the net
names can change from just a slight modification in the
source code.

There must have been an assumed way the tools were to be
used when the floor planner was being done. I'd guess one
assumption was that schematics were used atleast for the
top level of a hierarchial design.

I was wondering, if i did all the various parts of the
hierarchy as schematic blocks, and just filled in the
simple blocks with vhdl such as state machines, counters,
filters etc, would the end result give an easy to interpret
netlist amenable to sane routing in the floor planner?

After reading lots of C.A.F. messages, it seems the xilinx
floor-planning tools are a bit dated/broken/etc.

Article: 42416
Subject: Virtex 2: Partial Bitstream Generation
From: "Ryan Fong" <rfong@vt.edu>
Date: Tue, 23 Apr 2002 07:49:58 -0800
Links: << >>  << T >>  << A >>
Is it possible to generate partial bitstreams using the Xilinx ISE 4.2i tools, without using the Modular Design tools?  I am interested in run-time partial reconfiguration to change areas of an FPGA while keeping others areas unchanged.

Thanks.

Article: 42417
Subject: Re: Maximum Usage in a Virtex FPGA
From: kayrock66@yahoo.com (Jay)
Date: 23 Apr 2002 08:52:36 -0700
Links: << >>  << T >>  << A >>
My experience has been that once the tool starts packing unrelated
logic, its the beginning of the end.  This happens when the slices
number gets to 100%.

However, if the P&R finishes without error, even if it produces a slow
design, it should be functional (at rated slow speed).  If your
behaviour is varying with P&R then you must be doing something
asynchronous or you are not properly constraining your I/O timing.

Regards

"Jock" <ian.mcneil@uk.thalesgroup.com> wrote in message news:<aa38mo$bgn$1@rdel.co.uk>...
> What is the recommended maximum usage in a Virtex FPGA. I've heard on the
> grapevine that more than 80% full will give sub-optimal timing in a typical
> design.
> 
> I'm using an XCV50 which various between being 99% and 103% of slices being
> used (about 20% of these having unrelated logic), depending on how I set
> options such as resource sharing, etc.
> 
> When I change one function, I find a completely unrelated function will stop
> working.

Article: 42418
Subject: Re: Xilinx Easypath- Selling parts with known defects
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Tue, 23 Apr 2002 18:12:51 +0200
Links: << >>  << T >>  << A >>
"Austin Lesea" <austin.lesea@xilinx.com> schrieb im Newsbeitrag
news:3CC423B5.F1DD9AE0@xilinx.com...
> Jay,
>
> Cellular base stations, routers, switches, load balancers, the list is
endless.
>
> ASIC prototyping?  I actually don't know of any doing that.  Maybe they
are not
> telling me.

I heard, AMD does it. With boards equipped with dozens of your fine
flagships.


--
MfG
Falk





Article: 42419
Subject: problem with coding a bidirectional bus simulation
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Tue, 23 Apr 2002 12:27:46 -0400
Links: << >>  << T >>  << A >>
Hi,
    I am trying to simulate a system with a bidirectional bus.  Half of
the system resides in an FPGA and half resides elsewhere (actually a
second FPGA on a different board).
the data in the testbench is correct but when the output of the UUT is
tristated, the data being generated in the test bench does not show up
in the FPGA.  Thus the FPGA thinks its input is unknown (really
tri-stated), even though the actual value is being determined by the
testbench.

The data is declared as inout std_logic_vector and the tri-state control
line is being generated in the testbench and is declaed as input
std_logic in the UUT.

basicly my logic is as follows

in the testbench

if tristate='1' then
data<= test_bench_data
else
data<="ZZZZZZZZZZZZZZZZ"
end if;

in the UUT

if tristate='0' then
data<= UUT_data
else
data<="ZZZZZZZZZZZZZZZZ"
end if;

Of course these snippets are greatly simplified and don't include the
process lines, etc.

I hope this makes sense, as the actual code is far to complex to try to
attach to this post.  Can anyone help me?

I am using ise 4.1 and have simulated at every level but "Post Place and
Route".

Thanks,
Theron Hicks


Article: 42420
Subject: PAL and GAL
From: info@apeak-systems.com (Apeak)
Date: 23 Apr 2002 09:56:07 -0700
Links: << >>  << T >>  << A >>
Is TIBPAL22V10-7CNT (from TI) the same as GAL22V10C-7LP (from Lattice) ?
Thanks

Article: 42421
Subject: Re: Prototyping Boards for Hobbyist CPU/System Designs
From: "Manfred Kraus" <newsreply@cesys.com>
Date: Tue, 23 Apr 2002 18:59:52 +0200
Links: << >>  << T >>  << A >>
> - Other low cost SpartanII prototype/development/evaluation boards:
> All theses seem to be 200K devices, but none seem to have onboard
> SDRAM.

This is also true for the CESYS boards, but you can connect
external RAM to the expansion connectors.
 www.cesys.com

-Manfred Kraus



Article: 42422
Subject: Input Frequence
From: "Felipe Joffre Romano Renon" <Felipe.Renon@ic.unicamp.br>
Date: Tue, 23 Apr 2002 14:32:59 -0300
Links: << >>  << T >>  << A >>

How i can change frequence input from Kit Excalibur Altera (33Mhz), without
Skew ?




Article: 42423
Subject: Re: Xilinx 4.2i not working on my design
From: Peter Young <Peter.Young@AMIRIX.com>
Date: Tue, 23 Apr 2002 19:08:05 GMT
Links: << >>  << T >>  << A >>
David Frith wrote:
> Hello all
> 
> I've just loaded on ISE 4.2i and the first design I ran through gives me an
> error at ngdbuild. This is with exactly the same input files as 4.1i which
> works fine.
...
> ERROR:NgdBuild:669 - A parsing error has occurred at line 0 while reading
> lsb_opif.ucf. The value is .
> ERROR:NgdBuild:31 - Errors found while parsing .ucf file "lsb_opif.ucf".
> Please
> check for syntax errors in the UCF file. For more information on legal UCF
> constraints, please see the Constraints Guide for more information on this
> attribute.

	We encountered an error like this on one of our machines as we migrated
from 4.1i to 4.2i.  It eventually went away and we weren't 100% sure
why, but what we suspected was that the environment variables got
updated to point to 4.2i, but the path on the PC or the desktop shortcut
was still pointing to the old 4.1i installation.  Double check your
System variables, path, and shortcuts to make sure everything points to
4.2i.
			Pete 
-- 
Peter Young
Hardware Designer
AMIRIX Systems - Halifax, N.S.
(902) 450-1700 ext. 224

Article: 42424
Subject: Re: Xilinx Easypath- Selling parts with known defects
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Tue, 23 Apr 2002 20:22:10 +0100
Links: << >>  << T >>  << A >>
Austin Lesea wrote

> How much RAM is enough?

Dorothy Parker isn't always quoted in full, but as the lady said:
"you cannot be too thin or too rich, or have too much RAM"

Maybe 640K would be enough :-)

Of course, almost any on-chip RAM hugely increases the bandwidth
compared with off-chip memory, so we immesurably better off than
we were five years ago.







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