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Messages from 43825

Article: 43825
Subject: Re: divide by 5
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 04 Jun 2002 12:50:40 +1200
Links: << >>  << T >>  << A >>
John wrote:
> 
> A slightly simpler approach may be to notice that
> 
> 1/5 = 3/16  +  3/256  + 3/4096 + ... 3/(2^(4n))...

 Impressive. Just how did you 'notice' that ?

-jg

Article: 43826
Subject: chipscope
From: "cfk" <cfk_alter_ego@pacbell.net>
Date: Tue, 04 Jun 2002 01:44:44 GMT
Links: << >>  << T >>  << A >>
I am looking for an opinion from a user who has used Chipscope. Is it easy
to setup and get going? Is it quirky or straight forward. Should I invest my
time in understanding its care and feeding or not?

Charles



Article: 43827
Subject: FPGAs used to crack Xbox security
From: John Williams <j2.williams@qut.edu.au>
Date: Tue, 04 Jun 2002 12:30:45 +1000
Links: << >>  << T >>  << A >>
Hey folks, 

The linked article contains a link to a tech report describing how an
enterprising student used a Virtex-E to sniff a bus inside the Xbox
console and figure out the secure kernel encryption algorithm.  

(mind the wrap)
http://msnbc-cnet.com.com/2100-1040-931296.html?type=pt&part=msnbc&tag=alert&form=feed&subj=cnetnews

There is a certain irony here because the Xbox uses a
security-by-obscurity approach, which was defeated by a $50 FPGA whose
own internals are also protected by "security-by-obscurity".

Hardware sniffing - a new "killer app" for FPGAs?

Regards,

John

Article: 43828
Subject: Re: Looking for FPGA board with USB interface
From: "Kyle Davis" <kyledavis@nowhere.com>
Date: Tue, 04 Jun 2002 02:39:43 GMT
Links: << >>  << T >>  << A >>
I am looking for the board.
I already have Xilinx board (www.digilent.cc), but they used Spartan chip
and I would like to use bigger capacity chip, like the Virtex.
I took a look at Multilinx cable, but I probably wouldn't buy it because it
just too expensive. $465 just for the cable!
If I am going to spend that much money, I would rather buy a complete whole
board with big capacity chip.

"Jay" <kayrock66@yahoo.com> wrote in message
news:d049f91b.0206031114.2553ca05@posting.google.com...
> Are you just looking for a USB download cable (e.g. Xilinx Multilinx),
> or an FPGA protoboard that has a USB connector on it?
>
> "Kyle Davis" <kyledavis@nowhere.com> wrote in message
news:<g%gK8.3805$Zd.261084368@newssvr13.news.prodigy.com>...
> > Hi folks,
> > I am looking for FPGA board that use USB port or IEEE 1394 (Firewire)
for
> > downloading to the chip. My notebook only comes with USB and IEEE1394
port
> > so using FPGA board that only use parallel or serial port won't work!
> >
> > Thanks in advance!



Article: 43829
Subject: Re: FPGAs used to crack Xbox security
From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver)
Date: Tue, 4 Jun 2002 02:40:01 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3CFC2655.7441905F@qut.edu.au>,
John Williams  <j2.williams@qut.edu.au> wrote:
>Hey folks, 
>
>The linked article contains a link to a tech report describing how an
>enterprising student used a Virtex-E to sniff a bus inside the Xbox
>console and figure out the secure kernel encryption algorithm.  
>
>(mind the wrap)
>http://msnbc-cnet.com.com/2100-1040-931296.html?type=pt&part=msnbc&tag=alert&form=feed&subj=cnetnews
>
>There is a certain irony here because the Xbox uses a
>security-by-obscurity approach, which was defeated by a $50 FPGA whose
>own internals are also protected by "security-by-obscurity".

Actually, very little of the Virtex can be conisdered
"security-by-obsucrity", the general bitfile format is
semi-documented, it is fully manipulatable (with Jbits), etc
.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 43830
Subject: Sigma-delta DACs.
From: "Kelvin XCJ" <qijun@okigrp.com.sg>
Date: Tue, 4 Jun 2002 11:34:30 +0800
Links: << >>  << T >>  << A >>
Hi:

I am having a design which requires digital-to-analog conversion.
The digital values are from 0-63, changing at 6MHz. The digital
values are for a psudo-random bit-stream (1MBps) shaped with
sine-wave at transitions. The maximum transition is 8. The maximum
clock I have on my chip is 72MHz. The RC network is constrained
by R < 15Kohm, C < 100pF.

My idea was to quantize the digital signal into 12 levels, then use a
sigma-delta DAC, like the one done by Xilinx...
http://www.xilinx.com/xapp/xapp154.pdf

Anybody have some materials on how to design a sigma-delta DAC?
Anybody can suggest whether I can use integrated RC network and
some digital circuits to design this DAC?

Thanks.

--
Best Regards,
-----------------------------------------------------------------






Article: 43831
Subject: Re: divide by 5
From: "Steve Casselman" <sc_no_spam@vcc.com>
Date: Tue, 04 Jun 2002 04:25:26 GMT
Links: << >>  << T >>  << A >>
One way to do this might be to use one or two of the block rams for a lookup
table to get a first approximation. Then use the arithmetic techniques.

Steve Casselman



"James Horn" <jimhorn@svn.net> wrote in message
news:3cfbf038@news.svn.net...
> Without multiplying per se, consider that to 32 bits, 1/5=858993459/2^32
> (rounded).  The numerator is 3 * 17 * 257 * 65537.  Each of these factors
> has two non-zero bits.  So you get:
> n := n + (n<<1);
> n := n + (n<<4);
> n := n + (n<<8);
> n := n + (n<<16);
> return n>>32;
>
> Of course, rounding and moving the final shift to among the prior four can
> make for a smaller implimentation.  But that's essentially 4 pipelined
> adders.
>
> Jim Horn



Article: 43832
Subject: Re: divide by 5
From: John_H <johnhandwork@mail.com>
Date: Mon, 03 Jun 2002 21:49:41 -0700
Links: << >>  << T >>  << A >>
What's 1/5 in hex?  Grab MS Calculator.  (DEC) 2^32/5 -> HEX ->
33333333.


Jim Granville wrote:
> 
> John wrote:
> >
> > A slightly simpler approach may be to notice that
> >
> > 1/5 = 3/16  +  3/256  + 3/4096 + ... 3/(2^(4n))...
> 
>  Impressive. Just how did you 'notice' that ?
> 
> -jg

Article: 43833
Subject: Re: FPGAs used to crack Xbox security
From: "Matt" <bielstein@attbi.com>
Date: Tue, 04 Jun 2002 05:17:28 GMT
Links: << >>  << T >>  << A >>
And that is why they provided an encypted bit stream option for Virtex2.


"Nicholas Weaver" <nweaver@CSUA.Berkeley.EDU> wrote in message
news:adh9a1$7pc$1@agate.berkeley.edu...
> In article <3CFC2655.7441905F@qut.edu.au>,
> John Williams  <j2.williams@qut.edu.au> wrote:
> >Hey folks,
> >
> >The linked article contains a link to a tech report describing how an
> >enterprising student used a Virtex-E to sniff a bus inside the Xbox
> >console and figure out the secure kernel encryption algorithm.
> >
> >(mind the wrap)
>
>http://msnbc-cnet.com.com/2100-1040-931296.html?type=pt&part=msnbc&tag=aler
t&form=feed&subj=cnetnews
> >
> >There is a certain irony here because the Xbox uses a
> >security-by-obscurity approach, which was defeated by a $50 FPGA whose
> >own internals are also protected by "security-by-obscurity".
>
> Actually, very little of the Virtex can be conisdered
> "security-by-obsucrity", the general bitfile format is
> semi-documented, it is fully manipulatable (with Jbits), etc
> .
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu



Article: 43834
Subject: Re: FPGAs used to crack Xbox security
From: "Matt" <bielstein@attbi.com>
Date: Tue, 04 Jun 2002 05:20:28 GMT
Links: << >>  << T >>  << A >>
I'm guessing that is why Virtex2 has 3DES encryption option for the bit
stream. I plan on using it in future designs. I suspect nothing is fool
proof though.


Matt

"John Williams" <j2.williams@qut.edu.au> wrote in message
news:3CFC2655.7441905F@qut.edu.au...
> Hey folks,
>
> The linked article contains a link to a tech report describing how an
> enterprising student used a Virtex-E to sniff a bus inside the Xbox
> console and figure out the secure kernel encryption algorithm.
>
> (mind the wrap)
>
http://msnbc-cnet.com.com/2100-1040-931296.html?type=pt&part=msnbc&tag=alert
&form=feed&subj=cnetnews
>
> There is a certain irony here because the Xbox uses a
> security-by-obscurity approach, which was defeated by a $50 FPGA whose
> own internals are also protected by "security-by-obscurity".
>
> Hardware sniffing - a new "killer app" for FPGAs?
>
> Regards,
>
> John



Article: 43835
Subject: Re: chipscope
From: "Matt" <bielstein@attbi.com>
Date: Tue, 04 Jun 2002 05:23:36 GMT
Links: << >>  << T >>  << A >>
I have found it to be fairly easy to setup and use. I believe it is a good
thing and use it in conjunction with a test connector. It is improved since
it was first introduced. It does require some of the device resources which
I'm guessing is fine for most designs. I remove it from my final designs but
I suppose you could even use it for production testing.


"cfk" <cfk_alter_ego@pacbell.net> wrote in message
news:gYUK8.18719$RY4.602910011@newssvr21.news.prodigy.com...
> I am looking for an opinion from a user who has used Chipscope. Is it easy
> to setup and get going? Is it quirky or straight forward. Should I invest
my
> time in understanding its care and feeding or not?
>
> Charles
>
>



Article: 43836
Subject: Problem with spartan2 vhdl code
From: frankmotje@hotmail.com (F. Modderkolk)
Date: 4 Jun 2002 00:35:17 -0700
Links: << >>  << T >>  << A >>
If I test the vhdl code with modelsim, it works just fine, but when I
implement it, it doesn't do anything. The function of the code is to
create a puls with a lenght of one clockpuls when I push a button

the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity startertwee is
    Port ( puls : in std_logic;
           pulsuit : out std_logic;
           clk : in std_logic;
           stopenreset : in std_logic);
end startertwee;

architecture Behavioral of startertwee is
signal intern : std_logic;
signal bpulsuit : std_logic;

begin
process (clk)
begin
if clk'event then	
	if stopenreset = '1' then
 		pulsuit <= '0';
		intern <= '0';
		bpulsuit <= '0';
	else 
		if clk  = '1' then
			if puls = '1' and intern = '0' then
				bpulsuit <= '1';
				intern <= '1';
			elsif puls = '0' and intern = '1' then
				intern <= '0';
				bpulsuit <= '0';
			else 
				bpulsuit <= '0';
				intern <= intern;
			end if;
		end if;

		if clk = '0' then
			pulsuit <= bpulsuit;
		end if;
	end if;
end if;
end process;
end Behavioral;


Is there something I forget to program or something I do wrong?
I hope you can help me
thx

Article: 43837
Subject: Re: Looking for FPGA board with USB interface
From: Laurent Gauch <laurent.gauch@amontec.com>
Date: Tue, 04 Jun 2002 10:01:34 +0200
Links: << >>  << T >>  << A >>
May try to use a USB to parallel port cable, there are for $49.

Laurent Gauch

Kyle Davis wrote:

> Hi folks,
> I am looking for FPGA board that use USB port or IEEE 1394 (Firewire) for
> downloading to the chip. My notebook only comes with USB and IEEE1394 port
> so using FPGA board that only use parallel or serial port won't work!
> 
> Thanks in advance!
> 
> 
> 
> 


Article: 43838
Subject: Re: chipscope
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 04 Jun 2002 09:38:43 +0100
Links: << >>  << T >>  << A >>


Matt wrote:

> I have found it to be fairly easy to setup and use. I believe it is a good
> thing and use it in conjunction with a test connector. It is improved since
> it was first introduced. It does require some of the device resources which
> I'm guessing is fine for most designs. I remove it from my final designs but
> I suppose you could even use it for production testing.
>
>

I agree with this. Generally pretty straightforward although the GUI is a bit
clunkey. One bit of advice I got was to avoid the MultiLinx/USB connection and
just use the Centronics Parallel-III cable which ChipScope now supports - the
original version didn't. Maybe USB is better now ...

Beware though that its not as sophisticated as a full blown LA. A couple things
that caught me out

o  Chipscope seems to need a continuously running clock. It doesn't seem
possible to use an async clock to catch some samples, then hit stop before the
buffer's full and view them i.e. no equivalent of an HP LA's ``stop on no
state''.

o There's no ability to apply a filter to samples *before* the trigger. If you
want to do this you'll have to add some extra code yourself.

Finally, I've said this elsewhere, the JTAG connection seems to lose the plot if
there's another compute intensive process running in the background.


Article: 43839
Subject: Re: divide by 5
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 04 Jun 2002 10:35:41 +0100
Links: << >>  << T >>  << A >>


John wrote:

> A slightly simpler approach may be to notice that
>
> 1/5 = 3/16  +  3/256  + 3/4096 + ... 3/(2^(4n))...
>
>     = .0011001100110011001100110011001100110011....
>        ----
>        --------
>        ----------------
>        --------------------------------
>        ----------------------------------------------------------------
>
> First approximation is 3/16, a shift, add, and a shift.
>
> Take result, shift down by four and add again, this gives 8 bits precision.
> Take result, shift down by eight, add again, 16 bits of precision.
> Take result, shift down by sixteen, add again, 32 bits of precision.
>
> Thus Four adds => 32-bits of precision
>
> Five adds => 64 bits ...
>
> This is a general technique that can be used for _any_
> _fixed_ divisor, as there is always a repeating pattern...
> 1/5 is nice illustrative case, 1/3 and 1/7 also work well.
> HTH
>
>

Nice find.

If I've got my maths right in general 1/N can be expressed as a repeating pattern in radix 2**r if
there is a K such that

  N * K = 2**r -1

so N = 11 works with K = 93, r = 10. Is it always possible to do this ?



Article: 43840
Subject: Re: fpga cpu
From: "jerry1111" <jerry1111@wp.pl>
Date: Tue, 4 Jun 2002 12:14:52 +0200
Links: << >>  << T >>  << A >>
> I just don't follow your point.  Either way, it is multiple chips and it
> is one design.  With the soft CPU you have an FPGA, Flash and likely RAM
> along with various analog chips such as power on reset, etc.  With an
> MCU the Flash and RAM are in the chip unless you need huge amounts of
> RAM.  The MCU also comes complete with full power on/off reset (brown
> out) ADC/DAC and other functions as well.  Where is the advantage of the
> soft CPU other than being able to change the CPU instruction set (which
> is VERY hard to support in the compiler, which is where this thread
> started... "how do I get a custom C compiler?").  

Let's say that board containing Nios, Flash, Ram, POR and quick 12bit DAC
is named 'cpu-hybrid'. I can make ONE board, order 50pieces of it (becomes
cheaper than 1) and because of well-made pinout ideology it's VERY simple
to use it in various designs. When I need to change design (add second Nios f.e.)
or make some advanced logic in on-board FPGA, I make changes in Quartus
NOT in board itself. Believe me, it;s simple solution. All cpu-hybrids are compatible,
the only thing I must change from one design to another is the base-board which
has plugged cpu-board (because it's plugged using small connectors, it doesn't
use much space). I've made such a board (featuring Toshiba TLCS900 uP)
3 years ago, I can change to Nios-cpu without much stress.
Everything becomes pin-compatible (well, in Nios-board there is 100pins more,
but I sill can plug it instead of Toshiba-board).
When cpu-board is manufactured once (in quantity > 50 or 100 pcs. it becomes
quite cheap. When I burn the board (sometimes happens....) I can change it
in a minute ;)
This IS the point.
There are multiple chips? So what? As long as board doesn't need
special chips placed on main-board, I'm not seeing that cpu-board contains
'chips'. It contains CPU.

jerry

PS: When I will be making some portable devices not bigger that hand-watch, there will
be point for saving space, but now I'm doing electronics for quite big devices.



Article: 43841
Subject: Re: fpga cpu
From: "jerry1111" <jerry1111@wp.pl>
Date: Tue, 4 Jun 2002 12:17:35 +0200
Links: << >>  << T >>  << A >>
> But if you don't have the budget to support IP cores, how will you have
> the budget to roll your own MCU?  I think all of the things you list as
> being able to add to the CPU, you can still add in the FPGA even if the
> CPU is not in the FPGA.  

But when you want to use 5*uart, 5*timer, 5*edge-sensitive PIO how to connect
it to uC without making glue-logic as for, well, Z80?
You are buying IP-cpu ONCE. So choose it well ;)

jerry



Article: 43842
Subject: VirtexE DLL Output clock phase
From: nimrodm@yahoo.com (Nimrod Mesika)
Date: 4 Jun 2002 03:42:14 -0700
Links: << >>  << T >>  << A >>
We have two VirtexE-2000 that are driven by the same on-board clock
(33MHz). The clock is used to drive the Virtex DLL (ratio 1:1
currently) on both FPGAs.

The question is: are the two clocks generated by the DLLs identical
(up to a small skew)? Can we use one FPGA clock to sample data
generated by the other FPGA safely?

Nimrod.

p.s. the above question is due to a mysterious problem we have that
seem to appear randomly (right after power up).

Article: 43843
Subject: Re: NIOS GNUPro tool chain + SDK for Linux
From: "jerry1111" <jerry1111@wp.pl>
Date: Tue, 4 Jun 2002 12:47:11 +0200
Links: << >>  << T >>  << A >>
> Hi,
> I can't compile the SDK in Cygwin environment. "configure" command is
> correct, but "make install" error reported. Have anybody compiled the SDK?

I'll try to compile during weekend.
BTW: The Cygwin vesion is compiled by Altera and contained in Nios-devkit.

jerry

PS: Milo wiedziec, ze jeszcze jakis Polak uzywa Niosa ;)))



Article: 43844
Subject: Re: FPGA destruction possible?
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Tue, 04 Jun 2002 13:05:53 +0200
Links: << >>  << T >>  << A >>
Hello, Falk!

Falk Brunner wrote:

> ;-)))) Nice phrase. (My design is too good for the technology nowadays )
> If you have a good (optimized) design, wouldnt it dissipate LESS power??

Depends on what you optimize. If you optimize for performance (higher clock
frequency) and FPGA utilization (higher density) you inevitable dissipate much
power. And FPGAs (in opposition to ASICs) do not provide low-power techniques
such as voltage scaling.

> Hmm, no. The IOs of FPGAs are really though guys, even a short for hours
> doest damage them too much, I heard.
> But for a medium sized (lets say 200k gates) FPGA, its hard to overheat them
> with a normal design, unless you turn them into a 10.000 stage shift
> register and clock them with 200 MHz. I did this with a Spartan-II 100,
> draws ~2.7 W, gets real hot in a PQ208 but doesnt melt (at least not after
> 30s of my testing)

30s is not a very long testing time :-)

Regards,

Michael


Article: 43845
Subject: Re: divide by 5
From: Ray Andraka <ray@andraka.com>
Date: Tue, 04 Jun 2002 12:35:48 GMT
Links: << >>  << T >>  << A >>
How accurate do you need?  One possibility is to multiply by
the reciprocal.  In this case, the reciprocal has a nice
repeating bit pattern (common for 1/N's):  11001100...  If
you are multiplying by this, you can get an effective
multiply by a 32 bit representation of 1/5 using just 4
adders, with more accuracy than you have on the 21 bit
input.  If you can get by with a 16 bit representation, you
only need 3 adds.

if the input is a then

b<= (a + 2a)/16  =3a  (1100)
c<= b + 16b = 17b = 51a (11001100)
d<= c + 256c = 257c = 13107a (1100110011001100)
e<= d + 65536d = 65537d = 858993459a
(11001100110011001100110011001100)

858993459/(2^32) =0.19999999995,



Eyal Shachrai wrote:

> does anyone know of an elegant way to divide a number
> of 21 bits by 5 ?
> please note that I'm using xilinx's virtex 2
> and mentor's leonardo for synthesys.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin
Franklin, 1759



Article: 43846
Subject: Re: FPGA destruction possible?
From: Ray Andraka <ray@andraka.com>
Date: Tue, 04 Jun 2002 12:42:30 GMT
Links: << >>  << T >>  << A >>


Falk Brunner wrote:

> "Michael Boehnel" <boehnel@iti.tu-graz.ac.at> schrieb im Newsbeitrag
> news:3CFB4771.F64A2370@iti.tu-graz.ac.at...
> > Hello!
> >
> > Is it possible to kill (thermically destroy) an FPGA by a highly
> > optimized design (hand-placed; high-density; litte unrelated logic)
>
> ;-)))) Nice phrase. (My design is too good for the technology nowadays )
> If you have a good (optimized) design, wouldnt it dissipate LESS power??

Floorplanning does reduce power for a given clock rate, however the decreased
propagation times can lead to higher possible clock rates.  It is possible to
overheat the larger parts with a dense high performance design.  The average
user won't get to that point though.  I have one design on the bench that has to
have heatsinks on V2000E's, but that is a design that is being internally
clocked at 160 MHz, is 85% full, and has some 70% of the LUTs used as SRL16's.
The bottom line is that it is possible to make the bigger parts pretty hot, but
you'll have to work at it to do it.

>
>
> > assuming that interface lines are OK/room temperature?
> >
> > Did anybody observe such a behavior?
>
> Hmm, no. The IOs of FPGAs are really though guys, even a short for hours
> doest damage them too much, I heard.
> But for a medium sized (lets say 200k gates) FPGA, its hard to overheat them
> with a normal design, unless you turn them into a 10.000 stage shift
> register and clock them with 200 MHz. I did this with a Spartan-II 100,
> draws ~2.7 W, gets real hot in a PQ208 but doesnt melt (at least not after
> 30s of my testing)
> With the big guys (1M gates++), there are good chances to fry the FPGA,
> since power density is much bigger.
>
> --
> MfG
> Falk

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 43847
Subject: Re: FPGA destruction possible?
From: Ray Andraka <ray@andraka.com>
Date: Tue, 04 Jun 2002 12:45:34 GMT
Links: << >>  << T >>  << A >>
I have seen floorplanning and design optimization for performance reduce power
fairly consistently by around 15-20%.  Of course, it also reduces propagation
delays which means you can turn the clock up, losing any gains on overall power.
Where you do save is power per transition.

Michael Boehnel wrote:

> Hello, Falk!
>
> Falk Brunner wrote:
>
> > ;-)))) Nice phrase. (My design is too good for the technology nowadays )
> > If you have a good (optimized) design, wouldnt it dissipate LESS power??
>
> Depends on what you optimize. If you optimize for performance (higher clock
> frequency) and FPGA utilization (higher density) you inevitable dissipate much
> power. And FPGAs (in opposition to ASICs) do not provide low-power techniques
> such as voltage scaling.
>

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 43848
Subject: Re: VirtexE DLL Output clock phase
From: "H.L" <alphaboran@yahoo.no-spam.com>
Date: Tue, 4 Jun 2002 15:45:46 +0300
Links: << >>  << T >>  << A >>
In the timing simulation waveforms the derived clocks from the DLL appear to
have a large iming difference relative to the input clock, pick the clk_ipd
from a FF of your design and add it to the simulation waveforms. Compare the
new added signal with the FPGA's input clock, there should have a slight
difference (few ps). Also search in the xilinx.com for DLL timing
simulation.

Harris


"Nimrod Mesika" <nimrodm@yahoo.com> wrote in message
news:9ac14d2b.0206040242.39709502@posting.google.com...
> We have two VirtexE-2000 that are driven by the same on-board clock
> (33MHz). The clock is used to drive the Virtex DLL (ratio 1:1
> currently) on both FPGAs.
>
> The question is: are the two clocks generated by the DLLs identical
> (up to a small skew)? Can we use one FPGA clock to sample data
> generated by the other FPGA safely?
>
> Nimrod.
>
> p.s. the above question is due to a mysterious problem we have that
> seem to appear randomly (right after power up).



Article: 43849
Subject: Re: VirtexE DLL Output clock phase
From: Ray Andraka <ray@andraka.com>
Date: Tue, 04 Jun 2002 12:50:51 GMT
Links: << >>  << T >>  << A >>
The skew between clock domains can be significant, as it is not just
the DLL, but also loading and clock jitter that contribute to the
skew.  I had a problem a few years ago with a virtex design where data
crossing from a 1x to a 2x (or vice versa) domain was beating the
skewed clock.  The biggest contributor turned out to be clock jitter.

I do not advocate direct transfer between the clock domains because of
the potential for design killing skew.  You'll have to come up with a
safer transfer mechanism.

Nimrod Mesika wrote:

> We have two VirtexE-2000 that are driven by the same on-board clock
> (33MHz). The clock is used to drive the Virtex DLL (ratio 1:1
> currently) on both FPGAs.
>
> The question is: are the two clocks generated by the DLLs identical
> (up to a small skew)? Can we use one FPGA clock to sample data
> generated by the other FPGA safely?
>
> Nimrod.
>
> p.s. the above question is due to a mysterious problem we have that
> seem to appear randomly (right after power up).

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759





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