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Messages from 43900

Article: 43900
Subject: Re: FPGA destruction possible?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 05 Jun 2002 19:15:59 +0100
Links: << >>  << T >>  << A >>


John Eaton wrote:

> Falk Brunner (Falk.Brunner@gmx.de) wrote:
> : "John Eaton" <johne@vcd.hp.com> schrieb im Newsbeitrag
> : news:adh2p5$38c$1@news.vcd.hp.com...
> : >
> : > I have it on good authority that connecting a 3.3 volt 1M gate part to a
> : > flakey connector that shorts I/O pads to 5 volts WILL destroy the FPGA.
> : >
> : >
> : > And in the true interest of science the folks that performed that little
> : > experiment then verified that it was reproduceable.
>
> : So they are real scientists. They have reproducable results ;-)
> : More serious, I think overvoltage was not the question here, was it?
>
> -------------------------------------------------
>
> It was latch up. Some 3.3 volt outputs were shorted to +5 and sent the
> whole chip into melt down mode.
>
> We also have a new crop of software engineers who don't fully understand
> how to handle breadboards. You have to really babysit them and be ready to
> kill the power the INSTANT you hear,see,smell,taste or feel anything odd.
>
> The new guys will power them up and then run back to their cube and log
> in remotely to a debug session. About 1/2 hour later somebody will walk
> by and ask them if they know that their breadboards on fire.
>
> John Eaton

Hmmm! Perhaps as part of their training they should have the breadboard in their
cubes until they can convince management that they can distinguish  between the
smells of (a) expensive FPGAs reverting to melted sand + burning FR4 epoxy, (b)
newly arrived pizza. Dousing the cube with a dry power extinguisher on event
(a), if repeated often enough, should have the required effect - in a Pavlovian
kind of way [the pizza will taste *really* bad].

They might, of course, reply that its not their fault as the VC/C++ debugger
doesn't seem to have a ``breadboard on fire'' trap/breakpoint whereas it does,
so I've been lead to believe, have a ``next pizza'' timer.




Article: 43901
Subject: Re: synthesis issue
From: kayrock66@yahoo.com (Jay)
Date: 5 Jun 2002 11:30:13 -0700
Links: << >>  << T >>  << A >>
Just because you code in a structural fashion, doesn't prevent the
synthesis tool from doing any dang thing it wants to your logic on its
way to obtaining your requested optimization of speed and area
(implied).  It can do anything it wants as long as the logical
function of the circuit as observed from the primary I/O is preserved.
 You wanted a circuit that acts like a counter with the LSB inverted,
it gave you one, it just put the inversion on the other side of the
flop.  Probably because CLBs have combo logic followed by flop, and
not the other way around.

Regards

kkdeep@mailcity.com (kuldeep) wrote in message news:<a0f016a9.0206042045.5c1acf9d@posting.google.com>...
> i have a design in hand where i have to give output of a counter to
> some other module after inverting lsb 1.
> The relevent code looks like this. rest of code is purely srtuctural
> --s_out output of counter
> s_lsb <= not s_out (0) ;
> s_out_1 <= s_out(4 downto 1) & s_lsb;
> s_out_1 will be connected to the other module
> 
> but when i see the RTL view,  i cannot see the inverter. The synthesis
> tool somehow (synplicity) optimzes the inverter which is not intended.
> can some body throw some light
> why it happens?
> i took a primary output and assigned s_lsb to it. it keeps the
> inverter. why so?
> TIA
> Kuldeep
> 
> ps : i earlier posted the same message  with subject "synthesis
> problem" it got posted into some old thread.

Article: 43902
Subject: Re: Do I have metastability issues?
From: kayrock66@yahoo.com (Jay)
Date: 5 Jun 2002 12:25:58 -0700
Links: << >>  << T >>  << A >>
Yup

"Ken Mac" <aeu96186@yahoo.co.uk> wrote in message news:<adkg3u$rmi$1@dennis.cc.strath.ac.uk>...
> John,
> 
> Thanks for the reply.
> 
> Surely if I use a CLKDLL then the relationship between the two clocks and
> the clock to out can be determined deterministically (!) and we can
> therefore know if it will work or not?
> 
> Cheers,
> 
> Ken
> 
> "John_H" <johnhandwork@mail.com> wrote in message
> news:3CF79624.E49140E6@mail.com...
> > Without losing data or inserting junk in your 100 MHz multiplexed stream,
>  the 25
> > MHz has to be related to the 100 MHz in *some* fashion.  If the
>  relationship
> > between these clocks allows good clk-to-out at 25 MHz relative to the
>  setup and
> > hold at 100 MHz, accounting for the skew and jitter between the two
>  domains,
> > everything works.  If you don't know the relationship, only that they're
>  phase
> > locked, a short FIFO would be the cleanest implementation with a "half
>  full" as
> > the startup state so the FIFO doesn't over or under fill.

Article: 43903
Subject: Re: Interpreting coregen footprint output in terms of slices
From: Ray Andraka <ray@andraka.com>
Date: Wed, 05 Jun 2002 19:38:44 GMT
Links: << >>  << T >>  << A >>
the slice count will lie between 2013/2 and 1471+2013.  Realistically, assuming
most of the logic is one level of logic, the LUTs will tend to pack with the
flip-flops, and the packing will pack somewhere around 60-80% of the flip-flops
with other flip-flops, so a decent ballpark would be  (flip-flops/0.7)/2  or
about 70% of the number of flip-flops, in your case somewhere around 1400
slices.  Keep in mind it is a ballpark number and may vary considerably
depending on the nature of the logic as well as with any placement already in
the source.  Floorplanning can also reduce the slice count.

Ken Mac wrote:

> Ray,
>
> Thanks for your swift reply,
>
> <snip>
>
> > The slice count will lie between half the
> > larger of the register or lut sites as a lower bound and the sum of the
> lut
> > sites and register sites as an upper bound.
>
> <snip>
>
> So, the slice count will lie between 2013/2 and (1471+2013)/2  (or did you
> just mean 1471+2013 as the upper bound?)
>
> This is good enough for an estimate at the moment - thanks very much.
>
> Ken
>
> > Ken Mac wrote:
> >
> > > Hello,
> > >
> > > If I get Xilinx Core generator to generate a core and it reports the
> > > following for its footprint:
> > >
> > > "1,471 LUT sites used, 2,013 register sites used"
> > >
> > > How can I calculate (roughly) how many slices it will use when APR'd?
> > >
> > > Can I say 2013/2 = 1006.5 slices since there are two register sites per
> > > slice?
> > >
> > > Would this be reasonable?
> > >
> > > Also, is there any way to get the tools to give me a real slice cost for
> the
> > > core without having to go through the whole UCF process etc to avoid the
> > > core being optimised away since it would not be connected to anything?
> > >
> > > Thanks for your time,
> > >
> > > Ken
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 43904
Subject: Re: chipscope
From: kayrock66@yahoo.com (Jay)
Date: 5 Jun 2002 15:04:13 -0700
Links: << >>  << T >>  << A >>
Works like a charm, and I'd back up the other guys advice and save
your money on the USB cable and go with the parallel port one for now.
 I've used both, and strange as it sounds, the cheap cable seems to
work better.

The resources you'll use are a global clock net, and as much block ram
as bits of logic analyzer waveform you want to store.  One criticism
from an engineer here was that the traces weren't long enough (16k
samples max), or long as a multi megabyte dedicated LA, but I don't
debug like that, my finger gets tired of pressing the scroll button on
the LA display.  I prefer to zero in with clever triggers.  Also,
since the Chipscope LA essentially runs in state mode, you don't need
as much memory because every sample is golden- no oversampling
required.

Regards

"cfk" <cfk_alter_ego@pacbell.net> wrote in message news:<gYUK8.18719$RY4.602910011@newssvr21.news.prodigy.com>...
> I am looking for an opinion from a user who has used Chipscope. Is it easy
> to setup and get going? Is it quirky or straight forward. Should I invest my
> time in understanding its care and feeding or not?
> 
> Charles

Article: 43905
Subject: How to find a big, EEPROM based CPLD in a PGA package?
From: borisandcristi@my-beautiful-cristi.com (Boris and Cristi Sheikman)
Date: 5 Jun 2002 15:08:32 -0700
Links: << >>  << T >>  << A >>
Hi,

I'm not sure if I'm posting this to the right newsgroup. Please
forgive the intrusion if I am.

I am looking for >256 macrocell EEPROM based CPLD similar to the
Altera MAX 7000 series. Specifically it needs to have 5V I/O and it
needs to be in a PGA package. I've looked at Actel, Atmel, Lattice,
and Cypress. None of them seem to support this packaging. I'm not
looking for any backwards compatability but if it is somehow, in
someway, backwards compatable with some Altera devices... that can't
hurt.

I used to play around with the MAX9000 (EPM9560GC280-20) but now those
are obsolete.

Thanks! :-)

-- Boris

Article: 43906
Subject: Re: burning a design
From: jetmarc@hotmail.com (jetmarc)
Date: 5 Jun 2002 17:33:42 -0700
Links: << >>  << T >>  << A >>
> Hmm, theoretical yes. But Iam doubtfull if this will work out really good. A
> FPGA can not DIRECTLY change its own design, but another FPGA/uC can
> reprogramm it.

One can design a programmable state machine, and then load new programs
at run-time (from internal or external sources).  This avoids changing the
design (bitstream) itself, but allows for programmable behaviour.

A more sophisticated variant of this approach is the implementation of an
MCU (or CPU) in the FPGA, with the program being native code for that MCU.

Marc

Article: 43907
Subject: IOSTANDARD
From: "cfk" <cfk_alter_ego@pacbell.net>
Date: Thu, 06 Jun 2002 02:20:53 GMT
Links: << >>  << T >>  << A >>
Today, I am getting a PCI master device running in a VirtexE and I can see
some ringing and overshoot on my 33Mhz PCI clock signal that I generate. So,
I innocently added NET "PCICLK" IOSTANDARD="PCI33_3" to my UCF file. To my
surprise, there was no difference in the ringing and overshoot. I tried
making it a syntax error to convince myself that this file really was being
read by the ISE software and yes it is. So, I guess one of two things is
happening. 1) The statement NET <netname> IOSTANDARD="PCI33_3" is not being
set by the tool chain or my test setup was unable to see any difference. I
believe the default is LVTTL. Would I be correct in assuming that this is
the correct way to attempt to change the output voltage drive of a VirtexE
chip?
Charles



Article: 43908
Subject: Bad Behavior of JTAG Download on Altera CPLD with Other Devices
From: wangxy@fudan.edu (Wang Xiao-yun)
Date: 5 Jun 2002 20:10:09 -0700
Links: << >>  << T >>  << A >>
Dear gurus:
  I don't know wether there are any success stories on downloading
Altera CPLD through a boundary scan chain together with devices from
other vendors(PMC-Sierra ie.).
  Here is our problem:
  We have a design with several Altera CPLDs and we download the chips
via boundry scan chain. We found when CPLDs are the only devices in
the chain, download procedure can always accomplished successfully.
However The trick is there are several devices from other vendors in
the chain as well. We try to use BSDL files to identify the alien
devices. Of course the files are obtained from the vendors. The data
of all the devices in the chain are combined in one JAM file. Most of
the time, we observed an error message of "Unrecognized devices" and
the procedure can not continue, while some other times(very rare), we
may be lucky to finished the program.
  Our download procedure strictly follows the instrustion provided
from Altera's FAE. We have checked the waveform of the signals and did
not find obvious errors.
  I want to know wether others have been successful at the same
configuration. Your inputs are appreciated.
  Thanks in advance.

PS: The settings of download are:
  MAX-plus II from Altera for program
  CPLD EPM7064B from Altera

Article: 43909
Subject: xc3042
From: William Lenihan <lenihan3we@earthlink.net>
Date: Thu, 06 Jun 2002 06:29:12 GMT
Links: << >>  << T >>  << A >>

We have an old board design using xc3042 FPGAs (that's xc3042, not
xc3042A or xc3042L) and a new design for it using Verilog. The current
version of Synplicity Synplify will synthesize it into an xc3000 EDIF
netlist, but the recent versions of Alliance & Foundation do not seem to
support xc3000.

How far back into Xilinx tool history do we have to go to find a P&R
tool that will handle a xc3042? And what versions of Windows,
Solaris/SunOS does it require? Do we have to go all the way back to
XACT?

--
==============================
William Lenihan
lenihan3we@earthlink.net
==============================



Article: 43910
Subject: Re: Spartan II Proto. Board
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Thu, 6 Jun 2002 03:36:43 -0400
Links: << >>  << T >>  << A >>
Hi Greg,

You can program the Insight SpartanII with X-Checker or MultiLinx.

My board is for sale for 50% off. Are you interested ?

Sincerely
Daniel DeConinck
www.PixelSmart.com
TEL: 416-248-4473




Article: 43911
Subject: Xilinx JTAG verification failed
From: "Damir Danijel Zagar" <dzagar@srce.hr>
Date: Thu, 6 Jun 2002 09:41:34 +0200
Links: << >>  << T >>  << A >>
Hi,

I've successfuly implemented design on Spartan II 200 but during
JTAG programming (Parallel Cable IV) verification fails on 257
location. Also, when manualy identifying the JTAG chain, Spartan
is reported as Virtex. Otherwise FPGA works fine and user ID
code is readable without any problem. What could cause the
verification problems? Regards,

Damir




Article: 43912
Subject: Re: FPGA destruction possible?
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 06 Jun 2002 07:58:37 -0000
Links: << >>  << T >>  << A >>
>It was latch up. Some 3.3 volt outputs were shorted to +5 and sent the
>whole chip into melt down mode.

I used to think that latch up was instant death for a chip.  But
recently I've been working with a chip/board/setup that latches up
frequently enough that I'm getting an interesting education.  The
chip takes about 30 amps at 2.8 V.  Usually the overcurrent trips,
and everything is fine after a short timeout.  Sometimes we have
that jumpered off.  The chip has a big heat sink, but not that big.
It gets pretty hot if you leave it on for more than a few seconds.
But it doesn't melt or smoke and runs again after it cools off.  

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 43913
Subject: Re: xc3042
From: "Kevin Neilson" <kevin-neilson@removethistextattbi.com>
Date: Thu, 06 Jun 2002 08:17:46 GMT
Links: << >>  << T >>  << A >>
You have to draw X's on a template of the fusemap and convert to JEDEC by
hand and then load it in with an Altair.

"William Lenihan" <lenihan3we@earthlink.net> wrote in message
news:3CFF0149.BCB187FC@earthlink.net...
>
> We have an old board design using xc3042 FPGAs (that's xc3042, not
> xc3042A or xc3042L) and a new design for it using Verilog. The current
> version of Synplicity Synplify will synthesize it into an xc3000 EDIF
> netlist, but the recent versions of Alliance & Foundation do not seem to
> support xc3000.
>
> How far back into Xilinx tool history do we have to go to find a P&R
> tool that will handle a xc3042? And what versions of Windows,
> Solaris/SunOS does it require? Do we have to go all the way back to
> XACT?
>
> --
> ==============================
> William Lenihan
> lenihan3we@earthlink.net
> ==============================
>
>



Article: 43914
Subject: How design a 10 bits counter by using an XILINX FPGA
From: seilebost@aol.com (olivier JEAN)
Date: 6 Jun 2002 01:43:04 -0700
Links: << >>  << T >>  << A >>
Hi everybody.

 I want to design a 10 bits counter by using a XILINX SPARTAN and a vhdl code.
I want a small and fast counter. 
How make it ? By using a LSFR counter or an ordinary counter ?
If I do design my counter by a LSFR's method, I don't know how make it.
Is there a web site whose explain how make it ?

    I need help. 
       
      Thanks.

           Best Regards.

                   Seilebost.

 PS : Sorry. My english is poor

Article: 43915
Subject: Re: Do I have metastability issues?
From: "Ken Mac" <aeu96186@yahoo.co.uk>
Date: Thu, 6 Jun 2002 10:07:01 +0100
Links: << >>  << T >>  << A >>

Thanks again John,

I think I am understanding how to do this - just to confirm:

I feed a CLKDLL with a 100MHz clock and use it to get a divided by 4
output - i.e. 25MHz.

I can then clock my 25MHz sections with this div4 clock and use the other
output of the CLKDLL (i.e. the 100MHz clock) to clock my 100MHz sections.
Was the last part of the 1st paragraph saying that I should use the 90,180
or 270 phase output of the CLKDLL for the 100MHz clock?  Also, which clock
signal should I feedback to the CLKDLL - the 0 phase 100MHz output or the
phase that I am using in my design?

Sorry for all the detail but I have lost a lot of hours in the past trying
to work with multiple clock domains!

Thanks for your time,

Ken

"John_H" <johnhandwork@mail.com> wrote in message
news:3CFE3720.F639DBA9@mail.com...
> If you use the CLKDLL to generate one clock (or both) you will absolutely
be
> able to make the transition between domains.  The metastability question
does
> comes into play.  Ray Andraka has pointed out how the clock net loading
and the
> jitter in the DLLs can make the destination edge happen after the source
signal
> has already transitioned the the next cycle, catching the wrong phase of
the
> signal.  It may be better to choose a "safe" alignment of the signals so
you
> have a known delay (choose a different phase of the 100MHz clock) that
isn't
> destroyed by jitter and skew.
>
> If your 25MHz data path runs off the 100MHz clock with clock enables every
four
> cycles, your implementation with be clean - no problems with two clock
domains
> since the edged aren't related - they're the same!
>
>
> Ken Mac wrote:
>
> > John,
> >
> > Thanks for the reply.
> >
> > Surely if I use a CLKDLL then the relationship between the two clocks
and
> > the clock to out can be determined deterministically (!) and we can
> > therefore know if it will work or not?
> >
> > Cheers,
> >
> > Ken
> >
> > "John_H" <johnhandwork@mail.com> wrote in message
> > news:3CF79624.E49140E6@mail.com...
> > > Without losing data or inserting junk in your 100 MHz multiplexed
stream,
> > the 25
> > > MHz has to be related to the 100 MHz in *some* fashion.  If the
> > relationship
> > > between these clocks allows good clk-to-out at 25 MHz relative to the
setup
> > and
> > > hold at 100 MHz, accounting for the skew and jitter between the two
> > domains,
> > > everything works.  If you don't know the relationship, only that
they're
> > phase
> > > locked, a short FIFO would be the cleanest implementation with a "half
> > full" as
> > > the startup state so the FIFO doesn't over or under fill.
>



Article: 43916
Subject: Re: xc3042
From: "F.M. Fontaine" <fontain@nlr.nl>
Date: Thu, 6 Jun 2002 11:11:54 +0200
Links: << >>  << T >>  << A >>
I think that XACTStep 6.0.1 (which actually is XACT 5.2.1) from november
1996 is the last version to support the original XC2000/XC3000/XC4000
families.
XACTStep 6.0.1. is a windows version (originally Win 3.11) which will run
under Win95, I don't know if it will run under NT, 98, ME, 2000 or XP.
XACT 5.2.1 is a DOS version of the same core-tools.

Both version require a dongle ...

Filip


"William Lenihan" <lenihan3we@earthlink.net> wrote in message
news:3CFF0149.BCB187FC@earthlink.net...
>
> We have an old board design using xc3042 FPGAs (that's xc3042, not
> xc3042A or xc3042L) and a new design for it using Verilog. The current
> version of Synplicity Synplify will synthesize it into an xc3000 EDIF
> netlist, but the recent versions of Alliance & Foundation do not seem to
> support xc3000.
>
> How far back into Xilinx tool history do we have to go to find a P&R
> tool that will handle a xc3042? And what versions of Windows,
> Solaris/SunOS does it require? Do we have to go all the way back to
> XACT?
>
> --
> ==============================
> William Lenihan
> lenihan3we@earthlink.net
> ==============================
>
>




Article: 43917
Subject: Re: xc3042
From: Ray Andraka <ray@andraka.com>
Date: Thu, 06 Jun 2002 10:41:05 GMT
Links: << >>  << T >>  << A >>
I think you have to go back to XACT6, which ran under win3.1.  It will also
run under later versions if you avoid the GUIs, especially the floorplanner
and XDE.

William Lenihan wrote:

> We have an old board design using xc3042 FPGAs (that's xc3042, not
> xc3042A or xc3042L) and a new design for it using Verilog. The current
> version of Synplicity Synplify will synthesize it into an xc3000 EDIF
> netlist, but the recent versions of Alliance & Foundation do not seem to
> support xc3000.
>
> How far back into Xilinx tool history do we have to go to find a P&R
> tool that will handle a xc3042? And what versions of Windows,
> Solaris/SunOS does it require? Do we have to go all the way back to
> XACT?
>
> --
> ==============================
> William Lenihan
> lenihan3we@earthlink.net
> ==============================

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 43918
Subject: Re: Do I have metastability issues?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 06 Jun 2002 10:49:43 GMT
Links: << >>  << T >>  << A >>
be really careful about assuming the clocks out of a DLL are phase aligned.  They are locked to a
fixed frequency relationship and nominally to a fixed phase, but can be skewed significantly by the
sum of the effects of unequal loading on the clock nets, DLL skew and input jitter.  The input
jitter has bitten me once in the past giving enough skew between a 1x and 2x DLL output to cause
data direct from a flip-flop in one domain to a flip-flop in the other to get clocked in on the
wrong edge.  To be safe, use some added logic to move the transfer away from the common active
adge.  It doesn't have to be a FIFO, clever use of the clock enables and a circuit to synthesize
the slower clock in the faster clock's domain to use as the clock enable is sufficient.

Jay wrote:

> Yup
>
> "Ken Mac" <aeu96186@yahoo.co.uk> wrote in message news:<adkg3u$rmi$1@dennis.cc.strath.ac.uk>...
> > John,
> >
> > Thanks for the reply.
> >
> > Surely if I use a CLKDLL then the relationship between the two clocks and
> > the clock to out can be determined deterministically (!) and we can
> > therefore know if it will work or not?
> >
> > Cheers,
> >
> > Ken
> >
> > "John_H" <johnhandwork@mail.com> wrote in message
> > news:3CF79624.E49140E6@mail.com...
> > > Without losing data or inserting junk in your 100 MHz multiplexed stream,
> >  the 25
> > > MHz has to be related to the 100 MHz in *some* fashion.  If the
> >  relationship
> > > between these clocks allows good clk-to-out at 25 MHz relative to the
> >  setup and
> > > hold at 100 MHz, accounting for the skew and jitter between the two
> >  domains,
> > > everything works.  If you don't know the relationship, only that they're
> >  phase
> > > locked, a short FIFO would be the cleanest implementation with a "half
> >  full" as
> > > the startup state so the FIFO doesn't over or under fill.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 43919
Subject: Xilinx ise software?
From: javodv@yahoo.es (javid)
Date: 6 Jun 2002 03:52:18 -0700
Links: << >>  << T >>  << A >>
Hello,

I am new to fpgas. I was wondering if anyone could clarify me which is
the difference between ISE 4.2i (design environment PC) and the ISE
foundation 4.2i. I have seen that Xilinx also provide a "Service Pack"
for 4.2i, what is exactly this Service Pack?, Do I need to install it
or it is included in the ISE 4.2i?.

Thanks a lot and Best regards,

Javi

Article: 43920
Subject: Re: burning a design
From: David DOMINGUEZ <David.Dominguez@cern.ch>
Date: Thu, 06 Jun 2002 13:36:05 +0200
Links: << >>  << T >>  << A >>

Roger,
As Falk says, Max7000 is a CPLD not an FPGA. This means among
other things that even if you switch the power off, the configuration data
( bitstream file) you have in the CPLD will remain (so as if it was hardwired
inside): you don't need an external memory chip to reprogram the device
everytime power goes down. Opposed to FPGAs that do need this external
memory (for example a Flash memory chip like XC18Vxx). However the bitstream
is not really hard-wired since you can reprogram your CPLD.

 To reprogram a CPLD you will need an external "intelligent
device": I think the CPLD will not be able to reprogram itself on the fly
as you wish.

   For an FPGA it would be possible to write the new configuration
bitstream into a flash memory connecting  JTAG pins from flash to
user I/O in the FPGA  and get reconfigured with the new bitstream
by asserting program pin  or using the CF_b pin from the flash memory
chip (see XC18Vxx devices) via a JTAG command. You will need some extra
logic outside the FPGA to be able to write into the Flash without sending
the FPGA into "reconfiguration state" (JTAG protocol in XC18Vxx needs the
assertion of  reset pin that may send the FPGA into reconfigurationvia
Init signal).

  This would allow you to replace the old bitstream stored
in the flash with a new bitstream.

   *** BUT***: You have to realize that reprogramming an FPGA/CPLD
NEEDS a bitstream that you *cannot* generate internaly in the device, so
even if you are able to replace an old bitstream with a new one, you need
an external PC/workstation to generate the new bitstream file and hence
your system will not be able to reprogram itself with no external aid (PC)
as you wish.

  If you want to build a neural network with FPGAs/CPLD, I think
the best thing is to build a network based on PC/workstations.

-Each of these PC/Workstation will be responsable for a few FPGAs. One
PC can have 4 or 5 FPGA-based boards on its PCI bus.

               
PC        --------Ethernet/Gigabit/SCI-------------------
PC
<br>          /      
|    \                                                                        
/      |      \
<br>        /        
|      \ PCI BUS                                                    
/        |       
\PCI BUS
<br>      /          
|        \                                                                
/          |        
\
<br>  FPGA  FPGA   FPGA                                                  
FPGA  FPGA     FPGA

 - Every time an FPGA needs new configuration the PC will calculate
the new bitstream and download it via PCI.

Hope this helps
<br>Regards,

 David.
<br> 
<br> 

--------------
<br>"Roger King" &lt;roger@king.com> schrieb im Newsbeitrag
<br><a href="news:BlfL8.215525$t8_.150019@news01.bloor.is.net.cable.rogers.com">news:BlfL8.215525$t8_.150019@news01.bloor.is.net.cable.rogers.com</a>...

When you burn a design on an FPGA(Altera 7000) is it hard-wired? Can
it be
<br>changed internally, without the assistance of a PC? Like can one design
some
<br>circuit that can change itself? Maybe like neural networks... or some
other
<br>AI stuff... Thanks

Falk Brunner wrote:
<blockquote TYPE=CITE>"Roger King" &lt;roger@king.com> schrieb im Newsbeitrag
<br><a href="news:BlfL8.215525$t8_.150019@news01.bloor.is.net.cable.rogers.com">news:BlfL8.215525$t8_.150019@news01.bloor.is.net.cable.rogers.com</a>...
<br>> When you burn a design on an FPGA(Altera 7000) is it hard-wired?
Can it be

THe MAx7000 is a CPLD series. CPLDs are the little brothers of FPGAs.

changed internally, without the assistance of a PC? Like can one design
<br>some
<br>> circuit that can change itself? Maybe like neural networks... or
some
<br>other
<br>> AI stuff... Thanks

Hmm, theoretical yes. But Iam doubtfull if this will work out really
good. A
<br>FPGA can not DIRECTLY change its own design, but another FPGA/uC can
<br>reprogramm it.

--
<br>MfG
<br>Falk</blockquote>
</html>


Article: 43921
Subject: Re: FPGA destruction vs power management
From: "Cemal Coemert (TIP)" <coemert@fokus.gmd.de>
Date: Thu, 06 Jun 2002 13:38:17 +0200
Links: << >>  << T >>  << A >>
Ray Andraka wrote:

>  We also force zeros into the data path when there is no or invalid data at the input.  In bit serial (and distributed arithmetic) designs, even constant values can cause considerable power dissipation since they result in bit transitions.

If I understand you right a flip-flop dissipates less power when it drives '0' than driving '1'. Why ?
Is it maybe because of the leakage current when driving '1' ?

Regards, Cemal


Article: 43922
Subject: New verilog
From: Russell <rjshaw@iprimus.com.au>
Date: Thu, 06 Jun 2002 12:21:28 GMT
Links: << >>  << T >>  << A >>
http://www.eetimes.com/story/OEG20020604S0034

Article: 43923
Subject: PowerPC Architecture
From: Laurent Gauch <laurent.gauch@amontec.com>
Date: Thu, 06 Jun 2002 14:59:52 +0200
Links: << >>  << T >>  << A >>
Hi all,

Do you know a good book on the PowerPC architecture (with OPB LPB 
arbitrer description)!

(for introducing my students)

Laurent


Article: 43924
Subject: Re: PowerPC Architecture
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Thu, 06 Jun 2002 13:51:28 GMT
Links: << >>  << T >>  << A >>
On Thu, 06 Jun 2002 14:59:52 +0200, Laurent Gauch
<laurent.gauch@amontec.com> wrote:

>Hi all,
>
>Do you know a good book on the PowerPC architecture (with OPB LPB 
>arbitrer description)!
>
>(for introducing my students)

Did you try 
news:comp.sys.powerpc.tech or 
news:comp.sys.powerpc.misc ?

Allan.



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