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Messages from 45075

Article: 45075
Subject: Using an FPGA as an embedded system timing master
From: "Tom D" <uceeted@NOSPAMucl.ac.uk>
Date: Thu, 11 Jul 2002 14:38:25 +0100
Links: << >>  << T >>  << A >>
I am designing an embedded sensor system which consists of a C6k DSP chip
combined with a memory mapped Spartan IIE FPGA.  The DSP chip performs most
of the local data processing, and the FPGA controls peripherals, acts as
FIFOs for data from ADCs and buffers data to/from a simple network device.

Given that the on-board timers on the interrupt-based DSP can only
realistically achieve millisecond resolution, they are inappropriate as I
require sub-microsecond coherent timing control (e.g. a small integer number
of clock cycles).  Hence I would like to implement timer(s) on the FPGA
instead.
I may need to strobe an output pin or synchronously program a peripheral
over a bus connected to the FPGA with great accuracy (perhaps every 2 clock
cycles on the FPGA where it is clocked at 100MHz or 200MHz), with low jitter
such that the events are closely in phase to the clock.

I assume this should be possible using a Spartan IIE and have started to
write some VHDL for the functionality, but would appreciate comments about
the likely synchronisation I will be able to achieve, and any hints and tips
for maximising the performance of the design.

Many thanks

Tom




Article: 45076
Subject: Re: Using DLL's for 90 Degree Phase Shift
From: John_H <johnhandwork@mail.com>
Date: Thu, 11 Jul 2002 15:15:17 GMT
Links: << >>  << T >>  << A >>
The feedback should be from the clk0 (no gbuf will skew things but only a
little) with the lone GBUF you can spare coming from the clk90 output.  The
DLL tries to make the phases of the feedback and the reference frequency the
same.


n1089240 wrote:

> I am using clk0 out from a clkdll with feedback through a bufg.
> The system also uses the divide by 4 output (d4 clk) from the same dll.
> I would like (and have tried) to use the clk90 out to keep the 4x and 1x
> (divide by 4) clock edges away from each other. If I route the feedback
> from the clk90 - thru the bufg - into the feedback, the d4 clk still has
> same phase relationship with clk90 as it did before when using clk0.
> I saw a previous post that indicated it would be nice to use the clk90
> instead of the clk0 for that purpose, but I can't think of a way to do
> it. Did I mention, that I'm also out of bufg's at this point, although I
> still have 2 dll's lying around doing nothing. Part is v300e


Article: 45077
Subject: Deterministic Output?
From: "D Brown" <dbrown123@shaw.ca>
Date: Thu, 11 Jul 2002 09:20:45 -0600
Links: << >>  << T >>  << A >>
If I have the same vhdl source files, ucf files, and the same settings for
Synthesis and Implemnt Design, and Generate Programming File in Xilinx
Foundation ISE 4.2, using FPGA Express as the compiler, will I always get
the same .bit file as an output? So if I archive all the settings and source
in a project and some time later down the road go back and rebuild it, will
I get the EXACT same bit file?
Thanks,
Dave




Article: 45078
Subject: Re: Deterministic Output?
From: Alan Nishioka <alann@accom.com>
Date: Thu, 11 Jul 2002 09:32:01 -0700
Links: << >>  << T >>  << A >>
The .bit file contains the date and time from the ncd file in its 
header, so at the very least, this will change.

The actual bitstream should be the same, but I don't use the same 
toolchain so I don't know for sure.

Alan Nishioka
alann at accom dot com

D Brown wrote:

>If I have the same vhdl source files, ucf files, and the same settings for
>Synthesis and Implemnt Design, and Generate Programming File in Xilinx
>Foundation ISE 4.2, using FPGA Express as the compiler, will I always get
>the same .bit file as an output? So if I archive all the settings and source
>in a project and some time later down the road go back and rebuild it, will
>I get the EXACT same bit file?
>Thanks,
>Dave
>
>
>


Article: 45079
Subject: Re: Need a non-pipelined signed integer divider
From: Ray Andraka <ray@andraka.com>
Date: Thu, 11 Jul 2002 16:49:16 GMT
Links: << >>  << T >>  << A >>
It will have a fairly long delay: unlike multipliers, each of the partial
results depends on the previous partial so the partials have to be computed in a
chain rather than a tree.  I don't know of any commercial IP for this.  You
might look at Koren's book (link on the bookstore page in my website).  He
discusses fast division in reasonably good detail.  You'll have to take that
discussion and roll it into hardware.  At least in his book, the hardware is
reasonably laid out.

Jianyong Niu wrote:

> Hi, Guys
> I am looking for a non-pipelined signed integer divider with the reminder in
> fractional format. Anybody can offer any reference?
>
> Thanks a lot in advance!!!
>
> --
> Jianyong Niu
> -----------------------------
> Univ of Sheffield
> Email: cop00jn@shef.ac.uk

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 45080
Subject: Re: ModelSim License problem
From: newman5382@aol.com (newman)
Date: 11 Jul 2002 09:59:50 -0700
Links: << >>  << T >>  << A >>
Rob,
  Typically, the license file is pointed to by the LM_LICENSE_FILE
environmental variable.  If you look at the license file in question,
there will be something like DISK_SERIAL_NUM=CXXXXXXXX, where the
first letter specifies the drive letter if it is node-locked to a
drive.  The other 8 hex numbers would should match the VOL
<drive_letter>: command prompt command.

  Since it appears that the drive letter is part of the serial number,
I would expect changing the drive letter from C to D would break the
validation function.  You might want to check to see that the correct
new license file is in the LM_LICENSE_FILE path, and remove references
to the obsolete license files.

Newman
  
"Rob Finch" <robfinch@sympatico.ca> wrote in message news:<aM3X8.3492$5i5.1304622@news20.bellglobal.com>...
> I think the license file could also be tied to the hard drive serial number.
> When I upgraded the hard drive in my machine *poof* modelsim no longer
> worked saying I didn't have a valid license file. I tried unistalling and
> reinstalling and obtaining a new license file from Xilinx none of which
> worked. Eventually I had to put the old drive back in my machine (under a
> different drive letter) and change the license search path to include the
> old drive. I can at least run ModelSim now, but it complains when I run it
> that I only have a 30 day evaluation license. Somehow the license software
> knows that things have changed. I've tried looking in the registry for
> related entries but could figure out where they were.
> 
> I sure would like to know what the procedure is to keep ModelSim working
> when you upgrade your hard drive or network adapter.
> 
> Rob
> 
> 
> "Holger Kleinegraeber" <olgi42@web.de> wrote in message
> news:agc97u$kouhe$1@ID-69700.news.dfncis.de...
> >
> > "Derrick Cheng" schrieb:
> >
> > > invalid, such that I could not perform the simulation.
> > > I got the license file from the Xilinx, and I installed the license
> > > successfully with the License program.
> >
> > The License is bound to the MAC-Address of your Network card. Did you
> > registered, downloaded and work with the same computer?
> >
> > Greetings,
> >   Holger
> >
> >

Article: 45081
Subject: Virtex II - What to do with unused banks?
From: "Bill" <not@home.com>
Date: 11 Jul 2002 22:17:21 +0100
Links: << >>  << T >>  << A >>
Hi,

I'm forced for the moment to use a much-larger device than necessary due to
supply problems.   Since I'm not using anywhere near the maximum number of
i/o's, is it allowed to connect the VCCO pins of the unused banks to ground?
I can't find a reference in the docs regarding this subject.   Obviously the
VCCINT's are always connected, no matter what size device.

Bill



______________________________________________________________________
Posted Via Uncensored-News.Com - Still Only $9.95 - http://www.uncensored-news.com
      <><><><><><><>   The Worlds Uncensored News Source   <><><><><><><><>
  

Article: 45082
Subject: Re: Virtex II - What to do with unused banks?
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 11 Jul 2002 15:46:05 -0700
Links: << >>  << T >>  << A >>
Always connect the Vccio's to an appropriate positive voltage. You would not save any
measurable current by disconnecting them or tying them to ground.

Peter Alfke, Xilinx Applications

Bill wrote:

> Hi,
>
> I'm forced for the moment to use a much-larger device than necessary due to
> supply problems.   Since I'm not using anywhere near the maximum number of
> i/o's, is it allowed to connect the VCCO pins of the unused banks to ground?
> I can't find a reference in the docs regarding this subject.   Obviously the
> VCCINT's are always connected, no matter what size device.
>
> Bill
>
> ______________________________________________________________________
> Posted Via Uncensored-News.Com - Still Only $9.95 - http://www.uncensored-news.com
>       <><><><><><><>   The Worlds Uncensored News Source   <><><><><><><><>
>


Article: 45083
Subject: Xilinx RPMs before Virtex-II
From: John_H <johnhandwork@mail.com>
Date: Fri, 12 Jul 2002 00:53:49 GMT
Links: << >>  << T >>  << A >>
I'm trying to get some inputs and outputs to be adjacent to their
associated IOBs.

I can do hard placement for each individual element with a bunch of back
& forth to figure out which pins are at whiach row/column, or I can try
to RLOC.

I just now looked at the FPGA_EDITOR and found the "RPM grid" location
mentioned for each element - slice and IOB - are in X0Y0 format.  This
format might be valid for Virtex-II, but the RLOC doesn't allow it for
older parts.

Can I use an RLOC in some form?  Can I use the RPM grid?

I tried doing a LOC to the outside row or column but I ended up with the
elements shuffled back and forth across the range, not closest to the
IOB in most cases.  Do I *have* to LOC each of my 100+ inputs
independently?

...thanks.


Article: 45084
Subject: FPGA CPU?
From: "res19j1c" <res19j1c@verizon.net>
Date: Fri, 12 Jul 2002 01:58:22 GMT
Links: << >>  << T >>  << A >>
Hi,
I'm new to FPGAs. I just have a few questions. I'm sure some of these have
been asked already but I've been using the google archive to search old
posts and couldn't find anything.

1.) Is it correct that I could design a CPU on a FPGA?

2.) It seems that the ability to create a certain design is measured in
gates. So the more complex the design, the more gates it needs. Is this
true, or at least partly true?

3.) If so, how many gates would it take to implement a CPU with
functionality about equivalent to an Intel IA-32 style chip (80386 - 80686).

4.) About how many MHz would this run at on a newer FPGA such as the
Virtex-II?



Article: 45085
Subject: Re: FPGA CPU?
From: John Williams <j2.williams@qut.edu.au>
Date: Fri, 12 Jul 2002 15:31:34 +1000
Links: << >>  << T >>  << A >>


res19j1c wrote:
 
> 1.) Is it correct that I could design a CPU on a FPGA?

Yes.

> 2.) It seems that the ability to create a certain design is measured in
> gates. So the more complex the design, the more gates it needs. Is this
> true, or at least partly true?

Yes.  However CLBs (config. logic blocks) or LUTs are a more
representative figure for FPGAs than raw gate counts.

> 3.) If so, how many gates would it take to implement a CPU with
> functionality about equivalent to an Intel IA-32 style chip (80386 - 80686).

Heaps (technical terminology!).  For example, the LEON processor model,
which is functionally equivalent to one of the older SPARC chips takes a
fair slab of a modest sized Virtex (4800 LUTs out of approx 6000 LUTs in
an XCV300).

I'm guessing but I think an 80x86-style CPU would require a fair bit
more than that.

> 4.) About how many MHz would this run at on a newer FPGA such as the
> Virtex-II?

On a 2.5V Virtex speed grade 8 (the fastest) the Leon team report about
45Mhz (http://www.estec.esa.nl/wsmwww/leon/#Synthesis)

This would probably be quicker on a newer part.  

Regards,

John

Article: 45086
Subject: Re: FPGA CPU?
From: "Rob Finch" <robfinch@sympatico.ca>
Date: Fri, 12 Jul 2002 01:37:45 -0400
Links: << >>  << T >>  << A >>
> 1.) Is it correct that I could design a CPU on a FPGA?

Yes, it is possible to design a cpu and implement it on an FPGA. Some types
of cpu architectures are more suited to fpga's than others. It depends on
what your motivation is. If you are designing a cpu as an academic exercise
or as a proof of concept then you don't have to worry about the effect of
implementing it in an FPGA so much. If on the other hand, you want it to run
fast in an FPGA, then you have to be really aware of the FPGA's architecture
and design with it in mind.

> 2.) It seems that the ability to create a certain design is measured in
> gates. So the more complex the design, the more gates it needs. Is this
> true, or at least partly true?

Generally true. You can often reduce the complexity of a design while
retaining the same or almost the same functionality by thinking more about
it in the design stage. Also other factors can affect the gate count. For a
cpu that executes the same instruction set, the number of gates required can
vary widely, depending for instance on whether the focus is on low gate
count or high performance.

>
> 3.) If so, how many gates would it take to implement a CPU with
> functionality about equivalent to an Intel IA-32 style chip (80386 -
80686).

It depends what you mean by equivalent functionality. The 80383+.. is an
incredibly complex chip. Implementing all the features of this type of chip
would require an enormous number of gates (eg hundreds of thousands). Try
looking at the transistor count for the chip then dividing by the gate to
transistor ratio.

>
> 4.) About how many MHz would this run at on a newer FPGA such as the
> Virtex-II?
>

A simple RISC cpu can be made to run at about 60Mhz in a SpartanII. I
suspect in the much faster Virtex fpga a RISC cpu could be made to run much
faster eg. 120MHz+. However this is for a RISC cpu. A complex cpu like the
80386 would run much slower. As a wild guess I would say about 30-40MHz but
it depends a lot on the design.


I don't know what your background is. If you have not designed a cpu before,
I would suggest trying something simpler than the x86 architecture first.
Have a look at http://www.fpgacpu.org/ Also, I don't want to discourage you,
but unless you plan to assemble a team to work on it full time, it's not
really practical to design a clone of the IA-32 style cpu, or for that
matter most commercially available cpus. They are just plain too complex.
There is also the 90/10 or 95/5 rule. You can get the cpu 90% working in 10%
of the time it takes to get it 100% working.


Rob
http://www.birdcomputer.ca






Article: 45087
Subject: Re: Deterministic Output?
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Fri, 12 Jul 2002 06:03:08 GMT
Links: << >>  << T >>  << A >>
On Thu, 11 Jul 2002 09:32:01 -0700, Alan Nishioka <alann@accom.com>
wrote:

>The .bit file contains the date and time from the ncd file in its 
>header, so at the very least, this will change.
>
>The actual bitstream should be the same, but I don't use the same 
>toolchain so I don't know for sure.

We have had problems with the 3.1i tools.  Sometimes the downloads
would differ between different computers, even though the inputs
(edif, ucf) were identical, and the software version was identical.
Reinstalling the software on all machines concerned didn't improve
matters.
The differences we were seeing were quite significant:  some downloads
would work, and others were completely nonfunctional.

Xilinx said that they would look into this, but I'm not sure if it has
been fixed in the 4.2 tools.

OTOH, I've always had identical results from a given PC.

Regards,
Allan.

>Alan Nishioka
>alann at accom dot com
>
>D Brown wrote:
>
>>If I have the same vhdl source files, ucf files, and the same settings for
>>Synthesis and Implemnt Design, and Generate Programming File in Xilinx
>>Foundation ISE 4.2, using FPGA Express as the compiler, will I always get
>>the same .bit file as an output? So if I archive all the settings and source
>>in a project and some time later down the road go back and rebuild it, will
>>I get the EXACT same bit file?
>>Thanks,
>>Dave
>>
>>
>>
>


Article: 45088
Subject: Re: Deterministic Output?
From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver)
Date: Fri, 12 Jul 2002 06:04:29 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <agk7os$8jh$1@pallas.novatel.ca>, D Brown <dbrown123@shaw.ca> wrote:
>If I have the same vhdl source files, ucf files, and the same settings for
>Synthesis and Implemnt Design, and Generate Programming File in Xilinx
>Foundation ISE 4.2, using FPGA Express as the compiler, will I always get
>the same .bit file as an output? So if I archive all the settings and source
>in a project and some time later down the road go back and rebuild it, will
>I get the EXACT same bit file?

The place and route (and probably other pieces as well) are
probabilistic, deliberately so.  So you need to force a consistant
seed as well for the PRNG


-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 45089
Subject: How to develop a MCU?
From: "Reala" <manfield.chow@scoreconcept.com>
Date: Fri, 12 Jul 2002 15:07:03 +0800
Links: << >>  << T >>  << A >>
Dear all,

I am very interested in IC design. I just learnt from school but not real
experience.
I would like to know the procedure of developing a simple MCU?
How can i start this? I would like to develop the chip by verilog and
implement by FPGA. Any suggestion for me? which free tools in good for me?
Thank a lot.

Reala



Article: 45090
Subject: Re: Deterministic Output?
From: Petter Gustad <newsmailcomp3@gustad.com>
Date: Fri, 12 Jul 2002 08:07:39 GMT
Links: << >>  << T >>  << A >>
allan_herriman.hates.spam@agilent.com (Allan Herriman) writes:

> On Thu, 11 Jul 2002 09:32:01 -0700, Alan Nishioka <alann@accom.com>
> wrote:
> 
> >The .bit file contains the date and time from the ncd file in its 
> >header, so at the very least, this will change.
> >
> >The actual bitstream should be the same, but I don't use the same 
> >toolchain so I don't know for sure.
> 
> We have had problems with the 3.1i tools.  Sometimes the downloads
> would differ between different computers, even though the inputs
> (edif, ucf) were identical, and the software version was identical.
> Reinstalling the software on all machines concerned didn't improve
> matters.
> The differences we were seeing were quite significant:  some downloads
> would work, and others were completely nonfunctional.
> 
> Xilinx said that they would look into this, but I'm not sure if it has
> been fixed in the 4.2 tools.
> 
> OTOH, I've always had identical results from a given PC.

Are you sure there isn't some setting stored in the Windows registry
which is causing this?

I have never seen this, but I'm using mostly SPARC Solaris. I check
out the sources and script files from CVS (version control) and run
the entire toolchain from a script. I hate the fact that a FPGA would
fail in the lab because somebody has a different option checked off
far down in the menu hierarchy.

Synopsys FPGA Compiler II (I guess FPGA Express will too) will create
a project directory and use a form of incremental synthesis. I will
remove this directory when I do a full build. 

The script will do a full build, but optionally I can do a incremental
synthesis as well as a guided place and route. In the latter case the
results might of course differ from a clean build.

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 45091
Subject: Replacing a XC4006E
From: "Thomas Heller" <theller@python.net>
Date: Fri, 12 Jul 2002 10:51:05 +0200
Links: << >>  << T >>  << A >>
Are there any pin-compatible parts to that I can
replace a Xilinx XC4006E PQ160 - 2C without changing
the board layout? Probably a Spartan device?

How large are the chances that the pinout can be kept?

Regards,

Thomas Heller
ION-TOF GmbH



Article: 45092
Subject: HDL generate from handel-C can be accepted by synthesis tools?
From: ruibinw@hotmail.com (mike)
Date: 12 Jul 2002 02:09:09 -0700
Links: << >>  << T >>  << A >>
Hi,

who have experience about celoxica DK1? Is it possible to generate
VHDL/Verilog from handel c code and use Synplify or Synopsys to
generate Gate-Level netlist?

From the document, it said DK1 could generate EDIF netlist and use
FPGA tools( such as Quartus) to place and route. But I would like to
know the verilog generate from c code can be acceptable by othe
Synthesis tools. Thanks a lot.

mike

Article: 45093
Subject: Re: FPGA CPU?
From: "res19j1c" <res19j1c@verizon.net>
Date: Fri, 12 Jul 2002 09:53:03 GMT
Links: << >>  << T >>  << A >>
> I don't know what your background is. If you have not designed a cpu
before,
> I would suggest trying something simpler than the x86 architecture first.
> Have a look at http://www.fpgacpu.org/ Also, I don't want to discourage
you,
> but unless you plan to assemble a team to work on it full time, it's not
> really practical to design a clone of the IA-32 style cpu, or for that
> matter most commercially available cpus. They are just plain too complex.
> There is also the 90/10 or 95/5 rule. You can get the cpu 90% working in
10%
> of the time it takes to get it 100% working.

Thank you for the link. I have a pretty good hardware background. I have
never designed a CPU before, but I figured that an FPGA would probably be
the place to start seeing as I don't have billions of dollars :). I'm not
really trying to clone the IA-32, I was just curious. I am thinking of
starting pretty small and eventually implementing a simple RISC CPU.
Thanks for the tips.



Article: 45094
Subject: some questions from a fpga newer
From: zy_don@inhe.net (yi don)
Date: 12 Jul 2002 03:46:05 -0700
Links: << >>  << T >>  << A >>
i am interesting in fpga designing,but few experience of designing
fpga,and i am eager to design fpga,so anyone can help me how improve
my experience and where?

regards.

Article: 45095
Subject: Re: Deterministic Output?
From: Ray Andraka <ray@andraka.com>
Date: Fri, 12 Jul 2002 13:19:38 GMT
Links: << >>  << T >>  << A >>
That was true for the XACT tools.  I'm not sure it is true for the current PAR
though.  I've never checked, but for a give placer table we do get the same timing
numbers on a design run several times on the same machine.  Change anything, even
just adding an area group in the floorplan, and the timing will change.

Nicholas Weaver wrote:

> In article <agk7os$8jh$1@pallas.novatel.ca>, D Brown <dbrown123@shaw.ca> wrote:
> >If I have the same vhdl source files, ucf files, and the same settings for
> >Synthesis and Implemnt Design, and Generate Programming File in Xilinx
> >Foundation ISE 4.2, using FPGA Express as the compiler, will I always get
> >the same .bit file as an output? So if I archive all the settings and source
> >in a project and some time later down the road go back and rebuild it, will
> >I get the EXACT same bit file?
>
> The place and route (and probably other pieces as well) are
> probabilistic, deliberately so.  So you need to force a consistant
> seed as well for the PRNG
>
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 45096
Subject: Re: Getting started with FPGAs
From: "Paul" <kimbledesign@eircom.net>
Date: Fri, 12 Jul 2002 15:01:02 +0100
Links: << >>  << T >>  << A >>

> > Altera -not Xilinx- but really easy to use:
> >
> > http://www.hvwtech.com/intro-fpga.htm
>
> Hmm... Very interesting. Shame they don't seem to have any UK
distributors.


EBV are a distributor for Altera....




Article: 45097
Subject: Security features
From: "Paul" <kimbledesign@eircom.net>
Date: Fri, 12 Jul 2002 15:06:05 +0100
Links: << >>  << T >>  << A >>
Hi All,
Are there any security features in FPGA's that I can use to protect
software?

regards
Paul



Article: 45098
Subject: 6 parallel inputs to Mux? How?
From: "Hristo Stevic" <hristostev@yahoo.com>
Date: Fri, 12 Jul 2002 14:12:25 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hello,
i have 6 inputs of 12-bit wordlength to multiplex.
i can use muxes using LUts. 
Is there any better way (TBUF?) to do it?
target Xc4k or Virtex

Regards


-- 
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 45099
Subject: Question: Xilinx schematic entry, constants, bit swapping
From: Bob W <fa@_NO_SPAM_AskTheOracle.com>
Date: Fri, 12 Jul 2002 10:14:07 -0400
Links: << >>  << T >>  << A >>

II need to enter a 20 bit constant as a value to load into counter
designed using the Schematic entry tool. How do I do that? I could
probably use Vcc and Gnd macros but I am hoping there is a cleaner
solution.

In StateCad there is a constant function, in Altera there is an
LP_CONST macro. How do I do this in Xilinx?

Also, I would like to create a block that swaps the order if the bits
in a byte from 7..0 to 0...7. In Altera MaxPlus I could create a block
with the input from Datain7 connected to Data 0 through a Soft Cell
that allows me to connect 2 wires without creating any logic. How do I
do this in Xilinx?

Bob



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