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Yup, it is what you thought (a gate level sim). As for your "Quartus" way, I assume the sdo file comes into play automatically. You should be able to tell by looking at the transitions in the waveform - If they do not all change on clock edges (and you see lots of glitches between clocks), then the sdo file has been used during the Quartus sim. Cheers, Xanatos "Prashant" <prashantj@usa.net> wrote in message news:ea62e09.0208050712.17e721d5@posting.google.com... > Hi, > I have been simulating the gate level netlists the modelsim way, just > as you suggest. But I wanted to confirm if the Quartus approach was > what I thought. > > Also, I understand that with modelsim you should use the .sdo file. > But is this file taken into consideration when working the Quartus way > ? > > Thanks, > Prashant > > > "Xanatos" <fpsbb98@yahoo.com> wrote in message news:<S6k39.278432$WJf1.96674@news01.bloor.is.net.cable.rogers.com>... > > Yes. > > > > You can (in the EDA Tools section) set up a simulator specific output > > simulation file, which is a gate level netlist as well. I've used that quite > > a bit (with Modelsim -> creates a vo file and sdo timing file), and seems to > > work fine. > > > > Cheers, > > Xanatos > > > > "Prashant" <prashantj@usa.net> wrote in message > > news:ea62e09.0208041608.7e947420@posting.google.com... > > > Hi, > > > If I followed the Quartus II flow of compiling a design (includes > > > synthesis, fitting of the circuit in an FPGA device and timing > > > analysis) and then simulate the design in Quartus using its own > > > simulator, would that be considered equal to gate level simulation ? > > > > > > Thanks, > > > PrashantArticle: 45776
Hi all, I need to choose an AES (rijndael) IP core to use in Xilinx VirtexE. There is a wide perplexing selection of core providers on the internet. Does anybody have any recommendation regarding who is the best (performance & cost)? Also, I would highly appreciate it if anybody who has used an AES core from some core provider can share their experience on: 1. Did it work? 2. Was it easy to use? 3. How was the technical support? 4. Do you recommend it? Any information will be highly appreciated, KrishnaArticle: 45777
In article <c6efc5c9.0208050742.187cb4de@posting.google.com>, kkps <kkps@rapid5.com> wrote: >Hi all, > >I need to choose an AES (rijndael) IP core to use in Xilinx VirtexE. >There is a wide perplexing selection of core providers on the >internet. Does anybody have any recommendation regarding who is the >best (performance & cost)? Don't be afraid of designing your own, its not that big a deal. EG, my design isn't probably usable as a core to you (it is done as schematic, encryption only, at http://www.cs.berkeley.edu/~nweaver/rijndael/ ) but it should give you a good idea of how big it should be and how fast and desgin strategies to use. A good number should be ~800 slices and 10 BlockRAM for a >1.8 Gbps core in a Virtex E. For core selection... You need to make a decision on modes early, as this affects the design. IF you want to use CFB or CBC mode (feedbakc modes), you will want a latency optimized core: Single round, no pipeliing. Otherwise, if you are using CTR more or another no feedback mode, or many simultanious streams, you want a single round which is pipelined. If you CAN, use CTR mode only, it has no feedback cycles and only requires an encryption core, no decryption core. You probably want a key agile core, simply because it costs effectively nothing. In such a case, you want the encryption pipeline to output the last sets of keys for a decryption core. Amphion and Helion both seem to have competitive cores, but I've never worked with them, only read the data sheets. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 45778
It sounds like you are referring to an external chip. You can make a
sound generator inside the FPGA, which can range from a simple clock
generator to a DDS to drive a to a table based generator, and you can
use arithmetic to handle multiple channels. Depending on your
requirments, you can drive either a DAC or use a PWM through a simple
RC filter to get your sound output.
Tim Riemann wrote:
> Hi,
> does anybody know if there exists an FPGA soundchip? Maybe with FM
> synthesis?
>
> TIA Tim
>
> --
> Tim Riemann
> octoate@-SPAMREMOVE-.tcs-software.de
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45779
You can download ModelSim XE-Starter from ISE WebPACK download page.
(You will have to log in first.)
After you install ModelSim XE-Starter, it will ask you if you want to
obtain a license.
Although I know that ModelSim XE-Starter is crippled, the nice
(?) thing about it is that it is free and has no limitation on the size
of the design it can simulate.
However, if you try to simulate a design larger than 500 lines of HDL
code, ModelSim XE-Starter's simulation performance starts to suffer.
I do run a design that exceeds the 500 lines limitation by about 3,000
lines daily, but at least for my application, I find the simulation
performance acceptable.
Since it's a freebie, I won't complain about the simulation performance.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Reala wrote:
>
> Dear all,
>
> I know that there is a "starter version" of modelsim which is free.
> Where can i download and get the licence for "starter version"??
> Thank a lot.
>
> Reala
Article: 45780
Not.
Check out app notes XAPP653 and XAPP646. Only PCI and LVDCI can even come close, and at that you have to put in a hack to guarantee the pin will *never* exceed 3.6V from Vdd or Vss.
Software support for other 3.3v modes was removed in ISE4.2sp3.
Ken Ryan
Article: 45781Tim Riemann <tcs-software@t-online.de> writes: > does anybody know if there exists an FPGA soundchip? Maybe with FM > synthesis? Absolute minimal way to make sound with an FPGA is documented here: Virtex Synthesizable Delta-Sigma DAC http://www.xilinx.com/xapp/xapp154.pdf -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - Make your code truely free: put it into the public domainArticle: 45782
"Maurizio Stefani" <mstefani@elesia.it> wrote in message news:ailh1p$2rc5$1@newsreader1.mclink.it... > Hi, > I developed a design using two 22V10 using WARP by Cypress. > Now, in the production phase, we would like to use the GAL by ATMEL, I tryed > to use the ATMEL development sw but I am encontering a lot of problem to > pass the Cypress VHDL description. > After a lot of time I was able to pass the VHD source to an ATMEL program > named PeakFPGA but this program will not produce the .JED file needed to the > programmer. > > Is there someone able to help me with another more friendly tools or with a > tool to pass the .Jed produced by WARP to the .Jed required by ATMEL (it > seems that the two .jed are not equal). > > Thank you in advance Maurizio, First, PeakVHDL is a simulator, not a synthesizer or .jed builder so quit wasting your time on PeakVHDL. Second, you do not tell us what GAL by Atmel you are using, nor do you tell us if you are using one or two of them to replace the two 22V10 SPLDs from Cypress. My advice to you is to contact Atmel and have them fit the VHDL design into the Atmel chip. They will be more than glad to do this, knowing that they are going to win a socket from Cypress. If you don't like this free service from Atmel, you can pay me the big bucks to do the same thing for you. :) Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL USAArticle: 45783
> However, if you try to simulate a design larger than 500 lines of HDL > code, ModelSim XE-Starter's simulation performance starts to suffer. > I do run a design that exceeds the 500 lines limitation by about 3,000 > lines daily, but at least for my application, I find the simulation > performance acceptable. If I'm not mistaken, the limit is 500 *statements*, not 500 lines. JCArticle: 45784
Neil Franklin wrote: > Absolute minimal way to make sound with an FPGA is documented here: > > Virtex Synthesizable Delta-Sigma DAC > http://www.xilinx.com/xapp/xapp154.pdf Thx, it is a good start, but I think that I don't have the time to start the development of a complete soundchip :(. CU Tim -- Tim Riemann octoate@-SPAMREMOVE-.tcs-software.deArticle: 45785
Ray Andraka wrote: > It sounds like you are referring to an external chip. You can make a > sound generator inside the FPGA, which can range from a simple clock > generator to a DDS to drive a to a table based generator, and you can > use arithmetic to handle multiple channels. Depending on your > requirments, you can drive either a DAC or use a PWM through a simple > RC filter to get your sound output. Yes, that should be possible, but what I am thinking of is a soundchip like the YM262 OPL3 chip by Yamaha or maybe some of you remember the good old SID chip. Of course I would only get digital output, but that wouldn't be a problem, but is there a source where I can find a ready to use VHDL/Verilog implementation of such a complex chip? CU Tim -- Tim Riemann octoate@-SPAMREMOVE-.tcs-software.deArticle: 45786
I'm not aware of any commercial IP for a sound chip in an FPGA. As far as
standalone sound chips go, those have pretty much gone the way of the dodo
because the DSP based sound cards are so much more capable. YOu might have
better luck finding sounc generator code for a DSP micro and then using that as
an add-on outside the FPGA.
Tim Riemann wrote:
> Ray Andraka wrote:
>
> > It sounds like you are referring to an external chip. You can make a
> > sound generator inside the FPGA, which can range from a simple clock
> > generator to a DDS to drive a to a table based generator, and you can
> > use arithmetic to handle multiple channels. Depending on your
> > requirments, you can drive either a DAC or use a PWM through a simple
> > RC filter to get your sound output.
> Yes, that should be possible, but what I am thinking of is a soundchip like
> the YM262 OPL3 chip by Yamaha or maybe some of you remember the good old
> SID chip. Of course I would only get digital output, but that wouldn't be a
> problem, but is there a source where I can find a ready to use VHDL/Verilog
> implementation of such a complex chip?
>
> CU Tim
>
> --
> Tim Riemann
> octoate@-SPAMREMOVE-.tcs-software.de
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45787Maybe about $360 each. Now Engineering Sample. Full prodution is 2003 Q1. "Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:aic1od$lkv$1@agate.berkeley.edu... > Does anyone know what the ballpark prices for the XC2VP4 part is today > in small (~10) and large (~25,000) quantity? > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 45788
Not much we can tell from the design summary other than the size of the device and the percent utilization. You need to open
up the timing analyzer and look at the paths that are failing timing. Once you know what paths are failing, then you can
address fixes for the timing whether that is adjusting constraints to relax timing on non-critical (and multicycle) paths,
floorplanning to reduce distances on the critical path, or altering the design to reduce levels of logic and/or fanout.
sf wrote:
> in my project,my resource reports is:
> ************************************
> Design Summary:
> Number of errors: 0
> Number of warnings: 137
> Number of Slices: 33,366 out of 33,792 98%
> Number of Slices containing
> unrelated logic: 0 out of 33,366 0%
> Number of Slice Flip Flops: 32,997 out of 67,584 48%
> Total Number 4 input LUTs: 46,525 out of 67,584 68%
> Number used as LUTs: 44,818
> Number used as a route-thru: 1,691
> Number used as Shift registers: 16
> Number of bonded IOBs: 156 out of 684 22%
> IOB Flip Flops: 171
> Number of Block RAMs: 137 out of 144 95%
> Number of GCLKs: 7 out of 16 43%
> Total equivalent gate count for design: 9,605,081
> Additional JTAG gate count for IOBs: 7,488
> ************************************
>
> i add the constrain for my clock,and i hope it can be 83M.after p&R,it is only 50M.how should i meet my clock constrain?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45789Hi, I got your idea, but i was wondering whether it would be possible to view the data of the memories in my architecture , without explictly making them write on the display. Thanks, Ram. "Holger Kleinegraeber" <nul@nul.com> wrote in message news:<aili21$14q134$1@ID-69700.news.dfncis.de>... > "Ramakrishnan" wrote > > > that , " how would i be able to download or include the > > text file somehow in my program > > Which program? It's a hardware description. > You can define a constant in your package. An array of integer which holds > your values, or a std_logic_vector which holds your data in the form of > zeros and ones. > Then the syntheziser extracts a rom, which holds your data. > > Greetings, > HolgerArticle: 45790
Hi, I would like to know what tools are needed for custom IC design in a commercial IC design. How much they are? I find that many EDA tools are running on Sun OS. It seems that all Good tools do not support PC. Am I correct? RealaArticle: 45791
Hi, It may be useful to design at the very low level: Setting programmable switches, MUXes select lines, etc, individually. (useful for designing compact and fast library components, for example). Is there any straightforward way (e.g. schematic/text editors) to do that?Article: 45793
> Depending on the size of your design, I > bet you don't need a synthesis tool at all - in fact, if you produce a good > set of libraries, even very large designs don't need it. Just do your > design using schematics. Use a well-planned hierarchy and do a good job of > documentation. I know in the past that schematic-capture was the traditional design-entry method for digital-logic. But with today's crazy gate-counts and SoCs, is that really still practical?!? For maybe a small block or two, but the entire design? > For simulation, you can buy an expensive simulator... or you can use a free > one. I have had great success using both C and Pascal. You have to write > some infrastructure, though. Ok this approach might work for you, but I think this is VERY RISKY for a *FIRST-TIME* ASIC developer. At a minimum I would use a Verilog/VHDL simulator on the foundry's signoff-checklist (Cadence, Mentor, or Synopsys. I'm sure there are more.) > Depending on what ASIC vendor you use, they might do P&R of both logic and > clocks for you. That's true. You can hand-off a synthesized netlist (or maybe even VHDL/ Verilog in RTL source form) to the foundry. But you still need to meet their sign-off checklist. > If not, if you plan well, and your design isn't huge, you > can even do that yourself with some basic graphical tools. As for doing it yourself, that's not a wise choice for a first time ASIC developer. A lot of things can go wrong (if you do it yourself with no prior experience), and you could potentially waste a lot of money in re-fabbing the entire design to fix some layout error.Article: 45794
> Yes, that should be possible, but what I am thinking of is a soundchip like > the YM262 OPL3 chip by Yamaha or maybe some of you remember the good old > SID chip. Of course I would only get digital output, but that wouldn't be a > problem, but is there a source where I can find a ready to use VHDL/Verilog > implementation of such a complex chip? Check out the MAME game emulator project (www.mame.org) MAME is a arcade game emulator. It has C-source code for emulating (in C-software) hundreds of arcade hardware pieces. Not quite what you want (VHDL/Verilog), but with persistence, you should be able to translate the C-implementation into VHDL or Verilog. I don't know about your specific chip (YMF262), but many other Yamaha sound chips are emulated. Alos, the emulation quality varies from part to part. Some emulations are practically perfect, others are obviously flawed. The YMF262 is relatively simple compared to some of Yamaha's other chips (like the Ym2151 and 2610/2612) ... The MAME source code takes a little time to understand. Also plan on spending at least a week to understand the emulation mechanics (remember this the C-source code runs a 'virtual' hardware environment in software!)Article: 45795
Hi, FPGA gurus,
My question is "Is it necessary to instantiate the IPAD, OPAD, IBUF, OBUF,
IBUFG, ... in my HDL code of top-level ?"
----- if NO,
when I have to insert BUFG or/and BUFT explicitly, how to code to insert
what I want solely?
For example, a piece of code as below :
===============
-- MCU interface unit :
......
entity mcu_interf is
port(
clk : in std_logic;
rstn : in std_logic;
din : in std_logic;
addr : in std_logic_vector(0 to 7);
wrn : in std_logic;
dout : out std_logic_vector(0 to 7)
);
end mcu_interf;
......
-- the top level :
entity top is
port(
clk : in std_logic;
rstn : in std_logic;
data : inout std_logic_vector(0 to 7);
addr : in std_logic_vector(0 to 7);
wrn : in std_logic
);
end top;
Now, I must to instantiate a BUFT in top-level between "dout" of mcu_interf
and "data" of toplevel. Here, my wander is how to deal with the input
direction?
----- if YES,
If I add PAD and IOBUF for every port, I must not delare them in the port
list? And what this result for simulation? I get this info from here :
http://support.xilinx.com/xlnx/xil_ans_display.jsp?BV_SessionID=@@@@01509967
06.1028610616@@@@&BV_EngineID=cccgadcfledikjecflgcefndfgldfmi.0&getPagePath=
6085&iLanguageID=1&iCountryID=1
Would someone help me?
daryl
Article: 45796KVLKCL wrote: > I don't know about your specific chip (YMF262), but many other Yamaha > sound chips are emulated. Alos, the emulation quality varies from part This is just the chip which you have on the soundcards (up to the AWE64). It was used to generate the Adlib sound. > The MAME source code takes a little time to understand. Also plan on > spending at least a week to understand the emulation mechanics (remember > this the C-source code runs a 'virtual' hardware environment in > software!) Ok, I will have a look at it... CU Tim -- Tim Riemann octoate@-SPAMREMOVE-.tcs-software.deArticle: 45797
Ray Andraka wrote: > I'm not aware of any commercial IP for a sound chip in an FPGA. As far as > standalone sound chips go, those have pretty much gone the way of the dodo > because the DSP based sound cards are so much more capable. YOu might > have better luck finding sounc generator code for a DSP micro and then > using that as an add-on outside the FPGA. Ok, I will have a look at it and try to find a sound generator for DSPs. Maybe I have a little bit luck and find one which fits my needs =). CU Tim -- Tim Riemann octoate@-SPAMREMOVE-.tcs-software.deArticle: 45798
I saw that Xilinx was hiring for VLSI guys with some substantial experience, not just Verilog coders, but transistor level, HSpice, layout, the works etc. I just happen to fit the bill and being an FPGA nut as well, but I am out of state & MA based. As I was just about to expect a pre screen call, I was told that I would not be interviewed unless I waived the benefit of a relocation package as the budget is really tight. Of course I was working with a head hunter so it must be even more really tight. I was somewhat dumbstruck, flabbergasted, and somewhat pissed off. This would seem to be a blatant form of either age or distance related discrimination as I believe that many older engineers will have left the valley. But Si valley is where the action is as any job search will show so I was willing to go back even if the cost of living was much much higher than MA, and salary likely much lower and now apparently I have to buy the job. Is this true Peter, Austin, is it common that relocation is gone in the valley. I am sure that Peter didn't just walk from Denmark? to SJ to start work for what I thought was a remarkable company. John JaksonArticle: 45799
I am looking for some experiences (either good or bad) with Xilinx MicroBlaze running in bus configuration 1 (shared external code and data memory). Did anybody manage to create a "real life" product in this configuration? If so, is anybody willing to share experiences with me? Any comments very much appreciated, best regards Felix
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Compare FPGA features and resources
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