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Hi there. Has anyone already V2.1 of ALTERA´s QUARTUS II ? I hope that with 2.1 my design becomes better (timing problems)..... Has anyone experiences if 2.1 does a better job with ACEX 1k devices ? I have problems with slack times. I thought that QUARTUS tries to meet the timings but it seems as if QUARTUS uses the first successfull fit and does not try again if timings are not met. Or is this a thing of settings and I can set an option so that QUARTUS tries again ? Thanks in advance SvenArticle: 46326
default <default@nortelnetworks.com> wrote in message news:<3D623724.8C7D9BE4@nortelnetworks.com>...
> Hi Tom
>
> For digital filter design on FPGA...try ONEoverT from www.tyder.com.
> The RTL VHDL module is supplied free until the end of September. The whole
> package works out quite cheap....about $500 although this maybe more than
> what you want to spend.
>
Can't seem to get tyder the website to work, get:
Undefined catalog: /~tyder/cgi-bin/cart.cgi
$500 is out of my budget anyway.
Tom
Article: 46327christopher.saunter@durham.ac.uk (Christopher Saunter) wrote in message news:<ajtgme$3ai$1@sirius.dur.ac.uk>... > Hi Tom, > I have been trying something similar and have found using a > numerically competent and flexible programming language to be a real help > for DSP-FPGA work. I guess it's a question of if you want to spend time > or money... > <snip> > some links: > Python www.python.org > SciPy www.scipy.org <-- some visualisation, maths etc. I don't really want to spend a lot of time on programming and getting the environment setup. I want to spend my time on the actual understanding of the DSP algorithms and good architecture and design. I'll take a look at python. Thanks, I wouldn't have thought of that option myself. TomArticle: 46328
Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3D62523E.27315AB9@xilinx.com>... > Tom, > > There is: http://ptolemy.eecs.berkeley.edu/ > > which is incredibly useful and powerful. I have been told that some of the top three Austin, Thanks for the tip. At first look, it looks like it might be a little too academic and software focused. But maybe I can dig out the useful pieces like the math and signal processing functions and put them to use. I certainly agree that I am not interested in reinventing the wheel. Thanks, TomArticle: 46329
"Richard Schwarz" <Rick@associatedpro.com> wrote in message news:<8FR89.9867$u7.774805@news.direcpc.com>... > D S P TUTORIALS PAGE > > > > APS Begins its Virtex VHDL and DSP tutorials > > > goto: > http://www.associatedpro.com/dsp.html > Thanks, but this looks more like it would fit a corporate training budget than an individual/hobbyist budget. Although I would like to play with the latest Virtex parts, I am thinking that a lower end FPGA might be good enough and much lower cost. TomArticle: 46330
I've posted the technique for that here before. Look in google under
comp.arch.fpga and comp.lang.vhdl for "barrel shift". You should find my
comments.
liran wrote:
> doe's anyone has an example for writing "shifter" in vhdl
> "shifter" - means takeing a nember with 8 bit and "placing" it into a
> 32 bit vector , in a place choosen by anther integer , streching the
> other bits
>
> example :
>
> input :
> data:8 std_logic_vector;
> move: integer;
> output :
> data_out : 32 std_logic_vector;
>
> for input: data = 11110000
> move = 0
> output : 111111...11110000 ( takes the msb of the input and strach it
> all over )
>
> for input: data = 11110000
> move = 2
> output : 111111...1111000000 ( takes the msb of the input and strach
> it all over, add zeros for lsb as move indicates )
>
> for input: data = 01010101
> move = 3
> output : 000...01010101000 ( takes the msb of the input and strach it
> all over, add zeros for lsb as move indicates )
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46331
Ecliptek and Fox come to mind. You can get them from
digi-key or mouser for about $2 in quantities of 1
BasePointer wrote:
> Thanks for your responses.
> Can you advise a component/company for canned oscillator?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin,
1759
Article: 46332Hello all, I'm planning to try some VHDL stuff in order to load it into an FPGA and 'play' with it a little. For the moment, I'm still searching for free/freeware compilers and simulation tools. Any recommendations?? I already found the Alliance tools. Any comments?? I saw on the GNU page the 'Electric' package, wich claims to have a VHDL compiler and simulator in it. Any experiences with this?? Kind regards, Jan -- Jan Van Belle Jan.Van_Belle@advalvas.beArticle: 46333
Austin Lesea (austin.lesea@xilinx.com) wrote: : There is: http://ptolemy.eecs.berkeley.edu/ Austin, Thanks for the link - looks like a powerfull tool. : Don't re-invent the wheel. This code is partially delivered in some commercial : products now according to the grape-vine. I'm not sugesting trying to produce anthing as mature and featured as Ptolemy appears to be, but if you are a born tinkerer, taking a few dys to knock up a simple simulator for synchronous logic is quite interesting. Using a decent OO language takes 95% of the grunt work out, and there is a lot to be learnt from the experience. Writing a simple simulator gave me much more of an insight into using VHDL (the conecpts, if not the syntax...) for FPGAs than any of the books I've been reading. Regards, Chris SaunterArticle: 46334
I'm interested in analogue programmable arrays (FPAA, TRAC, PSOC, ispPAC etc.). I'm looking for someone who can tell me more about them or knows where i can find more information about them. Or maybe is someone looking for this information too. I already looked at these web sites: Motorola Zetex Lattice semiconductor University of Toronto, Field programmable analog array Cypress Anadigm who can help me? DennisArticle: 46335
Hi. For a future project, I plan to use a XILINX FPGA with ~1M Gates and DES encrypted bitstream. Is Virtex-II is the only appropriate family? Can you recommend an evaluation board? It should be affordable. I don't need external stuff like LCD etc, just the FPGA (already fitted), configurator, download cable, and all I/Os available on 2.54mm pins. What's the pricing for 1M gates Virtex-II slowest speed grade, at quantities of 100? What price can be expected in -say- 18 months from now? MarcArticle: 46337
You may want to consider putting together an Excel macro that will read the file and populate cells and plot charts. It may or may not be worth the time, depending on how much time you are going to spend debugging your filter in this manner. It can save a lot of tedious and repetitive cut/paste/import/plot operations. "Børge Strand" wrote: > I was hoping that there would be a cut/paste solution between graph and > excel vector. But that was hoping for a bit too much. > > Thanks for the tip, I got it working with $monitor in Verilog and cut/paste > into a textfile which I then imported. > > Børge > -- Davis MooreArticle: 46338
Just for the record, let me explain: Virtex and Spartan-II devices (prior to Virtex-II, where this problem is thoroughly licked) have an inrush current spike that starts the moment you apply Vcc. There is no way to delay this current by holding off configuration, since the configuration process itself has nothing to do with this. The excessive temporary current is there prior to the clearing of all configuration memory cells which always starts as soon as Vcc is above a certain threshold value. XAPP451 describes the various work-arounds in detail. Remember Fahrenheit 451 ? :-) Peter Alfke, Xilinx ApplicationsArticle: 46339
Charles I implement a LOS(lose of signal) detector with the following code, it should work for you too. and it only costs 4 flop flip. the idea is if the external clock is faster than internal clock the should be at least one external clock during one internal clcok. Process(ref_clk,ex_clk) --ref_clk is a lower than ex_clk if (ex_clk='0') then -- if ex_clk is low clean the ref_clk event flag ref_clk_delay1<='0'; ref_clk_delay2<='0'; elsif (ref_clk'event and ref_clk='1') then ref_clk_delay1<='1'; -- a flag indicates ref_clk event ref_clk_delay2<=ref_clk_delay1;-- one clock delay end if; end process; Process(ref_clk,ex_clk) if (ex_clk='1') then -- if ex_clk is high clean the ref_clk event flag nref_clk_delay1<='0'; nref_clk_delay2<='0'; elsif (ref_clk'event and ref_clk='1') then nref_clk_delay1<='1'; -- a flag indicates ref_clk event nref_clk_delay2<=nref_clk_delay1;-- one clock delay end if; end process; LOS <= ref_delay1 or nref_dealy1;-- in the case of external clock is floating, it maybe high or low depending on if you pull it up or down. Good luck Peng "Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl> wrote in message news:<gala9.2179$Br2.6103@amstwist00>... > Hi Charles, > > > Currently, I am thinking that counting some number of oscillator cycles > from > > both inputs with an always statement (in Verilog) and setting a terminal > > count of say 10000 cycles for the external and 100,000 cycles for the > > internal. They are both the same frequency. If the external doesnt reach > > terminal count before the internal one does, then I would run the logic > > circuitry off the internal oscillator. The only reason the external one > > would not reach terminal count first would be if it is not active. > > > > So, the question for Sunday is, "Is this a reasonable way to sense an > > external/internal oscillator or is there a better way?" > > Whatever you do (and I think that your method is OK, but counting to 10000 > is a bit of overkill - 3 or 4 clock transitions should do just fine), don't > forget to use a pull-up or pull-down resistor with the external clock pin. > I've had a lot of trouble with floating input pins on a broken connector > once - it picked up just enough RF to fake the presence of the pin but in > the end only transmitted garbage. > > Best regards, > > > BenArticle: 46340
Could someone clarify the usage of this pin? As I understand it, when tied to Vcc user I/O is left without pullups during configuration. By "user I/O" I understand all I/O signals on all banks. Thank you, -- Martin E. To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 46341
Is there a version of WebPack that supports any of the newer Virtex2 Pro devices? Or do I need to get ISE? Thanks for any replies.Article: 46342
In article <15cf85fc.0208230726.17d8c59c@posting.google.com>, Ramakrishnan <rxv20@po.cwru.edu> wrote: >Hi, > I think i got lost in the response to my original query. I have >access to Xilinx FPGA Demo board which contains Xc4003E and XC3020. >Now after looking at the description of the board, i don't know >whether XC3020 is a FLASH or not . >People in this thread have said that i could store the two bit streams >to a FLASH and download the appropriate bitstream to the FPGA as and >when required. > >Now my question is whether i need to plug in an external FLASH to >Xilinx demo board ?. If i want to do that, i think it would be quite >similar like connecting a host computer to the FPGA board and >downloading bitstreams as and when required and this is what i have >seen in a lot of research papers. > > >Thanks, > >Ram. >"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message >news:<ak3fo4$1f99rt$1@ID-84877.news.dfncis.de>... >> "Ramakrishnan" <rxv20@po.cwru.edu> schrieb im Newsbeitrag >> news:15cf85fc.0208220811.101ec55c@posting.google.com... >> > Hi, >> > Is there a way i could download two bit streams to a single Xilinx >> > FPGA board when starting up ?. and also is it possible for a >> > controller to switch between the two bit streams while in operation?. >> >> Sure. just store the two bitstreams in FLASH/RAM, and choose (and download) >> the appropiate to the FPGA. It sounds like you have one of the "old" Xilinx FPGA demo boards. The documentation for these is still available: from Xilinx's home page go to Support => Documentation => 2.1i SW Manuals; under "Foundation Series" look at "Hardware User Guide" ch. 3, "FPGA Design Demo Board". Neither of the FPGA's is a FLASH part, but the board has sockets for a serial PROM for each FPGA. I think you can also use daisy chaining to configure both chips from the 4000's PROM. It is possible to store multiple bit streams in the PROM and select one of them to be loaded. Read the section on "Configuration Switches" to see how. -- Caleb Hess hess@cs.indiana.eduArticle: 46343
Martin, When tied to Vcco, all IOs are tristate until configured. When grounded, all IOs have the weak pullups enabled until configurated. Austin "Martin E." wrote: > Could someone clarify the usage of this pin? > > As I understand it, when tied to Vcc user I/O is left without pullups during > configuration. By "user I/O" I understand all I/O signals on all banks. > > Thank you, > > -- > Martin E. > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu"Article: 46344
page 343 of the Virtex II handbook http://support.xilinx.com/products/virtex/handbook/ug002_ch3.pdf (chapter 3 on configuration) Austin Austin Lesea wrote: > Martin, > > When tied to Vcco, all IOs are tristate until configured. > > When grounded, all IOs have the weak pullups enabled until configurated. > > Austin > > "Martin E." wrote: > > > Could someone clarify the usage of this pin? > > > > As I understand it, when tied to Vcc user I/O is left without pullups during > > configuration. By "user I/O" I understand all I/O signals on all banks. > > > > Thank you, > > > > -- > > Martin E. > > > > To send private email: > > 0_0_0_0_@pacbell.net > > where > > "0_0_0_0_" = "martineu"Article: 46345
Tom, It sounds like you are also looking for an FPGA board. We sell a board that has the latest Spartan2E XC2S300E on it, for US$179. The XC2S300E is the largest device supported by the free WebPACK tools. http://www.burched.com.au/B5Spartan2.html With this board, the total cost of ownership of tools plus board with a large FPGA, is now within reach of many individuals/hobbyists/students. To verify your hardware DSP implementations, you will also need some way of getting the signal data to and from the FPGA. It doesn't necessarily need to be real-time to verify your functions. Maybe you could consider a parallel-port interface, or a serial port link for this purpose. You can observe results/signals by plotting the data using Excel, or your favourite plotting program. HTH:) Good luck and enjoy your hardware DSP journey:) Best regards Tony Burch http://www.BurchED.com Low cost FPGA boards, for System-On-Chip prototyping and education > > Thanks, but this looks more like it would fit a corporate training > budget than an individual/hobbyist budget. Although I would like > to play with the latest Virtex parts, I am thinking that > a lower end FPGA might be good enough and much lower cost. > > TomArticle: 46346
In my experience you can do 99% of the job in simulation, but often the design will fail in a really odd fashion (occasionally) when it gets used for real. We get the "It works perfectly in simulation but ..... " I use a 2Gig b/w digital scope, but have never actually had a fault that was due to a timing problem - it's always been a real genuine logic bug that occurs it a situation you never thought of when you wrote the test bench. Where I have spare pins, I wire them up to a dedicated logic analyser connector (16 data + clock where possible) and rebuild the design to bring out suspect sigs until I have found the problem. As Paul says, you need to be careful that your test header doesn't break your high speed pcb routing. If you are grabbing 'real' traces use flow through routing. I then use Reflection-X to put the Agilent logic analyser display on the same screen as the simulator and find the difference. Ray is correct in that it is better to get the design right first, but it is easier to chase an elusive bug with the analyser that the simulator, believe me ! we have 2 x analysers to 'scopes. Remember kids, test gear is optional until you actually need it - then it is really worth it. Cheers, Mike. "Paul" <nospam@needed.com> wrote in message news:nospam-2108022240060001@192.168.1.177... > In article <ea62e09.0208211211.1334e12a@posting.google.com>, > prashantj@usa.net (Prashant) wrote: > > > Hi, > > > > I have a prototyping board from Altera for testing my design. I'm new > > to using a prototype board and hence had some questions. The device in > > the prototype board is a EP20K1500E. > > > > Does anyone have views on whether I would need a logic analyzer with > > this board ? Do people who use prototype boards always use analyzers ? > > Is there an alternate way out without using analyzers ? Any > > recommendation on which logic analyzer should I use ? > > > > Thanks, > > Prashant > > Really, it depends on your budget and how much time you have to complete > a design, as to how much equipment you buy for development purposes. > > As others have pointed out, it can be difficult to see what is going > on inside an FPGA. (In another post, Austin mentions ChipScope, which > is a macro inside the device you can use to sample internal signals.) > One option is to dedicate a number of outputs on your design, where > each output is driven by a multiplexer tree which is connected to > the important nodes in your design. You then use jumpers to control > which internal multiplexer input is used to drive these spare outputs. > The multiplexer tree is P&R with the rest of the design, so it doesn't > have to be added later. > > Once any signals are available outside the chip (either test outputs > or real outputs), you can place a connector on the board which is only > populated on your lab prototype. For example, some analyzers have > probe inputs which connect to a small Amp Mictor connector. The Mictor > allows a 50 ohm environment to be maintained from the board to the > analyzer. If the signal traces flow "through" the connector on the > board, there is minimal signal integrity degradation when the connector > is removed in production. > > If you have zero budget for test equipment, I would still plan on > some kind of approach to test. Later, if you get desperate, you can > always lease test equipment for a month or two if the need arises. > > Simulation testbenches have really improved the bringup process for > designs in the lab. If you have a mainly datapath design, you can > frequently see positive results within a couple of days of delivery > of your populated board, if the design was simulated thoroughly > before design close. > > Where simulation sometimes breaks down, is at the board level. > Depending on the size of the design, it can sometimes be difficult > to load an entire board in simulation, so a piecewise approach > might be required. Also, encrypted behavioral models are not > always available for all the devices on your board. > > In a big company, I have seen a 4 channel digital scope on each > designers lab bench, while there are 2 logic analysers shared > for every 15 lab benches. This should give you some idea as to > which equipment has the highest utility. > > A digital scope with 1Ghz bandwidth can deal with making timing > measurements and checking signal integrity on "run of the mill" > CMOS interfaces. For a home project, even a digital scope can > be more than you can afford. > > If you ever plan on selling what you design, you should still do > some signal verification before releasing the design to production. > Leasing a bit of test equipment is much cheaper than a field > recall of your design. > > PaulArticle: 46347
Austin, Thanks for your note. I did read the configuration section of the manual. I guess where I got stuck was in trying to determine the pins HSWAP_EN affects. For example, does it affect "DONE"? How about M0, M1 and M2? And the other config pins? If it did I could eliminate some pullup resistors. Thanks again, -Martin "Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3D6A8C76.B8A9EA70@xilinx.com... > page 343 of the Virtex II handbook > > http://support.xilinx.com/products/virtex/handbook/ug002_ch3.pdf > (chapter 3 on configuration) > > Austin > > Austin Lesea wrote: > > > Martin, > > > > When tied to Vcco, all IOs are tristate until configured. > > > > When grounded, all IOs have the weak pullups enabled until configurated. > > > > Austin > > > > "Martin E." wrote: > > > > > Could someone clarify the usage of this pin? > > > > > > As I understand it, when tied to Vcc user I/O is left without pullups during > > > configuration. By "user I/O" I understand all I/O signals on all banks. > > > > > > Thank you, > > > > > > -- > > > Martin E. > > > > > > To send private email: > > > 0_0_0_0_@pacbell.net > > > where > > > "0_0_0_0_" = "martineu" >Article: 46348
Never mind ... I got my answer. Thanks again. -Martin "Martin E." <0_0_0_0_@pacbell.net> wrote in message news:xXya9.6208$9G4.633531620@newssvr13.news.prodigy.com... > Austin, > > Thanks for your note. I did read the configuration section of the manual. > I guess where I got stuck was in trying to determine the pins HSWAP_EN > affects. For example, does it affect "DONE"? How about M0, M1 and M2? And > the other config pins? If it did I could eliminate some pullup resistors. > > Thanks again, > > -MartinArticle: 46349
--------------856F274900D704E0594DFFE6 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Martin, The key words here in the paragraph is "affects all user ios".... That excludes dedicated ios. We generally refer to ios as either user, or general ios, and as dedicated ios. So, DONE, M0, etc. are all dedicated pins. I would not rely on an internal pullup on the mode pins (or done), as noise can easily overwhelm the weak pullup and trigger unusual results. Tie the pins high thru a resistor, or to ground, to make sure there is no issue with cross talk noise getting into these pins through traces on the pcb. DONE can be configured to actively pull high after configuration in complete and successful (start up options). Austin "Martin E." wrote: > Austin, > > Thanks for your note. I did read the configuration section of the manual. > I guess where I got stuck was in trying to determine the pins HSWAP_EN > affects. For example, does it affect "DONE"? How about M0, M1 and M2? And > the other config pins? If it did I could eliminate some pullup resistors. > > Thanks again, > > -Martin > > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message > news:3D6A8C76.B8A9EA70@xilinx.com... > > page 343 of the Virtex II handbook > > > > http://support.xilinx.com/products/virtex/handbook/ug002_ch3.pdf > > (chapter 3 on configuration) > > > > Austin > > > > Austin Lesea wrote: > > > > > Martin, > > > > > > When tied to Vcco, all IOs are tristate until configured. > > > > > > When grounded, all IOs have the weak pullups enabled until configurated. > > > > > > Austin > > > > > > "Martin E." wrote: > > > > > > > Could someone clarify the usage of this pin? > > > > > > > > As I understand it, when tied to Vcc user I/O is left without pullups > during > > > > configuration. By "user I/O" I understand all I/O signals on all > banks. > > > > > > > > Thank you, > > > > > > > > -- > > > > Martin E. > > > > > > > > To send private email: > > > > 0_0_0_0_@pacbell.net > > > > where > > > > "0_0_0_0_" = "martineu" > >
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