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Greetings All, I just saw the following post on comp.dsp: http://groups.google.com/groups?q=ni+niweek+labview+fpga&hl=en&lr=&ie=UTF-8&selm=3D6D58E5.1BE95798%40NAESPAM.yahoo.com&rnum=2 It looks like National Instruments LabVIEW code being targeted to Xilinx devices. LabVIEW offers a high level graphical programming language, and perhaps the way it is organised and used makes it more likely to benefit from automated targeting to FPGAs than 'c' style languages? I doubt it'll change the way I use FPGAs (gimmie LUTs... ;-) but I can see it going down well with many LabVIEW users who need to produce fast data processing hardware etc. --- cdsArticle: 46426
HI,everyone we are now developing 1553 terminals(BC,RT,BM) on an ISA PC card. Within the whole architecture of our design, there is a 1553 protocol chip which is implemented by FPGA. We hasn't determined which company's ASIC to use presently. My question may be a stupid one: whether we can find a development board just like a DSP Emulator or a MCU development board, or which company ever provide such kind of board. I know some companys(such as DDC,Condor) do provide ISA/PCI/VXI 1553 simulators and they declare that their products can be used for development, but I don't know which kind of development they mean. It seems that their development means system design that process Major/Minor Frame and network interconnecting, which is not what I need. Now I'm hesitating if I should buy a card to assist my work. Should I? Thank you for your helps!Article: 46427
ds wrote: > Does that mean that SpartanIII is a VirtexII? > - ds Do NOT bet on that! Peter AlfkeArticle: 46428
Hi,
I'm writing with a query on use of the Handel-C language, please let
me know if there is a more appropriate forum in which to post.
If you write code such as:
/*
* lookup tables
*/
ram <signed int> trig_256[320] with {block = 1};
ram <signed int> trig_2048[2560] with {block = 1};
/*
* read in trig array into block ram (block = 1)
*/
chanin <signed int> input_trig_256 with { infile = "trig_256.dat" };
chanin <signed int> input_trig_2048 with { infile = "trig_2048.dat"
};
unsigned int 13 i; // index for looping arrays
i=0;
do
{
par
{
i++;
input_trig_256 ? trig_256[i];
}
} while (i!=320);
i=0;
do
{
par
{
i++;
input_trig_2048 ? trig_2048[i];
}
} while (i!=2560);
the compiler will complain that the index i does not agree with the
size of the first array, trig_256, which only needs an unsigned 9 to
access all its elements. How do I get round this 'properly'? The
following two work arounds have been found to function but aren't
ideal
[1] declare a new index variable each time I need to loop an array of
a different size - but code gets messy
[2] do not declare size of RAM, but let Handel-C infer it i.e.
ram <signed int> trig_256[] with {block = 1};
- doesn't work with more complex code
Gov
Article: 46429I want to do a 100MHz bus with the SSTL2 standard. This bus will be between a VirtexII and an ASIC (with SSTL2 I/O). I want to know if I must use the class I or II.(i.e SSTL2_I or SSTL2_II). This bus is bidirectionnal and I saw in the datasheet ds031.pdf (figure 12, Page 18/301), for the DIC, the class I in not available for bidirectionnal line. Does it means the bidirectionnal bus requires the class II, and with the class I ,i can't realize a bidirectionnal bus. Thanks a lot for your opinionArticle: 46431
"Jim Raynor" <chris_cheung66@hotmail.com> schrieb im Newsbeitrag news:8gdb9.18094$rn4.825937@news1.telusplanet.net... > hi, > > I am using Spartan 2E XC2S50E in my design. Configuring the FPGA is > done by using Serial Slave Mode. However, for some reasons when I powered > up the device, I saw a 3Mhz clk signal on the CCLK pin. I don't have 3M hz > clk running on my board and I actually lifted up the CCLK pin so the 3Mhz > clk signal is generated by the FPGA itself. > However, when I started loading the FPGA (Asserting Program Bar), the 3 > Mhz clk signal goes away and the FPGA is loaded successfully. > My concern is in the Spartan 2E datasheet, it specified that CCLK pin is > the input but it actually acts like an output when the FPGA is powered up. Watch out for the mode pins (M2..M1). They select the configuration mode. They have internal (weak) pull-ups, but if the are connected to a trace or so, the might catch some noise (So the FPGA might think it should work in master mode). Using external pull-ups (4k7 or less) may solve the problem. -- MfG FalkArticle: 46432
"nospam" <nospam@please.com> schrieb im Newsbeitrag news:pn4omus6b8obef3dc1uaat50q4t772ial1@4ax.com... > Peter Alfke <peter@xilinx.com> wrote: > > >If this interests you or anyone else, I can give you more details. > >This is one of my pet subjects... > > Is there something novel about the design (state machines built from a > clocked latch and PROM were used years ago) or is it just an efficient fit > in Virtex/Spartan-II parts? It is "just" a Virtex/Spartan-II fit. > There was a software package called Log/IC (or maybe and add on for Log/IC) > by Isdata which would design FSMs with an option for implementation in a > PROM. Iam sure that every VHDL/Verilog Synthesizer has a FSM optimizer. The documentation of XST says something about it, but not much. But XST produces a analysis for each FSM it founds (number of states, transitions etc.) For practical reason, you can select the desired encoding manually and compare the results. I havent done a further investigation into this subject yet, since one-hot or binary was always fast and compact to me. -- MfG FalkArticle: 46433
Hugo, Per the standard, class I is intended for unidirectional buses, and class II is intended for bidirectional buses. This can be clearly seen by examining the mirror symmetry of class II terminations. Some customers point out that class I can be used bidirectionally, but it neither meets the standard, nor performs as well as class II.....but if it works to your satisfaction, there are no "SSTL police" to prevent you from doing this. Austin Hugo wrote: > I want to do a 100MHz bus with the SSTL2 standard. This bus will be between a VirtexII and an ASIC (with SSTL2 I/O). > I want to know if I must use the class I or II.(i.e SSTL2_I or SSTL2_II). This bus is bidirectionnal and I saw in the datasheet ds031.pdf (figure 12, Page 18/301), for the DIC, the class I in not available for bidirectionnal line. Does it means the bidirectionnal requires the class II and the class I can't realize a bidirectionnal bus. > > Thanks a lot for your opinion.Article: 46434
Look into the texas instruments MSP430 users guide. This microcontroller contains an oscillator fault detector from which the operation is reasonable documented. "cfk" <cfk_alter_ego@pacbell.net> wrote in message news:wS7a9.503$352.38590774@newssvr21.news.prodigy.com... > I have a design where either an oscillator can be supplied externally on an > IOB input or I can generate it internally. Today I am struggling a bit with > the question of how to sense whether the external oscillator is connected > and if it is not, then to run some logic circuitry off the internal > oscillator. > > Currently, I am thinking that counting some number of oscillator cycles from > both inputs with an always statement (in Verilog) and setting a terminal > count of say 10000 cycles for the external and 100,000 cycles for the > internal. They are both the same frequency. If the external doesnt reach > terminal count before the internal one does, then I would run the logic > circuitry off the internal oscillator. The only reason the external one > would not reach terminal count first would be if it is not active. > > So, the question for Sunday is, "Is this a reasonable way to sense an > external/internal oscillator or is there a better way?" > > -- > Charles Krinke > http://home.pacbell.net/cfk > cfk@pacbell.net > >Article: 46436
First thing I would check the mode pins M0, M1, M2. What are their states at power-up? Have you pull them up? What option you select for these pin when you compile?Article: 46437
Hello all Im new to this FPGA design stuff so any help or redirection will be appreciated. My problem is this. I am feeding an FPGA with a 100MHz clock. Under certain conditions I want to feed this clock to a pin on my FPGA as an output. To allow for the condition I need to gate the Main clock with what I have below. assign Acquisition_Clk = qbar ? Main_clk:1'b0; // Acquisition_Clk will be the output clk from the FPGA. // qbar is the negated q from a previous D-type FF. What worries me is that I am feeding a CLK signal through a non clk path. The translation report even warns me as below: Checking expanded design ... WARNING:NgdHelpers:357 - clock net "Main_clk_ACLKed" has non-clock connections So if what Im doing is not advisable, what should I be doing to gate the main FPGA clk. Many Thanks Denis PS. I am targeting a xilinx XC3020Article: 46438
Denis, why are you designing something with, for, or in a 15-year old device? 100 MHz is easy today, but was not easy in 1987 when the XC3020 was designed. My suggestion is to use a much faster, bigger, and generally more sophisticated device with better software support, like Virtex, Spartan-II, or Virtex-II devices. Much easier, cheaper, and more rewarding. :-) Peter Alfke, Xilinx Applications Denis Gleeson wrote: > Hello all > > Im new to this FPGA design stuff so any help or redirection > will be appreciated. > > My problem is this. I am feeding an FPGA with a 100MHz clock. > Under certain conditions I want to feed this clock to a pin > on my FPGA as an output. > To allow for the condition I need to gate the Main clock > with what I have below. > > assign Acquisition_Clk = qbar ? Main_clk:1'b0; > // Acquisition_Clk will be the output clk from the FPGA. > // qbar is the negated q from a previous D-type FF. > > What worries me is that I am feeding a CLK signal through > a non clk path. The translation report even warns me as below: > > Checking expanded design ... > WARNING:NgdHelpers:357 - clock net "Main_clk_ACLKed" has non-clock > connections > > So if what Im doing is not advisable, what should I be doing to gate > the main FPGA clk. > > Many Thanks > > Denis > > PS. I am targeting a xilinx XC3020Article: 46439
comp.arch.fpga Any FSM optimizer The software distribution dept at the Berkley campus of the Univ. of Calif. has/had a minimizer available for roughly $100US. Intel included it in the software for their PLD's. I remember using it but not how effective it was. Hul - for email, put the word keep in the subject heading -- dogwoArticle: 46440
hi all, just a quick question, for a completely random read ( to different row /bank /column ) to DDR SDRAM RAM the sustainable data rate is ~ 70 ns, BL=4. ( base on Micron MT46V8M16-8, tRC = 70 ns, clk=100 mhz). right ? thanks pyngArticle: 46441
This patch is now on the Quartus II Web Edition download page at https://www.altera.com/support/software/download/altera_design/quartus_we/dn l-quartus_we.jsp "Kevin Brace" <kevinbraceusenet.killspam@killspam.hotmail.com> wrote in message news:akf5g6$79h$1@newsreader.mailgate.org... > > > ds wrote: > > > > A patch is available from Altera for QII 2.1 Web Edition. > > - Subroto > > > > > I checked Altera website, but all I found was the Service Pack > for QII 1.1 and 2.0. > The QII 2.1 Service Pack doesn't seem to be available yet. > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.)Article: 46442
I am implementing a tristate bus in virtex. Should the bus be pulled up or can they be left as it is?Article: 46443
> I want to know if I must use the class I or II.(i.e SSTL2_I or > SSTL2_II). This bus is bidirectionnal and I saw in the datasheet > ds031.pdf (figure 12, Page 18/301), for the DIC, the class I in > not available for bidirectionnal line. Does it means the bidirectionnal > requires the class II and the class I can't realize a bidirectionnal bus. SSTL2-II has twice the drive current of SSTL2-I. That lets you put terminating resistors at both ends of the bus which you want to do if you are driving in both directions. If your bus is short enough you can get away with only one terminator, but you better know what you are doing. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 46444
I think Micron 4Mx32 is DDR SGRAM because the other x4,x8 or x16 DDR RAM is using A10 for precharge and more than 1 DQS...maybe you can get the Micron X16 simulation model for simulation...I didn't try their code but I refer to the code and modify for my use...I made the FSM and address,command generation and refer to their DCM and DDR I/O...I think you can run 100MHz using V2 easily... Regards, ParryArticle: 46445
Dear All, Currently I have a design which is quite simple and am planning to implement it in a CPLD. However, the target operating speed is around 300MHz. After searching, I found that some CPLDs from Xilinx and Lattice are claimed to be able to operate at more than 300MHz. However, it seems that there is no PLL/DLL inside their CPLDs. So how can they operate at this high frequency? Does it mean that I need to input a 300MHz clock signal into CPLD directly? If so, i think it may cuase some problems in the PCB design, and i will change the design avoiding this to be happened. Please advise, thanks in advance. Regards, KennethArticle: 46446
>One Virtex-II BlockRAM can implement: >Any state machine with 256 states, each with a four-way branch controlled by two >inputs, and with 37 outputs, arbitrarily defined for each state. No hidden >constraints or problems. >Or: 128 states, each with 8-way branch controlled by 3 inputs, same output >flexibility. >Or 64 states, each with 16-way branch, controlled by 4 inputs, same output >flexibility. There is another layer of hackery you can do for wider branching. This works particularly well if you are thinking of the state machine as microcode/software which is convenient for hundreds of states. Suppose you have many conditions that you might want to branch on, but you only look at 1 or 2 in each state. Use some output bits to drive a mux and feed the output of the mux into the bottom bits of the next state register (aka address input to ROM). Suppose you have a 1K by N ROM. You can think of that as 256 instructions/states with 4 way branching. But that's normally wasting a lot of your microcode slots - all the ones where you don't want to branch. So rather than replace the bottom bit of the next-PC field, OR them in, and make one of the inputs to the MUX be 0 (no branch). Now all the slots that you didn't want to branch to can be used for normal instructions. This makes the assembler slightly more complicated. It has to assign addresses for instructions so that the branches work out right. But again that's not a problem after you have one to copy. > The concept is archaic, but the practicality is new. > "Old" does not necessarily mean bad, I hope. :-) It was practical ~20 years ago. How about "again" rather than "new"? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 46447
Hi, The virtex bus is not *really* tristate, but allready pulled up. You don't need to do it yourself. grtx, chris rutten ------ I am implementing a tristate bus in virtex. Should the bus be pulled up or can they be left as it is? -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 46448
Hello Govind,
The correct way to make the width of the index match the width required by
the array is to explicitly extract the required bitfield from the variable
'i', thus:
input_trig_256 ? trig_256[ i <- 9 ];
This will take the lower nine bits from the variable 'i' and use those for
the array index.
Best regards,
Neil Stainton
Applications Engineer
Celoxica Ltd.
http://www.celoxica.com
"Govind Kharbanda" <govind.kharbanda@sli-institute.ac.uk> wrote in message
news:2f5db38d.0208290806.4721d7c1@posting.google.com...
> Hi,
>
> I'm writing with a query on use of the Handel-C language, please let
> me know if there is a more appropriate forum in which to post.
>
> If you write code such as:
>
> /*
> * lookup tables
> */
>
> ram <signed int> trig_256[320] with {block = 1};
> ram <signed int> trig_2048[2560] with {block = 1};
>
> /*
> * read in trig array into block ram (block = 1)
> */
>
> chanin <signed int> input_trig_256 with { infile = "trig_256.dat" };
> chanin <signed int> input_trig_2048 with { infile = "trig_2048.dat"
> };
>
> unsigned int 13 i; // index for looping arrays
>
> i=0;
> do
> {
> par
> {
> i++;
> input_trig_256 ? trig_256[i];
> }
> } while (i!=320);
>
>
> i=0;
> do
> {
> par
> {
> i++;
> input_trig_2048 ? trig_2048[i];
> }
> } while (i!=2560);
>
> the compiler will complain that the index i does not agree with the
> size of the first array, trig_256, which only needs an unsigned 9 to
> access all its elements. How do I get round this 'properly'? The
> following two work arounds have been found to function but aren't
> ideal
>
> [1] declare a new index variable each time I need to loop an array of
> a different size - but code gets messy
> [2] do not declare size of RAM, but let Handel-C infer it i.e.
>
> ram <signed int> trig_256[] with {block = 1};
>
> - doesn't work with more complex code
>
> Gov
Article: 46449
I have the following setup:
One Nios processor (16 bit) with to areas of (internal) RAM.
Both areas are about 2kbyte of size, one loacted at 0x0000 and one
located at 0x1000.
I have an "operating system" placed in the first memory area. It
receives over an UART software (C-Code, compiled with 'nb -b 0x1000
mycode.c') and writes it in the memory locateted at 0x1000, which is
working fine.
After receiving the program-data, the program gets executed with
asm(" PFX %hi(0x800)
MOVI %g0,%lo(0x800)
CALL %g0
NOP
");
This works fine, too.The software is running and I can accsess the
7seg-Display on the Nios development board.
But when I try to have the program writing to memory with:
unsigned int * memptr;
memptr = (int *) 0x1200;
*memptr= 0xabcd; // if I remove this line, program works again
the processor crashes ( at least the program stops execution).
Has anyone an idea, what causes this crash?
I have the following ideas:
1.) The program compiled with 'nb -b0x1000 mycode.c' is built to be the
only executable on the nios. Maybe there are mess-ups with some of the
nios registers, caused by the operating system running before.
2.) I am using the wrong method to write to memory.
3.) It has something to do with the framepointer (I am not into
assembly, but I found a lot of "%fp" in the objdump of my code. I
didn't find useful explainations on framepointer in the documentation.
Thanks for reading!
Christian
--
due to my bursting mailbox there is a no-spam tag in my e-mail adress ;-)
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z