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Messages from 49175

Article: 49175
Subject: Re: Excessive heating on Xilinx XC9500XL
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 4 Nov 2002 16:38:22 +0100
Links: << >>  << T >>  << A >>
"Andreas Kugel" <kugel@ti.uni-mannheim.de> schrieb im Newsbeitrag
news:3DC656A3.3080005@ti.uni-mannheim.de...
> Hello.
> One of our XC95288XL exhibits ecessive heating (untouchable!). It
> contains a multiplexor to select an output clock from 3 different input
> clocks. Two of the input clocks are attached to a GCK pin while one is
> attached to an IO/GTS pin. When selecting the the non-GCK clock source
> the parts start to heat-up dramatically. Frequencies are in the range
> between 60 and 100MHz. The device contains 180 macrocells in high-perf
> mode. Only about 20 macrocells are affected by the input clock
> selection, the others are connected to a GCK clock.
>
> Any hints ?

Open inputs? Short cicuits?

--
MfG
Falk





Article: 49176
Subject: Re: pc to fpga cpu commands
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 4 Nov 2002 16:39:47 +0100
Links: << >>  << T >>  << A >>
"newb" <n/a@n/a.com> schrieb im Newsbeitrag news:ee7a255.-1@WebX.sUN8CHnE...
> Hello,
>
> I was wondering if anyone had any urls, notes, or just general information
on using an fpga with cpu core, such as risc, then connect to PC (usb, lpt
etc) and have an application send the fpga cpu commands such as "add 3, 5"
and the result will be returned to the PC (8).  Thanks, newb.

Have a look at xapp 213, it contains a plug&play RISC processor, 8 bit, very
nice. Xapp 223 has a plug&play RS232 UART.

--
MfG
Falk





Article: 49177
Subject: Re: Incremental design question
From: kayrock66@yahoo.com (Jay)
Date: 4 Nov 2002 08:12:08 -0800
Links: << >>  << T >>  << A >>
A lot of people seek the same answer as you and as of yet I have not
seen a satisfactory solution.  You can do a piece wise (bottom up)
synthesis with some complexity in Synplify but the P&R and usually the
long pole.  This may not be the answer you want to hear but these are
the times that you make sure your simulation environment is rock solid
so you don't end up getting into the "turn and burn" cycle on that
FPGA.  Every nite you get another chance to run your P&R so hoipefully
that should be enough.  Imagine you had an ASIC and it took 3 months
for each trial.

Regards

President, Quadrature Peripherals
Altera, Xilinx and Digital Design Consulting
email: kayrock66@yahoo.com
http://fpga.tripod.com
-----------------------------------------------------------------------------

"Peng Cong" <pc_dragon@sohu.com> wrote in message news:<aq5di8$me2$1@mail.cn99.com>...
> Hello, every one.
>     I'm working on a FPGA design project, it includes many module.
> It'll take so long a time to run full implement one time when I only
> make a little change in one module.
>     So I wonder how I can do incremental implement. I use Synplify Pro
> and ISE 5.1i.
>     I've read the Xilinx document on how to do Incremental designing, but
> not really understand, it seems that I need do it in Synplify Pro GUI mode.
> Is it impossible to do it in ISE? And where can I find any example code?
> 
> Thanks for any advence

Article: 49178
Subject: Re: FDRE inference in Synplify
From: "RobertS" <szumu@poczta.onet.pl>
Date: Mon, 4 Nov 2002 16:23:41 -0000
Links: << >>  << T >>  << A >>
I have had the same problem with FPGA Express and only using attributes for
'Reset' signal forced tool to stop implement sync_reset on 'D' path of FF
and to use dedicated  sync_reset.

> I'm trying to write some VHDL that will infer an FDRE (ff with clock
> enable and *sychronous* reset) in a Xilinx Virtex-E or -2 device.
>
> We've tried several versions of Synplify Pro 7.x, and they all waste a
> LUT to implement the synchronous reset function.




Article: 49179
Subject: Re: FPGA convert to ASIC
From: prashantj@usa.net (Prashant)
Date: 4 Nov 2002 08:43:53 -0800
Links: << >>  << T >>  << A >>
Jay,
That was very informative and I had a question for you. When you say
"a large FPGA design into a small ASIC and 4x speedup", are there any
constraints to it OR will all designs of FPGA result into such a
speedup and area reduction. I understand why the area reduction and
speedup occur. Its just the factor by which they occur that I'm not
sure about. What would you say for a design that uses 20,000 LEs in an
Altera Apex20K1500E device and about 40,000 bits of internal RAM
working @ 40 MHz ? Would such a design speed up 4 times when converted
to ASIC ? I understand that the speed up numbers would vary from
design to design. But there must be a minimum and maximum possible
numbers ? Interested in your comments.

Thanks,
Prashant



kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0211011522.4fd5cec2@posting.google.com>...
> I've done a few FPGA prototypes of designs that we knew in advance
> were going to be ASICs.  We used TSMC and IBM.  I never heard the
> price on the TSMC and I think IBM was charging something like $400k
> for chip #1.  However, expect foundries to be very agreeable these
> days on account of the surplus capacity.  The results went fine,
> because usually, by the time you've worked out all the bugs to get the
> FPGA to work in the lab, you've solved most of your problems. Also
> FPGA use sort of forces a certain level of simplicity with repect to
> clocking.   A BIG FPGA turns into a small ASIC because of the
> difference in area efficiency.  Also, expect about a 4X speed-up going
> to ASIC.  And of course, yes you can hand place, super pipeline,
> embedded multiplier, etc your FPGA to get a faster design, but I'm
> speaking in general for random logic writen by your average ASIC
> designer, not spending all the time to get so deep into the
> implimentation details.
> 
> President, Quadrature Peripherals
> Altera, Xilinx and Digital Design Consulting
> email: kayrock66@yahoo.com
> http://fpga.tripod.com
> -----------------------------------------------------------------------------
> 
> 
> 
> "alla" <alng23@hotmail.com> wrote in message news:<aps669$cdd$1@tilde.itg.ti.com>...
> > Just want see anyone here has any experience of converting a Xilinx FPGA
> > design into an ASIC implementation. If so, which vendor did you use? What's
> > the cost? Are you happy with the result? We are using the Virtex series and
> > considering this option. Thanks

Article: 49180
Subject: Re: C\C++ to VHDL Converter
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Mon, 4 Nov 2002 11:47:26 -0500
Links: << >>  << T >>  << A >>
Noel,

> We bang on about QoR, size, area performance...why don't we use
> schematic capture and layout, this will give us serious efficiency?
> Probably because multi-million gate designs, or even multi-hundred
> thousand gate designs would take an eternity to complete and the
> product would be defunct before it got anywhere near the market.

That's simply not true.  The Alpha CPUs were designed using schematic
capture, as well as many other multi-million gate designs.  It IS entirely
possible to design multi-million gate designs with schematics equally as
fast and obviously far more efficiently with schematics.  IF you know how to
use schematics.  You don't draw things by the gate, you use a library of
heriarchical symbols, and it's basically drag and drop.

Austin



Article: 49181
Subject: Re: Excessive heating on Xilinx XC9500XL
From: kayrock66@yahoo.com (Jay)
Date: 4 Nov 2002 09:31:51 -0800
Links: << >>  << T >>  << A >>
That GTS signal is a high capacitance net because its routed to every
single I/O cell regardless of whether or not its used.  You probably
should pick another I/O.  Also, why operate in high perf mode if the
design is only 100MHz or less?  I'm assuming that you know that the
static power dissipation doubles for each macrocell you select for
that mode.

Regards
President, Quadrature Peripherals
Altera, Xilinx and Digital Design Consulting
email: kayrock66@yahoo.com
http://fpga.tripod.com
-----------------------------------------------------------------------------

Andreas Kugel <kugel@ti.uni-mannheim.de> wrote in message news:<3DC656A3.3080005@ti.uni-mannheim.de>...
> Hello.
> One of our XC95288XL exhibits ecessive heating (untouchable!). It 
> contains a multiplexor to select an output clock from 3 different input 
> clocks. Two of the input clocks are attached to a GCK pin while one is 
> attached to an IO/GTS pin. When selecting the the non-GCK clock source 
> the parts start to heat-up dramatically. Frequencies are in the range 
> between 60 and 100MHz. The device contains 180 macrocells in high-perf 
> mode. Only about 20 macrocells are affected by the input clock 
> selection, the others are connected to a GCK clock.
> 
> Any hints ?
> 
> Thanks,
> Andreas
> 
> P.S. One idea is that the IO/GTS input drives the GTS net with the clock 
> even if the GTS signal is not used ???

Article: 49182
Subject: Re: Leonardo 2002d and virtex2_multipliers
From: Shareef Jalloq <sjalloq@arm_removeMe_.com>
Date: Mon, 04 Nov 2002 17:34:29 +0000
Links: << >>  << T >>  << A >>
Tomas Lopez wrote:

> Has anyone had a problem with the latest Leonardo version (2002d) and the "virtex2_multipliers" variable? Even though I set it to FALSE, Leonardo insists on using one of the embedded multipliers.

I haven't had a problem directly related to your question but Leonardo on the whole is horribly buggy.  We've had to try different versions just to try and minimise the number of synthesis bugs we've
been finding and we currently have 1 or 2 that we have to manually edit after synthesis!  Move to Synplify if you can.

Shareef.




Article: 49183
Subject: Re: Excessive heating on Xilinx XC9500XL
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 04 Nov 2002 09:56:44 -0800
Links: << >>  << T >>  << A >>
Andreas,
I would radically reduce the clock frequency ( down by at least a factor
ten), and then check the temperature.

If ( and I do not believe it) it's dynamic power, the temperature should be
much lower. If, as I suspect, it's internal or external contention, the
power stays the same...

Peter Alfke
===========================
Andreas Kugel wrote:

> Hello.
> One of our XC95288XL exhibits ecessive heating (untouchable!). It
> contains a multiplexor to select an output clock from 3 different input
> clocks. Two of the input clocks are attached to a GCK pin while one is
> attached to an IO/GTS pin. When selecting the the non-GCK clock source
> the parts start to heat-up dramatically. Frequencies are in the range
> between 60 and 100MHz. The device contains 180 macrocells in high-perf
> mode. Only about 20 macrocells are affected by the input clock
> selection, the others are connected to a GCK clock.
>
> Any hints ?
>
> Thanks,
> Andreas
>
> P.S. One idea is that the IO/GTS input drives the GTS net with the clock
> even if the GTS signal is not used ???


Article: 49184
Subject: Re: Excessive heating on Xilinx XC9500XL
From: David Hawke <dhawke@xilinx.com>
Date: Mon, 04 Nov 2002 18:01:07 +0000
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------98F33DBA5A2ABD0EB25F5EC3
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Andreas,

It seems strange that it only heats up when you have the GTS input selected.
How is the mux implemented - are you sure that the Synthesis tool hasn't
implemented the mux as tristates?

If you are seeing this - I think you may be causing contention.

Dave

Andreas Kugel wrote:

> Hello.
> One of our XC95288XL exhibits ecessive heating (untouchable!). It
> contains a multiplexor to select an output clock from 3 different input
> clocks. Two of the input clocks are attached to a GCK pin while one is
> attached to an IO/GTS pin. When selecting the the non-GCK clock source
> the parts start to heat-up dramatically. Frequencies are in the range
> between 60 and 100MHz. The device contains 180 macrocells in high-perf
> mode. Only about 20 macrocells are affected by the input clock
> selection, the others are connected to a GCK clock.
>
> Any hints ?
>
> Thanks,
> Andreas
>
> P.S. One idea is that the IO/GTS input drives the GTS net with the clock
> even if the GTS signal is not used ???



Article: 49185
Subject: Re: read and write same address of the ESB memory in the same cycle
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 04 Nov 2002 10:02:57 -0800
Links: << >>  << T >>  << A >>
ssy wrote:


> I use APEX20k400E, and I use the lpm_ram_dp in quartus II to construct
> my register file, all input signal is registered , so read and write
> are all sync
> 
> so if I read and write the same address of this memory at the same
> clock edge, can I get the just writen value?


You get an unspecified value.
You have to add logic to arbitrate this.
For a FIFO, this is the "empty" state.
You can't pop more than you push.

   -- Mike Treseler


Article: 49186
Subject: Re: Incremental design question
From: guardfield@hotmail.com (g. Field)
Date: 4 Nov 2002 10:05:53 -0800
Links: << >>  << T >>  << A >>
"Peng Cong" <pc_dragon@sohu.com> wrote in message news:<aq5di8$me2$1@mail.cn99.com>...
> Hello, every one.
>     I'm working on a FPGA design project, it includes many module.
> It'll take so long a time to run full implement one time when I only
> make a little change in one module.
>     So I wonder how I can do incremental implement. I use Synplify Pro
> and ISE 5.1i.
>     I've read the Xilinx document on how to do Incremental designing, but
> not really understand, it seems that I need do it in Synplify Pro GUI mode.
> Is it impossible to do it in ISE? And where can I find any example code?
> 
> Thanks for any advence

I think synplify 7.2 has a feature for what you want.
It's called Multipoint synthesis.
http://www.synplicity.com/literature/pdf/synpro_multi_xilinx.pdf
There is a tutorial in this apps note.

Article: 49187
Subject: tips for cutting down on slice usage in a VirtexII
From: amyks@sgi.com (Amy Mitby)
Date: 4 Nov 2002 10:56:55 -0800
Links: << >>  << T >>  << A >>
My design is using too many slices for the device
I am targetting (XCV2000), although my LUT and slice
flip flop count is under 100%. Any suggestions for logic
and / or slice reduction?

Number of slices: 5,246 out of 5,120
Number of slice flip flops: 6,175 out of 10,240   60%
Number of 4 input LUTs: 8,516 out of 10,240   83%

Article: 49188
Subject: Re: tips for cutting down on slice usage in a VirtexII
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Mon, 4 Nov 2002 14:19:07 -0500
Links: << >>  << T >>  << A >>
Amy,

What is your design entry tool?

Austin

"Amy Mitby" <amyks@sgi.com> wrote in message
news:2d2a8f5d.0211041056.edc3a80@posting.google.com...
> My design is using too many slices for the device
> I am targetting (XCV2000), although my LUT and slice
> flip flop count is under 100%. Any suggestions for logic
> and / or slice reduction?
>
> Number of slices: 5,246 out of 5,120
> Number of slice flip flops: 6,175 out of 10,240   60%
> Number of 4 input LUTs: 8,516 out of 10,240   83%



Article: 49189
Subject: Re: C\C++ to HDL Converter, why not HDL -> C instead
From: johnjakson@yahoo.com (john jakson)
Date: 4 Nov 2002 12:19:36 -0800
Links: << >>  << T >>  << A >>
One of the most cited reasons for using C is the claimed simulation
speed, write in C & the simulations is bound to be vastly faster than
the same behavioural code in Verilog/VHDL. Somthing like an FFT in C
(classic rad 2) will run orders faster than same in behavioral HDL.

I was of the same opinion too, but eventually the C model still had to
be rewritten in Verilog to synthesize it. I specifically used an RTL C
style of coding in instances so the Verilog RTL was almost a 1 to 1
map. Problem was the C code looked bloody ugly, hierarchy was very
difficult to manage, & was manually levelised and ended up being a
very poor mans Verilog. Worse still, all the revisions were done to
the Verilog & not all the way back to the C as it was often quite
difficult to express in poor mans C what is easy in HDL. At the end of
the road I even had the C env auto magically spit out the
corresponding Verilog using lots of ugly macros that did both
simulation & equiv HDL code output. This was maybe ok in the gate
level world, lots of companies did this too!

I got real tired of doing that flow. The cleverer the tool got to be
more like Verilog, the slower the sims became. In the end I junked it
& wrote a direct RTL subset of Verilog to C compiler. NOW I can model
in RTL Verilog AND I have the speed of C in simulation. There is a
penalty, the backend doesn't optimize as well as it could, but it is
only a few times slower than raw C. Expect to fix that one day, gee
might even add x86 raw output since passing the C code to VC6 tends to
really burden it (100k lines in a fn() will kill most C compilers). I
call it Vpp (like the old Cpp from Bell Labs) or sometimes V2C. One
day might put it out under open source (BSD/MIT) if there is enough
interest.

Other than that, I have to agree with Ray & others, there is some room
for HandelC, Occam, StreamsC, CSP etc for Reconfigurable Computing
with a FPGA board to speed up a PC, but to create an actual ASIC or
FPGA product, I am much more skeptical? I would expect to see a
performance penalty of at least a decade or so but the more the C app
looks like a DSP flow, the better the result will close in to hand
RTL. I have seen the Celoxica demos & I was quite impressed with the
Venus de Milo show at the Xilinx VirtexPro fair last spring.

Now I would like to draw your attention to CSP or Occam. 40 yrs ago
Tony Hoare was a real live EE & did design work in RTL (Resister
Transister Logic hehehe). he later moved into SW (at Oxford U) & later
became world famous for his work in Par programming.

In v1 of his work, I believe (& so does he now) that he & others got
it all wrong, hence this is why the SW world has such a hard time with
Par programming since most SW people work with spinlocks, P & V,
deadlocks, mutexes, semaphores etc. These have nothing to do with HW
abstraction so they don't help make that Par code any use to HW
design. It is also why Java & even C# with threads are Thread unsafe &
why that kind of Par programming is extremely hard when HW guys find
Par so easy but Seq much harder.

In v2 of his work only a few years later (1968 IIRC), he must have
sobered up & remembered he was once a HW guy. CSP & esp Occam is a HDL
(or PDL) using processes & messages to describe logic. Channels in
Occam are essentially equiv to wires connecting the outputs of one
process to the inputs of another. Now the Transputer executed Occam
programs in a similar way to how a HDL simulator works. It included a
round robin scheduler to effect the par execution of all the par
expressions, & shuffling the outputs back to inputs (eventually). At
Inmos, Occam was even used to write a simulator & to describe the T800
FPU.

So I though I might also mention I am working on a modern Transputer
called T2 for FPGA using Vpp etc and lots of work still to do. Perhaps
next yr more news. Now with a Transputer in FPGA, you really could
could array them in the bigger FPGAs and benefit from the near linear
increase in performance since using lots of Transputers was alot like
partitioning a big HW block into smaller blocks with the interconnect
timeshared over the channels/links.

I have now come to the conclusion that Transputing is the soft side of
RC & FPGAs are the hard side, both complimentary and somewhat
interchangeable. Now if you put a Transputer or 2 (or more) in FPGA,
it is not only the ideal embedded cpu, but it makes it easy to divy up
the project into HW (FPGA) & SW (T/Occam/.. code).

my 2c

Article: 49190
Subject: Re: 16-bit FGPA CPU core (commercial)
From: brimdavis@aol.com (Brian Davis)
Date: 4 Nov 2002 12:29:43 -0800
Links: << >>  << T >>  << A >>
Jan wrote:
> 
> If there *are* other 16-bit C-programmable soft processor cores
> under (say) 400 LUTs out there, please let us know.
> 

 When last compiled to an XC4005E a couple of years back, my
homebrew 16/32 bit RISC weighed in at 335 LUTs in 16 bit
datapath mode, including onboard RAM/ROM/IO ports:

  http://groups.yahoo.com/group/fpga-cpu/message/118

 The 16 bit datapath hasn't been tested very much lately, as
XST has many bugs handling constant range checking inside
conditional generates, and won't compile the VHDL source
in 16 bit mode without manual edits.

 An alpha version under LGPL should be ready by year's end
(as unsupported free code with no warranty, support, etc.)

Brian

Article: 49191
Subject: Re: C\C++ to HDL Converter, why not HDL -> C instead
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 05 Nov 2002 09:48:31 +1300
Links: << >>  << T >>  << A >>
john jakson wrote:
> 
<snip good stuff >
> I have now come to the conclusion that Transputing is the soft side of
> RC & FPGAs are the hard side, both complimentary and somewhat
> interchangeable. Now if you put a Transputer or 2 (or more) in FPGA,
> it is not only the ideal embedded cpu, but it makes it easy to divy up
> the project into HW (FPGA) & SW (T/Occam/.. code).
> 
> my 2c

Interesting post.

What's the status of Transputer tools ? 

Don't STm still have some flavour of the Transputer targeting 
the set-top-box market ?

- jg

Article: 49192
Subject: new to fpga, what language is better to start with
From: "Klemen" <nec4b@email.si>
Date: Mon, 4 Nov 2002 21:51:07 +0100
Links: << >>  << T >>  << A >>
Hi!

I'm new to FPGAs and i don't know in which language should i begin to
design( vhdl, verilog, c). I currently have Webpack 4.1.

regards



Article: 49193
Subject: Re: Incremental design question
From: vishker@yahoo.com (Vishker)
Date: 4 Nov 2002 13:16:22 -0800
Links: << >>  << T >>  << A >>
I think Synplify has come up with something called multi-point
synthesis. They say its used for incremental synthesis. Try searching
their docs.



"Peng Cong" <pc_dragon@sohu.com> wrote in message news:<aq5di8$me2$1@mail.cn99.com>...
> Hello, every one.
>     I'm working on a FPGA design project, it includes many module.
> It'll take so long a time to run full implement one time when I only
> make a little change in one module.
>     So I wonder how I can do incremental implement. I use Synplify Pro
> and ISE 5.1i.
>     I've read the Xilinx document on how to do Incremental designing, but
> not really understand, it seems that I need do it in Synplify Pro GUI mode.
> Is it impossible to do it in ISE? And where can I find any example code?
> 
> Thanks for any advence

Article: 49194
Subject: Re: Incremental design question
From: brian@hierdesign.com (Brian Jackson)
Date: 4 Nov 2002 13:54:32 -0800
Links: << >>  << T >>  << A >>
Hello Peng,

This is a common complaint for people doing large FPGA designs. I work
for a new EDA company called Hierarchical Design Inc. We are coming to
market with an FPGA floorplanner to solve this specific issue as well
as a host of others. I'd be happy to share some more details about our
product with you. Feel free to contact me at anytime.

Regards,

Brian Jackson
Vice President, Business Development
Hierarchical Design Inc.
www.hierdesign.com
408-982-8277


"Peng Cong" <pc_dragon@sohu.com> wrote in message news:<aq5di8$me2$1@mail.cn99.com>...
> Hello, every one.
>     I'm working on a FPGA design project, it includes many module.
> It'll take so long a time to run full implement one time when I only
> make a little change in one module.
>     So I wonder how I can do incremental implement. I use Synplify Pro
> and ISE 5.1i.
>     I've read the Xilinx document on how to do Incremental designing, but
> not really understand, it seems that I need do it in Synplify Pro GUI mode.
> Is it impossible to do it in ISE? And where can I find any example code?
> 
> Thanks for any advence

Article: 49195
Subject: Re: tips for cutting down on slice usage in a VirtexII
From: Tim Jaynes <Tim.Jaynes@xilinx.com>
Date: Mon, 04 Nov 2002 14:51:55 -0800
Links: << >>  << T >>  << A >>
Amy,
Just wanted to make sure you're aware that you can change the pack
factor in map to allow the merging of unrelated logic into your slices.
It's design dependent and can hurt timing, but I'd guess that you could
probably use it to slim your slice utilization down below 100%.  For
information check out the DSR Guide at:
http://support.xilinx.com/support/sw_manuals/xilinx5/index.htm
and reference the section on MAP.
Regards,
Tim Jaynes
AAE



Amy Mitby wrote:

> My design is using too many slices for the device
> I am targetting (XCV2000), although my LUT and slice
> flip flop count is under 100%. Any suggestions for logic
> and / or slice reduction?
>
> Number of slices: 5,246 out of 5,120
> Number of slice flip flops: 6,175 out of 10,240   60%
> Number of 4 input LUTs: 8,516 out of 10,240   83%


Article: 49196
Subject: WANTED: Technology partner to help verify new FPGA floorplanner
From: brian@hierdesign.com (Brian Jackson)
Date: 4 Nov 2002 15:19:00 -0800
Links: << >>  << T >>  << A >>
My name is Brian Jackson and I am the business development manager for
Hierarchical Design Inc. We are an EDA company bringing the next
generation heirarchical physical floorplanner to market for Xilinx
VirtexII devices. Our product allows you to easily partition and
floorplan your FPGA design. It allows incremental updates from
synthesis and will perform block based PAR using Xilinx ISE tools. The
results can then be assembled and modified inside of the floorplanner.
There are quite a few more features that I won't bother to get into
here.

We are currently looking to sign up a small FPGA design consultant as
a technology development partner to beat on it within a "real" design
environment. This way we can work out any kinks before making a big
splash in the market. Preferrably, this would be someone in the
Silicon Valley area. We would compensate with either licenses or with
a prearranged consulting fee. If you are interested and do complex
FPGA designs in VirtexII, please don't hestitate to contact me.

Regards,
Brian Jackson
Vice President, Business Development
Hierarchical Design Inc.
www.hierdesign.com
brian@hierdesign.com 
408-982-8277

Article: 49197
Subject: Re: 2-nios design using SOPC builder
From: kempaj@yahoo.com (Jesse Kempa)
Date: 4 Nov 2002 15:34:46 -0800
Links: << >>  << T >>  << A >>
Hi,

I've done several experimental designs with multiple CPUs without any
problems.

One hint, though, in case you use custom instructions: each custom
instruction is defined and synthesized as its own design entity
(whether that is .v, .vhd, .edf, etc). If you have two CPUs and each
has a custom instruction, there can be some tool confusion if both
CPUs use a custom instruction of the same name (as all SOPC Builder
HDL code is generated in a common project directory). You can easily
safeguard this by ensuring each processor's custom instructions (if
any) have unique names inside the SOPC Builder GUI.

Have fun with this - I'd be happy to hear about the progress of your
project!

Regards,

Jesse Kempa


satchit_h@hotmail.com (satchit) wrote in message news:<ddf018f6.0210300811.32d31548@posting.google.com>...
> Hi,
> 
> has anybody tried a 2-nios parallel design using SOPC builder? I am
> trying to build one which can run separate pieces of code
> concurrently. Any comments would be helpful. thanks,
> 
> regards,
> Satchit

Article: 49198
Subject: Re: Excessive heating on Xilinx XC9500XL
From: "Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it>
Date: Mon, 04 Nov 2002 23:36:17 GMT
Links: << >>  << T >>  << A >>
"Andreas Kugel" <kugel@ti.uni-mannheim.de> ha scritto nel messaggio
news:3DC656A3.3080005@ti.uni-mannheim.de...

> One of our XC95288XL exhibits ecessive heating
> (untouchable!).

What do you mean with "untouchable"? It could be 50-60 C, which is
completely safe.

--
Lorenzo



Article: 49199
Subject: VME Master Design
From: "Scott Munroe" <smunroe@phillipsaerospace.com>
Date: Mon, 4 Nov 2002 15:53:52 -0800
Links: << >>  << T >>  << A >>
Does anyone know of an available VME Master core or reference design?

Scott Munroe

smunroe@phillipsaerospace.com





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