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Uwe, Yes, every Vref pin shall have its own bypass. Unfortunately, if every IO pin can be any standard, we can not take advantage of what ASICs and ASSPs do, and provide a bypass capacitor internally on a dedicated Vref pin. So we have to require a bypassing arrangement to keep noise off of the Vref pins. Additionally, be careful about having any switching traces run near the Vref traces, as that will couple cross talk into the pcb traces, and make the Vref noisy (a problem for any chip, not just the FPGA). Austin Uwe Bonnes wrote: > Hallo, > > to implement a GTL+ interface with a Spartan II, I need four banks where I > will use the VREF pins. With th PQ208 packages, this boils down to 16 pins > that need to get connected to the GTL+ reference voltage. > > What are the decoupling requirements for these Pins. Should every VREF pin > have it's own decoupling capacitor, may I group close VREF pins and use one > capacitor ofr that group or is the VREF decoupling on the VREF pin > uncritical? There will be no other consumer of the GTL VREF voltage on my > board. > > Thanks > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 49226
Bernhard, LVDS in Virtex II and Virtex II Pro is current sourced, and is inherently safe for a short circuit to each other, to ground, or to Vcco. In fact, given the size of our IOB transistors to meet all of the standards, any IO standard is safe for any short circuit condition for quite awhile (we have seen them go for months without a failure being shorted). Momentary connector shorts are just fine. I would not recommend shorting an output forever. Austin Bernhard Mäder wrote: > Hi people > > I'm working on a thesis project for which we'd like to use the > Virtex-II I/Os to connect to an external device via LVDS signals. The > question is: how safe are they concerning short circuits and the like? > Can I just route them to my connector? I can't risk to damage the > FPGA... > > An option would be to use a dedicated LVDS chip (National Semi). > > Thanks for any suggestions > Bernhard MäderArticle: 49227
I've generally found floorplanning to be more effective in solving timing problems. But first you need to identify the problem. Your tool should tell you which path(s) are failling. If it is an I/O, rahter than fool with timing, make sure there is a register in the I/O cell, if you can. For internal long paths, apply a constraint to that specific path or group of paths. Or you may see that some floor planning would get what you want more directly. You mentioned a derived clock. Multiple clocks are almost always a pain. I would look very carefully at how that clock is derived and distributed. Make sure it is using only clock routing resources, not general routing resources. Look very carefully at signals that go between the clock domains. Maybe you can get rid of it by using an enable signal instead.Article: 49228
Jan, I just downloaded and installed the service pack. I was able to obtain the proper download size of 46 Mb. The installation ran through to completion as well. I would suggest trying again due to some potential web problems that may have been resolved over night. I have not heard of any known problems at this time, but I may get some information later on. Another option is to download the WebInstall routine and try this. This will download a much smaller fileset. Regards, Larry Jan Pech wrote: > I can't install the Service Pack 2 for my WebPACK. When I run the file > "5_1_02i_pc.exe", it just tells me that file cannot be unpacked and that > executable has been corrupted. I tried to download this file many times but > the result was every time the same:( > Is the file at Xilinx' web site really corrupted or is the problem somewhere > else? > Does anyone succeeded in installing SP2? > By the way, is it finally possible to use iMPACT with parallel cable as a > normal user under W2k after installing SP2? > > Thanks, > JanArticle: 49229
> > > elaborate testbenches. HDL can be treated like a programming language > > > for simulation only stuff. > > > > Why is this precluded for schematics? > > Schematics require you to come up with a circuit for the test bench. If the > testbench is done as a programming language you have considerably more > flexibility. When I was doing schematics, we often did testbenches in VHDL, but > it required additional tools to do it, and was at times awkward. I don't understand. What tools are you talking about? I simply run my testbench, written in HDL, same as I would for any design even if the design is in HDL, and get the same output waveforms...or better yet, it displays the actual signals on the schematics. > > And of course the MAJOR benefit of schematics (or netlisting using HDLs), is > > you KNOW what the tools are going to give you for output, and you don't have > > to fight with them NEAR as much to make things fit, and make timing. > > I do this for critical and placed stuff in HDLs using a library of generated > instances. As you know, I had fine tuned my schematic entry to be able to turn > around designs quickly using a rather extensive library. The same common > components written with generate statements encapsulating primitives works fine > in VHDL and gives the same degree of control as I had with schematics. What about placement? Problems I've had were the tools didn't allow the use of consistent names, either when a change was made with to either the design, or the toolset. > The big > win with VHDL is I have written those components so that they are parameterized > to generate exactly what is needed for each instance from a single library > design. And what preculdes you from doing that with schematics? Did you ever see Philip's tool for generating schematic elements? > The advantage is if I make a change to the macro, it only gets changed > in one place, which is not necessarily true with schematics (using 2 bit slices > for arithmetic, it is almost true, but you still have the special cases at the > start and end of a carry chain). The parameterization includes options for > layout, assignment to different device families (RLOC format for example), > automatic signed/unsigned extension, automatic selection of reset vector values > with the proper FDRE/FDSE etc. These are things that were a little awkward with > schematics, and are very easy to do with the HDL generates. Hum, I don't find them awkward at all with schematics, but do with HDLs... > > The ideal methodology, IMO, is mixed schematic (for data path) and HDL for > > control logic...but I've seen some very good schematic state machine designs > > (and libraries can be used here as well) that no HDL could come close to. > > Yes, you've probably seen my schematic flow chart state machines too. They are > very readable compared with HDL, and just as easy to edit. Sorry, haven't seen them. > The main reason for going to HDL, however (at least in my mind) is to maintain a > more or less mainstream tools flow, which seems to be pretty important to my > customers. Mainstream? Not really. Synplify may be the "tool de Jour", but I don't see that as being any better than schematics, though you are locked to a single vendor with schematics, no doubt. Also, as you know, every damn revision of these HDL compilers generates different code...which reeks havoc on some designs. > Schematic entry is considered by most to be an archaic design entry > method (not that I agree, but the fact is that is the prevailing attitude). It is the prevailing attitude amongst "young" people who know no better, yes. Unfortunately, this abysmal "ignorance" has prevailed with respect to programming...not that I'm advocating assembly programming, as current C compilers are far far far better than current HDL compilers. > By > moving to HDLs a few years ago, I kept from locking myself out of many > customers. I agree. Designs I do for my own projects, I do in schematics...simply because it keeps the parts cost down, ups the speed significantly...and I don't have to wrestle with the tools. I do mostly HDL work for clients now, as for misbegotten reasons, they believe it saves them time and money...when in every instance, it absolutely, unquestionably does not. > So will I be seeing you in San Jose tomorrow? If so, we can discuss this in > person. No, sigh...I am unable to make it, but I was assured by Philip that you would defend the fort better than either of us would ;-) Regards, AustinArticle: 49230
Phil Hays wrote: > Austin Franklin wrote: >>That's simply not true. The Alpha CPUs were designed using schematic capture > ... by a large building full of designers. Who no longer work for Digital Equipment Corp. -- Mike TreselerArticle: 49231
Peter Wallace <pcw@karpy.com> wrote: : On Tue, 05 Nov 2002 05:35:54 -0800, Petter Gustad wrote: :> "Jan Pech" <j.pech@noSPAMieee.org> writes: :> :>> I can't install the Service Pack 2 for my WebPACK. When I run the file :> :> Does anybody know if 5.1 is shipped to all Xilinx customers by now? I :> haven't received mine yet... :> :> Petter : : I got mine a couple of weeks ago. It sits idle on my desk since I am : still running NT4 sp6a and have vowed to let no more Redmond Devils Spawn : thru our portals... I run webpack through wine on linux... However impact dosen't work for principal reasons. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 49232
> What is your design entry tool? My flow is Verilog --> Synplify Pro --> Xilinx ISE 4.2.03i (ISE 5.0 doesn't yet work with the PCI core for me, so I can't update yet)Article: 49233
Hello, Could someone please explain more the VersaRing utility? i know it is the routing ressources which allow connecting the IOBs to CLBs is it so performant and quick such that i don't have to bother myself too much about the design padding thanksArticle: 49234
There is a 4.2i ISE for Linux Redhat. Is programming supported there? How is it done? Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 49235
Austin Lesea <austin.lesea@xilinx.com> wrote: : Uwe, : Yes, every Vref pin shall have its own bypass. Unfortunately, if every IO : pin : can be any standard, we can not take advantage of what ASICs and ASSPs do, : and : provide a bypass capacitor internally on a dedicated Vref pin. : So we have to require a bypassing arrangement to keep noise off of the Vref : pins. Additionally, be careful about having any switching traces run near : the : Vref traces, as that will couple cross talk into the pcb traces, and make the : Vref noisy (a problem for any chip, not just the FPGA). Thanks for the response. Is there any substantial currents flowing into or out of the VREF pins? I would guess not. So then there would be no need for a high capacitance decoupling capacitor associated to each pin. In my design I probably can make the whole top layer inside the area defined by the pins a VREF plane. Layer 2 is a ground layer, and the vref plane would get on 100nF decoupling cap on bottom. In my understanding this should make a low noise VREF supply, as long as no substantial currents flow i/out of the VREF pins. Or do I miss something? Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 49236
"Peter Alfke" <peter@xilinx.com> ha scritto nel messaggio
news:3DC71B5C.2FB03CBC@xilinx.com...
> "untouchable" seems to mean "too hot to touch". That
> occurs at a
> temperature significantly above 60 degrees C.
Personally I couldn't touch them neither at 60 C. :-)
> At 25 degree ambient, this means about 40 to 45 degrees
> over-temperature.
After some (very rough) extimations, I think that even in industrial
temperature range this could lead to a junction temperature of 130-135
C, which is above the absolute maximum rating (150 C).
> Look that up in the thermal impedance
> table...
Junction-case thermical resistance is often negligible if compared to
case-free air Rth; 95288XL is packaged in five ways:
Rja Rjc
TQ144 57.6 5.5
PQ208 36.9 4.8
BG256 38.8 3.9
FG256 33.6 3.9
CS280 30.5 0.8
If you have a temperature between case and ambient of 45 degrees, in the
worst case you could have 48, 52 C between junction and ambient.
(I would add "maybe", because Murphy is always there... :))
--
Lorenzo
Article: 49237Uwe, There is no current on a vref pin, other than the leakage present for any IO pin. You have not missed anything. If the cross talk coupling is ~10 pF for a pin, then 1000pF (1nF) should reduce this by 100:1. The 10 pF number is just a guess from the pcb trace geometries that might be present. Could be less, could be more. Austin Uwe Bonnes wrote: > Austin Lesea <austin.lesea@xilinx.com> wrote: > : Uwe, > > : Yes, every Vref pin shall have its own bypass. Unfortunately, if every IO > : pin > : can be any standard, we can not take advantage of what ASICs and ASSPs do, > : and > : provide a bypass capacitor internally on a dedicated Vref pin. > > : So we have to require a bypassing arrangement to keep noise off of the Vref > : pins. Additionally, be careful about having any switching traces run near > : the > : Vref traces, as that will couple cross talk into the pcb traces, and make the > : Vref noisy (a problem for any chip, not just the FPGA). > > Thanks for the response. > > Is there any substantial currents flowing into or out of the VREF pins? I > would guess not. So then there would be no need for a high capacitance > decoupling capacitor associated to each pin. > > In my design I probably can make the whole top layer inside the area defined by > the pins a VREF plane. Layer 2 is a ground layer, and the vref plane would > get on 100nF decoupling cap on bottom. In my understanding this should make > a low noise VREF supply, as long as no substantial currents flow i/out of > the VREF pins. Or do I miss something? > > Thanks > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 49238
Anybody else have problems with speed of this program in 5.1i? We are seeing 5+ second delays to type a value in when the waveforms get large (~200 clock cycles, 30 ports). Used to work ok with 4.2. We opened a support case but so far Xilinx can't reproduce it so though I'd check here to see if we really are only one seeing this problem. We are using XP.Article: 49239
Klemen wrote: > Hi! > > I'm new to FPGAs and i don't know in which language should i begin to > design( vhdl, verilog, c). I currently have Webpack 4.1. Schematics. -- rk, Just an OldEngineer "A good engineer gets stale very fast if he doesn't keep his hands dirty." -- Wernher von Braun, 1964Article: 49240
Some of you know we do a "Stamp Project of the Month" every month on our Web site. This month we are trying a "PLD project of the month" that will usually change on the 15th of the month (plus or minus a few days). This month, we are early, so the next update will be roughly December 15th. Have a look and let me know what you think: http://www.al-williams.com/pom.htm Al Williams AWCArticle: 49241
ich habe ein fir filter mit dem xilinx corgen gerneriert. jetzt meine frage welches signal braucht der filer auf dem ND-pin ? ist das clk signal des filters auch meine abtastfrequenz ? liest der filter die digitalen daten parallel ein und gibt sie parallel wieder aus ? bye JohannesArticle: 49242
Rick Filipkiewicz wrote: > I read on this NG that from 5.x onwards Win-NT is no longer `supported' > by Xilinx. Since I'm loathe to change O/S for no very good reason and > AFAIC, Win-NT 4.0 SP6A is as close to bomb-proof as any 'doze O/S has > ever got I'd like to at least try installing 5.1 under NT. > > Has anyone tried this successfully ? Win2k is as bomb-proof as anything, and does all the usb and plug/pray stuff.Article: 49243
"faidon" <fdn23@yahoo.com> wrote news:ee7a1ab.3@WebX.sUN8CHnE... > hello again > > Peter you are right, for some reason i expanded the address without being necessary.I must keep it the same. > Finally i got it working, but i had to remove the bit 9 of address of S8_S8 in the declaration and in the process that calculates the new address, because S16_S16 uses 8 bit width.(Otherwise i got wrong data). > hello, if you want to use the LFSR counters for 8 bit addresses, you should use bits 7,5,4 and 3 in the linear feedback function: read_linearfeedback <= NOT (read_addr(7) XOR read_addr(5) XOR read_addr(4) XOR read_addr(3)); and the same for the write counter. If you have to design new sync. fifos in future take a look at the xapp052 http://www.xilinx.com/xapp/xapp052.pdf There is a table for the linear feedback function for 3 - 168 bit LFSRs (*note: the bits are counted from 1 to n and not from 0 to n-1 there). Such a LFSR uses only 1 LUT + addr_width*FFs. Erich Krause.Article: 49244
Hi all impact works fine when I use it as administrator but brings up an error message when I try to use it as an simple user. does anybody know how I can use impact as user not as administrator? thanx ThomasArticle: 49245
Hi, I have worked with XST and the Quartus synthesis tool with decent results; but I'd like to upgrade to a more powerful third-party tool, for million-gate designs. Can you quickly share your experience and your opinion of cost vs performance for: - FPGA Express - Synplify - Synopsis - LeonardoSpectrum Thanks, -- Tullio Grassi ====================================== Univ. of Maryland - Dept. of Physics College Park, MD 20742 - US Tel +1 301 405 5970 Fax +1 301 699 9195 ======================================Article: 49246
Kiran, I have spent many hours on the phone with Xilinx support with this same question. Xilinx doesn't support this feature. If there are power or ground (logic level 1 or logic level 0) connections in your design, then this is probably the source of the error. The tool has a problem with power and ground connections. kputtego@vt.edu (Kiran Puttegowda) wrote in message news:<72480649.0210271033.535836f4@posting.google.com>... > I created a macro following the directions given in Xilinx Answer > Record number: 10901. It has a single Virtex-2 slice. I was trying to > instantiate this macro into the top level design. When ngdbuild tries > to load the macro from the file I get an error > (FATAL_ERROR:Ncd:basncmacrodef.c:1466:1.19.2.1 - Mangled nmc file > start property read <0xffffcacc>). > Can anyone let me know why this error occurs. > Thanks > -KiranArticle: 49247
2comander2@gmx.de (Johannes) wrote in message news:<966f8080.0211060259.22a3b095@posting.google.com>... > ich habe ein fir filter mit dem xilinx corgen gerneriert. jetzt meine > frage welches signal braucht der filer auf dem ND-pin ? ist das clk > signal des filters auch meine abtastfrequenz ? liest der filter die > digitalen daten parallel ein und gibt sie parallel wieder aus ? > > bye Johannes Perhaps you might get more help trying in English: "I generated a FIR filter using Xilinx Coregen. Now I'm trying to determine how to drive the ND pin of the filter. Is the clock signal of the FIR filter also my sample rate ? Does the filter read the digital data in, in parallel and output them in parallel out again ?" Sorry, the translation isn't very good. I personally have never used Coregens FIR filters so don't really know what Johannes is talking about ... rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores: http://www.asics.ws/free_ip.shtmlArticle: 49248
Thomas, It should be repaired in the Service Pack 2. Unfortunately I still haven't good luck to download it correctly so I couldn't check it yet:( Regards, Jan "Thomas Buerner" <buerner@lrs.e-technik.uni-erlangen.de> wrote in message news:3DC9353C.32321019@lrs.e-technik.uni-erlangen.de... > > Hi all > > impact works fine when I use it as administrator > but brings up an error message when I try to use > it as an simple user. > does anybody know how I can use impact as user not as administrator? > > thanx > > ThomasArticle: 49249
Hi, Do you know what is the procedure and the cost to join the Altera ACAP programm? Thanks beforehand Vulcain
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