Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 50000

Article: 50000
Subject: Re: question about PCB traces for FPGA board... ?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 27 Nov 2002 22:50:49 GMT
Links: << >>  << T >>  << A >>
Just a note about the digital terminators in V2.  They are a great
feature, but they don't come for free.  Your power dissipation will
increase substantially should you use them, so make sure you consider that
when doing your thermal and power design.  We got burnt a little (no pun
intended) on that recently.  Still, a great feature, just be aware that
the terminators necessarily dissipate power.

V2 is still more expensive per CLB than virtexE, but in terms of marketing
gates it is cheaper.  If you can take advantage of the multipliers and
extra memory it is a win, especially if the DCMs or terminators are useful
to you.


"A. Karen Alfke" wrote:

> Falk Brunner wrote:
> > Switch to Virtex-II, they provide internal termination capabilities.
> >
> As Falk said, your problem disappears completely with Virtex-II, which
> is a better deal anyhow, considering several improved features, like
> better clock management and larger BlockRAMs, and (if I remember
> right) even a lower price.
> I am still on vacation, but back this coming Monday.
>
> Peter Alfke

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 50001
Subject: Re: Frequency multiplier with digital h/w
From: Marc Guardiani <marcg@fyi.DELETE.net>
Date: Wed, 27 Nov 2002 20:36:01 -0500
Links: << >>  << T >>  << A >>
Altera's Stratix FPGAs have PLLs (analog Phase Locked Loops) that have 
lower jitter than Xilinx's DLLs :-).

See 
http://www.altera.com/products/devices/apex/features/apx-20ke_jitter.html
(I am told the Stratix uses the same PLL technology as the Apex 20KE.)

Gary Desrosiers wrote:
> Xilinx's Virtex devices have DLL (Digital Delay-Locked Loop) frequency
> multipliers onboard. See;
> http://www.xilinx.com/products/virtex/techtopic/vtt003.pdf
> 
> "Skillwood" <skillwoodNOSPAM@hotmail.com> wrote in message
> news:arv489$me3js$1@ID-159866.news.dfncis.de...
> 
>>HI all experts,
>>  Can somebody say me , how to implement a frequency multipliers with
>>digital hardware without using a any combinational logic
>>
>>Thanks & Regards,
>>SKillie
>>
>>
> 
> 
> 

-- 


Marc Guardiani
marcg "at" fyi "dot" net


Article: 50002
Subject: Re: question about PCB traces for FPGA board... ?
From: "Bob" <nimby1_not_spmmm@earthlink.net>
Date: Thu, 28 Nov 2002 03:16:52 GMT
Links: << >>  << T >>  << A >>
Ray, you're right. Same thing happened to me with Virtex-II's DCI. We
planned to use it, but failed to realize how much power it really draws (per
bit). It effectively adds 200ohm from VCCO to GND (per bit) if you've set it
for 50ohm termination.

When we first loaded the FPGA, I thought we had done something wrong. Turns
out, with 64bits of DCI the thing gets HOT!

Bob


"Ray Andraka" <ray@andraka.com> wrote in message
news:3DE54C7E.123C0C68@andraka.com...
> Just a note about the digital terminators in V2.  They are a great
> feature, but they don't come for free.  Your power dissipation will
> increase substantially should you use them, so make sure you consider that
> when doing your thermal and power design.  We got burnt a little (no pun
> intended) on that recently.  Still, a great feature, just be aware that
> the terminators necessarily dissipate power.
>
> V2 is still more expensive per CLB than virtexE, but in terms of marketing
> gates it is cheaper.  If you can take advantage of the multipliers and
> extra memory it is a win, especially if the DCMs or terminators are useful
> to you.
>
>
> "A. Karen Alfke" wrote:
>
> > Falk Brunner wrote:
> > > Switch to Virtex-II, they provide internal termination capabilities.
> > >
> > As Falk said, your problem disappears completely with Virtex-II, which
> > is a better deal anyhow, considering several improved features, like
> > better clock management and larger BlockRAMs, and (if I remember
> > right) even a lower price.
> > I am still on vacation, but back this coming Monday.
> >
> > Peter Alfke
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>
>



Article: 50003
Subject: Re: Frequency multiplier with digital h/w
From: "A. Karen Alfke" <karen@2ndesign.com>
Date: Wed, 27 Nov 2002 19:31:18 -0800
Links: << >>  << T >>  << A >>
Marc Guardiani wrote:
> 
> Altera's Stratix FPGAs have PLLs (analog Phase Locked Loops) that have
> lower jitter than Xilinx's DLLs :-).
> 
It's not that simple. 
A DLL is a digital circuit, and as such has deterministic jitter.
A PLL is an analog circuit and would have zero jitter in an idealized world.

In the real world, with many signals switching and the ground
bouncing, a PLL can have more jitter than a DLL.
It all depends on the overall activity.

Peter Alfke

Article: 50004
Subject: Xilinx ISE/XST Problem or FFT Designer can help me.
From: "Sanjay Patil" <sanjay@cg-coreel.com>
Date: Thu, 28 Nov 2002 09:42:57 +0530
Links: << >>  << T >>  << A >>
Hi,
I'm doing 1024 Point FFT Processor Design.
I'm using ISE 5.1 XST Technology which supports math_real library of IEEE.
But while synthesis, it gives error that type real is not supported.
I tried to use Math_Real for simple Multiplication using '*' and it
synthesizes using ISE XST.

Can any one from Xilinx clarify this?
or anyone who is working on FFT can help me Pls.

Thanks in advance.
Sanjay




Article: 50005
Subject: Re: question about PCB traces for FPGA board... ?
From: "A. Karen Alfke" <karen@2ndesign.com>
Date: Wed, 27 Nov 2002 20:39:41 -0800
Links: << >>  << T >>  << A >>
Bob wrote:
> 
> Ray, you're right. Same thing happened to me with Virtex-II's DCI. We
> planned to use it, but failed to realize how much power it really draws (per
> bit). It effectively adds 200ohm from VCCO to GND (per bit) if you've set it
> for 50ohm termination.
> 
> When we first loaded the FPGA, I thought we had done something wrong. Turns
> out, with 64bits of DCI the thing gets HOT!

Well, well. Let's keep this in perspective:
"Digitally Controlled Impedance" is most often used as series
termination at the transmitting end, increasing the output impedance
to match the trace impedance. But it can more rarely also be be used
as parallel termination at the receiving end, avoiding the reflection.

As series terminator it does not have any static power consumption at
all, and I claim that it does not increase the dynamic power either.
Charging and discharging a load capacitance consumes and dissipates
the same amount of power, totally independent of the output
resistance. The power is f•C•Vsquared. There is no R in this equation!

Using DCI for parallel termination does cause significant power
dissipation, but remember that this is not the most popular or most
important application.

Series termination has always been ideal for single-source, single
destination interconnects. It utilizes the reflection instead of
fighting it, and it does not cost extra power. 
Parallel termination must be used when there are multiple distributed
loads on the line. It is known to be power hungry, and has been that
way for the past 50 years.
Nothing new, and nothing that Xilinx can do anything about.
Peter Alfke, Xilinx Applications
 
> 
>

Article: 50006
Subject: Re: HardMacro (from FPGA Editor) Instantiation
From: muthu_nano@yahoo.co.in (Muthu)
Date: 27 Nov 2002 20:51:16 -0800
Links: << >>  << T >>  << A >>
Hi Ryan,

With that Answer record as reference only i tried. Here i generated a
netlist of a module to which i want to make a macro with out inserting
IO pads during the synthesis using synplify. Then i did place and
Route. and i simply saved as a macro by opening the .ncd file in FPGA
editor.

the Answer record says, the IO Pads has to be uplaced and an macro
Pads should be inserted one by one. If i have so many IOs, how should
i do?

And even this approach, after i unplaced the PADs. I tried to insert
the macro IOs. But when i click the Green dot pins (as mentioned in
the answer record) the adding of macro pins in the Edit menu is not
enabled.

why is this so? Could u explain me in detail from your experience on
this.

Thanks in advance,

Best regards,
Muthu

Article: 50007
Subject: Re: question about PCB traces for FPGA board... ?
From: "Bob" <nimby1_not_spmmm@earthlink.net>
Date: Thu, 28 Nov 2002 06:21:12 GMT
Links: << >>  << T >>  << A >>

"A. Karen Alfke" <karen@2ndesign.com> wrote in message
news:3DE59E0E.F01385C4@2ndesign.com...
> Bob wrote:
> >
> > Ray, you're right. Same thing happened to me with Virtex-II's DCI. We
> > planned to use it, but failed to realize how much power it really draws
(per
> > bit). It effectively adds 200ohm from VCCO to GND (per bit) if you've
set it
> > for 50ohm termination.
> >
> > When we first loaded the FPGA, I thought we had done something wrong.
Turns
> > out, with 64bits of DCI the thing gets HOT!
>
> Well, well. Let's keep this in perspective:
> "Digitally Controlled Impedance" is most often used as series
> termination at the transmitting end, increasing the output impedance
> to match the trace impedance. But it can more rarely also be be used
> as parallel termination at the receiving end, avoiding the reflection.
>
> As series terminator it does not have any static power consumption at
> all, and I claim that it does not increase the dynamic power either.
> Charging and discharging a load capacitance consumes and dissipates
> the same amount of power, totally independent of the output
> resistance. The power is f.C.Vsquared. There is no R in this equation!
>
> Using DCI for parallel termination does cause significant power
> dissipation, but remember that this is not the most popular or most
> important application.
>
> Series termination has always been ideal for single-source, single
> destination interconnects. It utilizes the reflection instead of
> fighting it, and it does not cost extra power.
> Parallel termination must be used when there are multiple distributed
> loads on the line. It is known to be power hungry, and has been that
> way for the past 50 years.
> Nothing new, and nothing that Xilinx can do anything about.
> Peter Alfke, Xilinx Applications
>
> >
> >
>

Peter,

I was under the impression that even when one is doing series (source)
termination that the parallel load is still there. As it was explained to
me, the source model is really a current source driving the middle of the
pair of 100ohm resistors (that stretch between the supplies) -- thus giving
the 50ohm source impedance. Is this not correct?

When we did our XGMII in a pair of 2V1000's, we saw static power consumption
increase (greatly) both on the transmit and receive FPGAs. We were using
SSTL2_II_DCI IOB's.

Regards,
Bob



Article: 50008
Subject: Re: Asynchronous FIFOs using Handel-C?
From: "Bernhard Mäder" <bmaeder@ee.ethz.ch>
Date: Thu, 28 Nov 2002 09:23:07 +0100
Links: << >>  << T >>  << A >>
Hi

>
> I've been pondering this, and wondering what is a neat answer.
> When you say
> "asynchronous fifo" do you mean that data is put in to the fifo in
> one
> clock domain, and received in a different asynchronous clock
> domain?

Yes, exactly. That's what I'm trying to accomplish.


> Does the delay matter between clock domains, i.e. does it matter
> if clock cycles
> are used to resynchronise the data?

Delay is no issue, but bandwidth is.

> Is data transfer one way only?

Yes.

> The reason I ask is that in HandelC it would make sense to use
> a channel to send the data from one domain to the other, as that
> would
> take care of synchronisation - and then use a synchronous FIFO in
> the second clock domain (implemented in a RAM). The source will
> then automatically block when the channel has not been read, so
> you
> will have to make sure the data transfer on the source side can
> cope
> with this.

The only way I could get along with channels is to allocate for of 'em in
parallel (since each transfer between asynchronous clock domains takes 4
cycles of the slower clock), in order to reach my desired throughput of one
word per cycle. I don't know how big the hardware for a channel is, but I
don't think that would be the best solution.

> Using a shared MPRAM is also a recommended way by Celoxica, but
> you need
> to make sure
>
> a) you have one in the technology you are using

That's ok, I'm using a Virtex-II.

> b) you can cope with overflow /underflow somehow as the pointers
> into
> the RAM are in the two different clock domains.

Actually, I made it work now. The pointers are passed over the mpram, too
(using LUTs and FF and not block ram, of course). Allthough there is
significant delay in passing the index from one domain to the other, that
doesn't really matters if the fifo is not full or not empty (it's just that
the delay when reading from an empty fifo and a new value is written into it
at the same time is at least one clock cycle of the reading clock). So I
think I can live with that.

>
> To implement the other suggestions people have made (i.e. some
> pieces of wire going from one clock domain to the other) you would
> need to create two main() functions in two different projects, and
> then simulate with the netlist simulator to verify it (or even
> better
> build it!)
>
> regards
>
> Alan
>
>
> --
> Alan Fitch
> [HDL Consultant]
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
> Services
>
> Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire,
> BH24 1AW, UK
> Tel: +44 (0)1425 471223                          mail:
> alan.fitch@doulos.com
> Fax: +44 (0)1425 471573                           Web:
> http://www.doulos.com
>
> This e-mail and any  attachments are  confidential and Doulos Ltd.
> reserves
> all rights of privilege in  respect thereof. It is intended for
> the use of
> the addressee only. If you are not the intended recipient please
> delete it
> from  your  system, any  use, disclosure, or copying  of this
> document is
> unauthorised. The contents of this message may contain personal
> views which
> are not the views of Doulos Ltd., unless specifically stated.
>
>

Thanks for your reply

regards,

Bernhard



Article: 50009
Subject: Xilinx XC2S400E and XC2S600E
From: "Jan Gray" <jsgray@acm.org>
Date: Thu, 28 Nov 2002 01:52:14 -0800
Links: << >>  << T >>  << A >>
This month Xilinx announced two new, larger devices in their Spartan-IIE
line.

Unlike the earlier members of the family, these new devices have the same
ratio of BRAMs to LUTs as do their Virtex-E cousins.  For example, there
will be 72 BRAMs in a '2S600E.  All that and ~14 KLUTs for only $45 (next
year, huge quantity).  A wonderful development.  (No QFP package but you
can't have everything.)

A chart comparing the '2SE family with the Cyclone family, is at
fpgacpu.org#2s600e.

Jan Gray, Gray Research LLC



Article: 50010
Subject: Re: hardware image processing - log computation
From: Martin Brown <martin.brown@pandora.be>
Date: Thu, 28 Nov 2002 10:47:04 GMT
Links: << >>  << T >>  << A >>


Tim Nicolson wrote:

> I'm currently implementing an image processing algorithm in hardware.
>
>   The ip algorithm requires that I compute logarithms.  This can prove quite a computationally expensive
>   operation, but I only need accuracy down to around 4/5 significant figures.
>
Significant figures here meaning bits (easy) or decimal digits (harder)
?

>   Currently, as binary floats are represented as m*2^e, where m is a number between 1-2, I have approximated
>   the log function between 1-2 with a cubic polynomial.  I then just scale the base2 exponent and add it to the
>   result of the poly.
>
>   This method is inexpensive but gives limited accuracy.  Operations shown below
>
>
>   z = a + b*mant + c*mant^2 + d*mant^3;
>
>   if (e ~= 0)
>       z = z + exp * C1;
>   end;
>
>   This requires 6* and 4+.
>
Nothing is faster than a lookup table, but if you also need code
compactness...

Depending on how fast your hardware divide is the Pade approximant isn't
bad

    ln(1+x)  ~ x*(6+x)/(6+4*x)

Tweak the coefficients a bit and it is good to nearly 4 decimal sig fig
for 0 < x < 1

>   Unfortuately, adding extra terms to the poly increases the accuracy slowly.
>
>   So....  Does anyone know of a better way of computing the logarithm of a base2 fp number?
>
But starting from the other classic log polynomial

    ln ( (1+y)/(1-y)) = 2y + 2y^3/3 + 2y^5/5

where y = x/(2+x)

is even better and also gives a very good Pade approximant.

    ln (1 + x )  ~   2*y * (15 - 4y^2)/(15 - 9y^2)

That is already close to 5 decimal digits accuracy before any tweaking.

Maxent  might object if the resulting log implementation isn't
continuous in the first derivative.

Regards,
Martin Brown


Article: 50011
Subject: Leon Softcore and Altera
From: kriegler@sun.ac.za (Eduard Kriegler)
Date: 28 Nov 2002 04:08:42 -0800
Links: << >>  << T >>  << A >>
Has anyone tried to compile the leon core under Altera MaxPlusII or
QuartusII? I'm having difficulty setting up the model and the project
under Quartus.

Article: 50012
Subject: Re: Frequency multiplier with digital h/w
From: fpga_wonderkid@yahoo.com (FPGA Wonderkid)
Date: 28 Nov 2002 04:13:15 -0800
Links: << >>  << T >>  << A >>
"A. Karen Alfke" <karen@2ndesign.com> wrote in message news:<3DE58E06.BC3771E0@2ndesign.com>...
> Marc Guardiani wrote:
> > 
> > Altera's Stratix FPGAs have PLLs (analog Phase Locked Loops) that have
> > lower jitter than Xilinx's DLLs :-).
> > 
> It's not that simple. 
> A DLL is a digital circuit, and as such has deterministic jitter.
> A PLL is an analog circuit and would have zero jitter in an idealized world.
> 
> In the real world, with many signals switching and the ground
> bouncing, a PLL can have more jitter than a DLL.
> It all depends on the overall activity.
> 
> Peter Alfke

I agree with Peter to some extent that Xilinx DLL might socre over
Analog PLL. But Altera has done some considerable improvement to their
PLL technology with Stratix. I characterized both and found Altera PLL
working with lower Jitter comapred to DLL of Virtex. I am not sure if
there are any changes/improvements to Virtex-2pro. Stratix works
really well at elevated frequencies compared to Virt/e and v2.


FPGA Wonderkid

Article: 50013
Subject: Where can find MPEG-2 codec SOFT-IP CORE module, DCT&#12289;Motion-estimation...etc
From: m8931612@student.nsysu.edu.tw (Ru-Chin Tsai)
Date: 28 Nov 2002 05:05:30 -0800
Links: << >>  << T >>  << A >>
I prepare to implement MPEG-2 codec system for some application.
Does any one can give me some issues or suggestions about MPEG2
implemetation on FPGA v.s. DSP? Which one can reach real-time
encoding/decoding? Which one has higher complexity and cost? The
MPEG-2 codec kernel modules,
DCT&#12289;Motion-estimation(compensation)&#12289;Variable-length
coding(VLC)...etc, do any SOFT-IP CORES are available now?

Article: 50014
Subject: Re: Leon Softcore and Altera
From: "Leon Heller" <leon@heller123.freeserve.co.uk>
Date: Thu, 28 Nov 2002 13:28:30 -0000
Links: << >>  << T >>  << A >>

"Eduard Kriegler" <kriegler@sun.ac.za> wrote in message
news:1968af66.0211280408.7067ad96@posting.google.com...
> Has anyone tried to compile the leon core under Altera MaxPlusII or
> QuartusII? I'm having difficulty setting up the model and the project
> under Quartus.

There is a Leon mailing list.

Leon (no connection)
--
Leon Heller, G1HSM
leon_heller@hotmail.com
http://www.geocities.com/leon_heller



Article: 50015
Subject: question about PCB traces for FPGA board... ?
From: kayrock66@yahoo.com (Jay)
Date: 28 Nov 2002 08:46:42 -0800
Links: << >>  << T >>  << A >>
Hi Anand,

Get to know the Vertex built in impedence control well.  Its designed
for your exact kind of scenario.

Also, while its true that changing the trace width will impose an
impedance bump in your transmission line, so will putting a series
termination resistor, but since you would be putting it "close enough"
to the source, it doesn't matter.  That would be were you'd upsize the
trace if you were going to do that.  And yes your board house will
charge you a premium based on the finest pitch on the board, after the
series term resistor, and you're out in the open area away from the
BGA footprint, you could make the trace wider with benefits in yield,
aggravation, and impedance.

Regards

President, Quadrature Peripherals
Altera, Xilinx and Digital Design Consulting
email: kayrock66@yahoo.com
http://fpga.tripod.com
-----------------------------------------------------------------------------

anand287@lycos.com (Anand) wrote in message news:<a6908954.0211261743.1d96e642@posting.google.com>...
> hi everybody,
> 
> I hope this is the right audience for this question.
> 
> I am designing a Printed Circuit Board which mainly consists of an
> FPGA [XCV2000E, xilinx virtex-E 2000 part,package : FG1156 ,fine pitch
> ball grid array]  , "16" SCSI connectors [68 pin female]
> and oscillator,regulator and configuration PROM.
> 
> Now, I am using 544 I/O's of this FPGA.
> As result, I have 136 I/O's  from each side of the FPGA (four sides in
> all)
> and leaving the FPGA on various layers.
> 
> Following the Xilinx Board Routability Guidelines I chose 5 mil trace
> width for these I/O's traces.
> 
> I plan to use 33 ohm series [ source ] termination resistors for half
> of these 544 lines (since I intend to use half of them for sending and
> half of them for receiving data ; and apparently the receivers do not
> need termination)
> 
> Any suggestions on what is done in such a situation wherein one needs
> to put in "so many termination resistors " and  very  limited space
> [BGA part] is available ?
> 
> How much leeway do I have in choosing these termination resistors ?
> Is 33 ohm  acceptable as a series termination resistor for a wide
> range of trace characteristic impedances ?
> 
> Further, I believe I need to use 5 mil trace width  as  they leave the
> FPGA BGA because  the number of traces is huge considering the space
> between succesive balls in this BGA [ball grid array package].
> 
> I am not clear about the width of these traces as they move away from
> the FPGA.
> 
> Is the trace width changed along the length of the trace ,normally ?
> Say, the traces are on an average of length , 4 inches long ?
> 
> Please reply with your suggestions/comments...
> I'd really appreciate it.
> 
> thanks very much 
> regards
> Anand Kulkarni

Article: 50016
Subject: Re: question about PCB traces for FPGA board... ?
From: "A. Karen Alfke" <karen@2ndesign.com>
Date: Thu, 28 Nov 2002 08:59:25 -0800
Links: << >>  << T >>  << A >>
Bob wrote: 
> Peter,
> 
> I was under the impression that even when one is doing series (source)
> termination that the parallel load is still there. As it was explained to
> me, the source model is really a current source driving the middle of the
> pair of 100ohm resistors (that stretch between the supplies) -- thus giving
> the 50ohm source impedance. Is this not correct?
> 
Bob, I am sorry that you were mislead. 
The actual mechanism is quite straightforward:
The internal drive and/or the internal sink transistor is being
modified to mimic the external reference resistor(s).
In the case of series termination, only one of the resistors is turned
on, as you would expect. And the static power is zero.
For series termination, one can turn on parts of both transistors,
each with the desired resistance value. That's what causes the static
current and the power consumption, which can be quite high if busses
are terminated this way.
Parallel termination against an external half-voltage supply would
reduce the total static power in half, but that requires an external
resistor plus the extra supply.
I would always use series termination with DCI whenever there is a
single-source-single destination. That's what it was invented for! 
And I would always be concerned about the internal power consumption
with DCI parallel termination. But it only requires the simplest form
of arithmetic to figure out the extra power paid for the pc-board simplicity.

Everybody here in the US have a nice and relaxing Thanksgiving ! I had
a great 2 weeks in Germany and France...

Peter Alfke, Xilinx Applications

Article: 50017
Subject: Re: Custom FPGA synthesis
From: kayrock66@yahoo.com (Jay)
Date: 28 Nov 2002 09:00:17 -0800
Links: << >>  << T >>  << A >>
Synopsys Design Compiler can do this but I doubt you own a copy of
that.

Another way of doing what you want is you use the off the shelf
synthesis tool to synthesize to an intermediate format that it happens
to support (say vendor A for example).  Then you build a translation
library that says in effect: "Every time you see ALTERA_NAND2, use my
logic equivalent cell HOMEBREW_NAND with structure A,B and C".  It may
not give you an optimal result but at least you were able to code in
an HDL and somes the P&R code can make the simple optimizations you
lost in the translation.

Regards

President, Quadrature Peripherals
Altera, Xilinx and Digital Design Consulting
email: kayrock66@yahoo.com
http://fpga.tripod.com
-----------------------------------------------------------------------------

"Andy Mitchell" <acm11@york.ac.uk> wrote in message news:<as09to$4bv$1@pump1.york.ac.uk>...
> Hi,
> 
> I`m wondering if anyone knows of a synthesis tool for FPGAs (i.e.
> LeonardoSpectrum) where a custom Technology/architecture can be specified as
> opposed to using the existing Technologies (i.e. Xilinx Virtex)...I`ve heard
> that a plug-in/module exists for Leonardo which allows this but I cant seem
> to find any information on it..
> 
> Many thanks for any help.
> 
> --

Article: 50018
Subject: Re: Asynchronous FIFOs using Handel-C?
From: "A. Karen Alfke" <karen@2ndesign.com>
Date: Thu, 28 Nov 2002 09:15:30 -0800
Links: << >>  << T >>  << A >>
I just caught up with this long thread...
From a hardware point of view, an asynchronous FIFO with clock rates
up to 150 MHz is quite simple. The basic mechanism uses a dual-ported
BlockRAM with independent addressing of each port, one for writing,
one for reading.(They can even be of different width).
All the difficulty lies in the generation of FULL and EMPTY, which
requires comparing the two address counters in  two different clock domains.
That's why these counters must be Grey-coded (only one bit changing at
any time), and I find it easiest to generate the Grey code by XORing
adjacent binary counter bits. The leading edge of FULL ( and the
leading edge of EMPTY) is actually synchronous with respect to the
clock domain where it is relevant. It is the trailing edge of these
signals that must be transferred across the clock domains. But luckily
this does not require the ultimate speed, so it can be
double-synchronized. 
I have published some papers in Xilinx TechXclusives, also about the
related topic of metastability.

Peter Alfke, Xilinx Applications
presently with
Karen Alfke
2nd Nature Design
Port Townsend, WA
karen@2ndesign.com

Article: 50019
Subject: Re: Anybody know of vendors of PCI boards with FPGAs?
From: r.white@nallatech.com (Robert)
Date: 28 Nov 2002 09:41:34 -0800
Links: << >>  << T >>  << A >>
skintigh@yahoo.com (Seth) wrote in message news:<ab6e8fe6.0211251516.2851d6bd@posting.google.com>...
> I am looking for vendors of PCI FPGA boards for production, not just
> prototyping.
> 
> So far I know of Annapolis Microsystems which offers boards with
> Virtex chips and RAM.
> 
> Can anyone recommend any others?

You can check www.nallatech.com

Robert

Article: 50020
Subject: Re: question about PCB traces for FPGA board... ?
From: "Bob" <nimby1_not_spmmm@earthlink.net>
Date: Thu, 28 Nov 2002 17:42:32 GMT
Links: << >>  << T >>  << A >>

"A. Karen Alfke" <karen@2ndesign.com> wrote in message
news:3DE64B6D.FEC6BA65@2ndesign.com...
> Bob wrote:
> > Peter,
> >
> > I was under the impression that even when one is doing series (source)
> > termination that the parallel load is still there. As it was explained
to
> > me, the source model is really a current source driving the middle of
the
> > pair of 100ohm resistors (that stretch between the supplies) -- thus
giving
> > the 50ohm source impedance. Is this not correct?
> >
> Bob, I am sorry that you were mislead.
> The actual mechanism is quite straightforward:
> The internal drive and/or the internal sink transistor is being
> modified to mimic the external reference resistor(s).
> In the case of series termination, only one of the resistors is turned
> on, as you would expect. And the static power is zero.
> For series termination, one can turn on parts of both transistors,
> each with the desired resistance value. That's what causes the static
> current and the power consumption, which can be quite high if busses
> are terminated this way.
> Parallel termination against an external half-voltage supply would
> reduce the total static power in half, but that requires an external
> resistor plus the extra supply.
> I would always use series termination with DCI whenever there is a
> single-source-single destination. That's what it was invented for!
> And I would always be concerned about the internal power consumption
> with DCI parallel termination. But it only requires the simplest form
> of arithmetic to figure out the extra power paid for the pc-board
simplicity.
>
> Everybody here in the US have a nice and relaxing Thanksgiving ! I had
> a great 2 weeks in Germany and France...
>
> Peter Alfke, Xilinx Applications
>

Peter,

Thanks for the explanation. We have avoided using DCI since are busses are
generally very wide, and were concerned about the power consumption. Perhaps
we made some type of error in defining our IOBs' DCI output characteristics
in our XGMII design. The use of (external) series termination is very common
in our boards, and almost all of our new designs utilize Virtex-II.

Having said that, I can't believe you went to Germany and France and didn't
take me along with you. Maybe next time?

Bob



Article: 50021
Subject: Re: Metastability in FPGAs
From: "A. Karen Alfke" <karen@2ndesign.com>
Date: Thu, 28 Nov 2002 09:44:20 -0800
Links: << >>  << T >>  << A >>
Michael S wrote:
> 
> hmurray@suespammers.org (Hal Murray) wrote in message news:<utd7cdm3r2gsac@corp.supernews.com>...
> > >I am not familiar with the techXclusive, can you provide a URL?
> >
> >  http://support.xilinx.com/support/techxclusives/metas-techX32.htm
> 
> Good article. Unfortunately, it doesn't mention the temperature
> conditions for the mesurements.
> 
> Recently we suffered a problem which I attribute to metastability. Our
> design fed Intel 386EX processor with asynchronous READY# signal.
> Simetimes it caused the hang up. The processor's RD# signal was
> indicating that READY# is accepted while correspondent CS# signal
> remained asserted, indicating that READY# was missed. Looks like
> classic metastability problem, doesn't it ?!
> The problem was very temperature dependent. I never did a statistical
> mesurements (was to busy to understand and resolve the problem), but
> there was at least order of magnitude difference between  0 and -20deg
> Celsius (the colder is worse).
> Theoretically, the strong temperature dependance is expectable. It
> would be fine if Xilix will provide us with temperature data.

Sorry for the late response.
I strongly believe that your problem was due to the difference in
capture time between the two signals, not at all to metastability.
Metastabilty resolves faster when the gain-bandwidth product of the
master-latch feedback loop is higher.
That means it resolves faster at low temperature! (Contradicting your theory)
I did not vary temperature, but varied Vcc instead. Changing Vcc is so
much simpler than changing temperature !
High Vcc is equivalent to low temperature or fast processing. 
Low Vcc is equivalent to high temperature or slow processing. 

Metastability is very often blamed for completely unrelated sins.
Synchronizing an asynchronous input in more than one flip-flop is the
most common deadly sin.

Peter Alfke, Xilinx Applications

Article: 50022
(removed)


Article: 50023
Subject: Re: question about PCB traces for FPGA board... ?
From: "A. Karen Alfke" <karen@2ndesign.com>
Date: Thu, 28 Nov 2002 10:21:59 -0800
Links: << >>  << T >>  << A >>
Peter wrote
> > 
> > .........For series termination, one can turn on parts of both transistors,
> > each with the desired resistance value. That's what causes the static
> > current and the power consumption, which can be quite high if busses
> > are terminated this way.

I should of course have written: For parallel termination....
Too much German beer of French wine???
Peter Alfke, Xilinx Applications
> >

Article: 50024
Subject: Re: question about programmable oscillator ?
From: kolja@bnl.gov (Kolja Sulimma)
Date: 28 Nov 2002 10:34:15 -0800
Links: << >>  << T >>  << A >>
anand287@lycos.com (Anand) wrote in message news:<a6908954.0211261143.68ae094c@posting.google.com>...
> hi everybody,
> 
>  I am looking for a programmable oscillator for a XCV2000E board .
> i.e the VIRTEX-E 2000 part. This FPGA has 3.3 volt I/O's.
> 
> (So I assume it needs 3.3 v oscillator ???)
> 
> I need it to be programmable between say, 1Mhz to 120 Mhz.
> Moreover I need to be able to program it "after" it has been installed
> on the board.
> 
> Also, the programming needs to be accomplished in a simple way ;
> 
> I am not knowledgeable enough to devise elaborate programming options
> like something that XESS does using their XESS setclk program etc.

Check www.icst.com for their ICS525-01 part.
A frequency from 1MHz to 160MHz is selected by selectivly pulling
input pins to ground.
You can solder the pins to a fixed voltage, or connect them to DIP
switches or even FPGA outputs.

Kolja Sulimma



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search