Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, In dual port Block RAMs, we are having 2 ports (A and B) which is running on independent clock domains. There is a possiblity of occuring an Tbcss Violation(Clock to Clock setup time violation if the addresses are same and any one of the port is doing write operation) Due to this metastabilty issue, the output bus will be XXXX...??? Can't we avoid this using any synchronisers? First of all, is this violations cause any major issues in the design? Best regards, MuthuArticle: 50101
> > So, why exactly are you telling me this? You asked a technical question, I > recommended you to take a look at their ASIC, not their boards. What all of > this board/development tools cost math has to do with the original question? > My original question was to see if anyone had interfaced a SHARC to a PCI bridge using a FPGA, and in particular, the details regarding the state diagrams. You are correct in that my response had little to do with your recommendation. Bittware has been contacted regarding a quote for the SFIN-161, but based on their current pricing schedules as listed, it will probably be cost prohibitive for my particular application. Thanks for your input.Article: 50102
John, I believe the SharcFin is based on one of the QuickLogic FPGA's which has a hardwired PCI core. If you ask I can dig up the exact part number. So, you could design your own interface chip based on the same part... If I were you I would stay away from any of the soft PCI cores, not to mention designing your own unless your quantities can justify $20-30 economy or you are fighting for every square inch of your board space. Regards, /Mikhail "John Jacob" <jjacob@graphite.com> wrote in message news:asfl2n$jdp$1@iruka.swcp.com... > > > > So, why exactly are you telling me this? You asked a technical question, I > > recommended you to take a look at their ASIC, not their boards. What all > of > > this board/development tools cost math has to do with the original > question? > > > My original question was to see if anyone had interfaced a SHARC to a PCI > bridge using a FPGA, and in particular, the details regarding the state > diagrams. You are correct in that my response had little to do with your > recommendation. Bittware has been contacted regarding a quote for the > SFIN-161, but based on their current pricing schedules as listed, it will > probably be cost prohibitive for my particular application. > > Thanks for your input. > >Article: 50103
Hi Muthu, Two things to check are: make sure that you saved the .ncd file as a macro before trying to add macro I/O. It won't let you do any macro functions such as adding macro I/O without already having saved the file as a .nmc file. The other thing (probably not your case) is to make sure that any I/O that may have made it into your .ncd/.nmc file is no longer there. Change the list menu to show all unrouted nets and delete the nets if they're going to I/O pads. Since you said that you have no IOBs (without I/O pads inserted by synplify) the first issue is most likely what you're seeing. If neither of these solves the problem, please file a case at support.xilinx.com or by calling the hotline (if you're in the US, that number is 800-255-7778). Very best regards, Ryan Laity Xilinx Applications Muthu wrote: > Hi Ryan, > > With that Answer record as reference only i tried. Here i generated a > netlist of a module to which i want to make a macro with out inserting > IO pads during the synthesis using synplify. Then i did place and > Route. and i simply saved as a macro by opening the .ncd file in FPGA > editor. > > the Answer record says, the IO Pads has to be uplaced and an macro > Pads should be inserted one by one. If i have so many IOs, how should > i do? > > And even this approach, after i unplaced the PADs. I tried to insert > the macro IOs. But when i click the Green dot pins (as mentioned in > the answer record) the adding of macro pins in the Edit menu is not > enabled. > > why is this so? Could u explain me in detail from your experience on > this. > > Thanks in advance, > > Best regards, > MuthuArticle: 50104
hmurray@suespammers.org (Hal Murray) wrote in message news:<uuik52376mnb11@corp.supernews.com>... > >So the question should be re-phrased: Any hints on how to get the best > >carry performance out of an Altera 10k (-4). > > You are just adding a number (from a register) into an accumulator. > Right? You don't care about a delay (pipeline) as long as you can > keep adding that number in on each clock cycle. > Thanks Hal, you have answered the question spot on. I understand your argument, also the need for extra pipelining in the lower half of the accumulation registers to ensure all bits of the addition appear at the same time. You were right in saying that one of the input add coefficient is a constant (well not quite, as it is controlled up and down slowly by a digital PLL). Hence the need for the extra pipelining. I shall try implementing your idea as three groups of 8 adders (The Altera 10K device seems to group LAB registers in eights). This may work optimally, we shall see..... Again, thanks to all who responded... theoArticle: 50105
--------------847803BB5A9767B7F2BDE6F7
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
For JTAG cable and some other FPGA products see
http://members.rogers.com/petikian01/seytronix/products.html
Regards!
Seiran
RFrank1234 wrote:
> Where can I find low cost 3rd party Xilinx j-tag programmer? I have found low
> cost programmers for Altera, but not Xilinx. Does anyone know where I can find
> one that is compatible with Xilinx's DLC-7 programmer?
>
> Thanks,
>
> Ryan Frnaklin
> rfrank1234@aol.com
Article: 50106zhengyu wrote: > does anyone have any idea on the complexity of implementing a string to > integer conversion is hardware? > It's got to be quite complicated. Not complex, but I can't imagine a motivation to do so. If you need to do math on an fpga, consider signed or unsigned input vectors. -- Mike TreselerArticle: 50107
Hello, all, I have developed some products using Xilinx FPGAs and CPLDs. I have had some problems with certain customers blowing out these devices, and suspected they may be using really bad ESD procedures, and just kind of ignored the problem. Then, I was testing a board on the bench with an XCS30-3TQ144C Spartan 5V FPGA. I powered it up, tested it, all looked good. I turned it off, turned it back on, and it wouldn't configure. A quick check indicated the power supply was overloaded. I took out the regulator chip and hooked it to a bench supply, and found it would draw about 1.8 A at only 3 V. My bench supply was at current limit. I removed several other parts, and determined the Spartan was drawing all the current. Now, from reading other info on ESD, this may have been a latent fault that chose that moment to develop. My experience is that I can count on one hand all the other chips I've blown out. But, now, I seem to be getting a very large pile of Xilinx parts that have died. Anyway, this device is mostly opto-isolated, but has a connector to a PC's parallel port. I think that is the path that needs to be protected. Does anyone have any suggestions on what I should put into the next revision? Has anyone fought this sort of problem before? I plan on putting one of those diode clamp packs in to clamp all lines between gnd and +5 V, and see if that prevents any more of these problems. Has anyone tried this approach, or are TVS devices a better plan? Thanks in advance for all comments! JonArticle: 50108
It is trivial ASCII 0 = 0x30, 1 = 0x31 ... take in char and it with 0xf. Steve "zhengyu" <zhengyu@attbi.com> wrote in message news:F_uG9.201727$QZ.29995@sccrnsc02... > does anyone have any idea on the complexity of implementing a string to > integer conversion is hardware? > It's got to be quite complicated. > > Jimmy > >Article: 50109
Hi everybody, I came across this statement with reference to a series termination resistor in a book called "EMC and the Printed Circuit Board ......." by Mark Montrose. The book says: "This resistor must be located directly at the output of the driver without the use of a via between component and resistor." But in my design I have a large BGA part (FPGA). [ placed on the top layer] Because of so many I/O signals and the the required series termination I am forced to use vias between component driver output and the termination resistor (placed on bottom layer). Is this acceptable ? The design is maximum 100 Mhz. please do reply with your comments and suggestions ... thanks very much , Anand KulkarniArticle: 50110
It's absolutely fine to have a via and/or some track between the driver and the resistor. The driver sees the effective impedance and behaves appropriately - that impedance is altered only slightly at the edge rates you should expect to experience. If you had severl vias and a couple inches of track before the resistor (such as you'll find in many motherboards for the DDR memory interface) you'll still get good results, just not "pristine." The comment made by the author is probably severely over-constrained for most applications. "Anand" <anand287@lycos.com> wrote in message news:a6908954.0212021348.5dfe161d@posting.google.com... > Hi everybody, > > I came across this statement with reference to a series termination > resistor in a book called "EMC and the Printed Circuit Board ......." > by Mark Montrose. > > The book says: > > "This resistor must be located directly at the output of the driver > without the use of a via between component and resistor." > > But in my design I have a large BGA part (FPGA). [ placed on the top > layer] > Because of so many I/O signals and the the required series termination > I am forced to use vias between component driver output and the > termination resistor (placed on bottom layer). > Is this acceptable ? > > The design is maximum 100 Mhz. > please do reply with your comments and suggestions ... > thanks very much , > > Anand KulkarniArticle: 50111
If you "simultaneously" write conflicting data from two ports into the same location, the conflicting bits end up unknown. X signifies the unknown state, not necessarily metastability. In reality, the later write operation wins, but when they are very close together, you don't know which one is later. Metastability is not the issue, it would resolve very fast. Almost simultaneous writing is the issue. There is no remedy, except reading after writing or locking out the simultaneous write clocks. Peter Alfke, Xilinx Applications =================== Muthu wrote: > Hi, > > In dual port Block RAMs, we are having 2 ports (A and B) which is > running on independent clock domains. There is a possiblity of > occuring an Tbcss Violation(Clock to Clock setup time violation if the > addresses are same and any one of the port is doing write operation) > > Due to this metastabilty issue, the output bus will be XXXX...??? > Can't we avoid this using any synchronisers? > > First of all, is this violations cause any major issues in the design? > > Best regards, > MuthuArticle: 50112
Jon Elson wrote: > > Hello, all, > > I have developed some products using Xilinx FPGAs and CPLDs. I have had > some problems with certain customers blowing out these devices, and > suspected > they may be using really bad ESD procedures, and just kind of ignored > the problem. > > Then, I was testing a board on the bench with an XCS30-3TQ144C Spartan 5V > FPGA. I powered it up, tested it, all looked good. I turned it off, > turned it back > on, and it wouldn't configure. > A quick check indicated the power supply > was overloaded. > I took out the regulator chip and hooked it to a bench supply, and found > it would draw > about 1.8 A at only 3 V. My bench supply was at current limit. I > removed several > other parts, and determined the Spartan was drawing all the current. > Now, from reading > other info on ESD, this may have been a latent fault that chose that > moment to develop. > > My experience is that I can count on one hand all the other chips I've > blown out. But, now, I > seem to be getting a very large pile of Xilinx parts that have died. You could check the pin characteristics, on the dead pile, to see if any show leakage/damage signs. > Anyway, this device is mostly opto-isolated, but has a connector to a > PC's parallel > port. I think that is the path that needs to be protected. Does anyone > have any > suggestions on what I should put into the next revision? Has anyone > fought this > sort of problem before? I plan on putting one of those diode clamp > packs in to > clamp all lines between gnd and +5 V, and see if that prevents any more > of these > problems. Has anyone tried this approach, or are TVS devices a better plan? Sounds like the PC Parallel port is directly connected to the FPGA ? Diode clamps would seem best, or even a 1284 buffer device, eg fairchild. Series R also helps reduce the currents. Damage modes could be ESD, which should be pin-specific, or triggered latch-up, which does not need ESD voltages to occur. Latch up needs just enough injection current from < 0V, or > 5V, to get the lateral thyristor above the trigger threshold, and then it crowbars the Vcc until power is removed. You can test latch-up currents yourself - when we tried this on CPLDs, we found +ve latch up needed high voltages (10-14V) to get enough injection, and at that level it's a debate on current/voltage trigger. -ve latchup has a steeper diode, and less minus voltage injection was needed but it was still in the hundreds of mA. We also tested the thyristor holding current, thinking that a smart powersupply could self cure this problem - but found they are actually quite good thyristors, with 5-10mA region holding currents!Article: 50113
"MM" <misoma@NOrogersSPPAMM.com> wrote in message news:<dGKG9.1386$yq.34708@news>... > John, > > I believe the SharcFin is based on one of the QuickLogic FPGA's which has a > hardwired PCI core. If you ask I can dig up the exact part number. So, you > could design your own interface chip based on the same part... > > If I were you I would stay away from any of the soft PCI cores, not to > mention designing your own unless your quantities can justify $20-30 economy > or you are fighting for every square inch of your board space. > > Regards, > /Mikhail > > > > > > My original question was to see if anyone had interfaced a SHARC to a PCI > > bridge using a FPGA, and in particular, the details regarding the state > > diagrams. You are correct in that my response had little to do with your > > recommendation. Bittware has been contacted regarding a quote for the > > SFIN-161, but based on their current pricing schedules as listed, it will > > probably be cost prohibitive for my particular application. > > > > Thanks for your input. > > > > Hiya, I have used the sharc for a project in which we directly interfaced to an FPGA. The sharc seemed pretty easy in this respect as it provided very easy to decode interface signals. Recently we have been using boards from alpha data (www.alpha-data.com) which interface virtex II's to PCI. They came with a PCI bridge chip (sorry I cant remember the part offhand) and more importantly VHDL to interface to it. Having played with their PCI interface I do not think it would be all that hard to connect a sharc to it. Try having a chat with alpha data as I have found them very helpful. One word of caution - though I found the sharcs outside world interface good I was not particularly impressed with the processor itself. The development environment crashed all the time (then again so did my code) and the CPU was well underpowered so we had to move virtually everything into the FPGA. Hopefully the TigerSharc will be better (or your project better planned...!). Cheers, Andy.Article: 50114
hi. everybody, I wrote a program in VHDL to realize the following function : if en=1 ,x is latched into reg_x, y is latched into reg_y after "not" has been excuted in alu. if en=0 , x adds y in alu. I used xilinx2.1 to simulate it but failed , and i found that x was latched into reg_x just when en=0, but y into reg_y when en=1. Someone have told me that there must be something wrong with the difference with register and latch , but he knows little about it. Can you help me ? Thank you!Article: 50115
muthu_nano@yahoo.co.in (Muthu) wrote in message news:<28c66cd3.0212020451.4fcf0b@posting.google.com>... > Hi, > > In dual port Block RAMs, we are having 2 ports (A and B) which is > running on independent clock domains. There is a possiblity of > occuring an Tbcss Violation(Clock to Clock setup time violation if the > addresses are same and any one of the port is doing write operation) > > Due to this metastabilty issue, the output bus will be XXXX...??? > Can't we avoid this using any synchronisers? > > First of all, is this violations cause any major issues in the design? > > Best regards, > Muthu Hello, I would really suggest you avoid the possibilty of the read/write adresses conflicts if you can. You can grab code for asynchronous FIFO's from the Xilinx website and (with some effort) make them work reliably. Try starting at: www.xilinx.com/support/techxclusives/fifo-techX18.htm to find an appropriate source code. I would suggest you test it seperately in hardware first as it can be very difficult to take asynchronous clock domains from simulation to hardware. Cheers, Andy.Article: 50116
My program : Library IEEE; use IEEE.std_logic_1164.all; use work.alu_package.all; entity x_y is port(x,y:in std_logic_Vector(7 downto 0); z:out std_logic_vector(7 downto 0); en:in std_logic); end x_y; end x_y; architecture alg of x_y is signal a_in,b_in,c_out,reg_x,reg_y:std_logic_vector(7 downto 0); signal ci_in:std_logic_vector(1 downto 0); begin z<=c_out; u1:alu8 port map(a_in,b_in,c_out,ci_in); step1:process(en,x,c_out) begin if en='1' then reg_x<=x; reg_y<=c_out; end if; end process; step2:process(en,y) begin if en='1' then a_in<=y; ci_in<="01"; b_in<="00000000"; else b_in<=reg_x; b_in<=reg_x; a_in<=reg_y; ci_in<="10"; end if; end process; end alg; Thanks ! :)Article: 50117
"MM" <misoma@NOrogersSPPAMM.com> wrote in message news:dGKG9.1386$yq.34708@news... > John, > > I believe the SharcFin is based on one of the QuickLogic FPGA's which has a > hardwired PCI core. If you ask I can dig up the exact part number. So, you > could design your own interface chip based on the same part... > > If I were you I would stay away from any of the soft PCI cores, not to > mention designing your own unless your quantities can justify $20-30 economy > or you are fighting for every square inch of your board space. > If it's no trouble, I would appreciate it. Another gentleman suggested using a FPGA for the PCI Bridge chip itself. An implementation is available from http://www.opencores.com/projects/pci/, however, it is my understanding that it has not been used on a real system. An excellent article by Intel on the efficient use of the PCI stated that advanced PCI commands (Memory Read Line, Memory Read Multiple, Memory Write Invalidate, etc.) should be used for optimum data transfers. See http://suport.intel.com/support/chipsets/PC1001.HTM. Although the soft core would allow a more tailorable bridge and cache to be designed, your advice is well taken with regards to the soft cores. Troubleshooting them would be a nightmare. As to board space, at present that is not an issue.Article: 50118
That's why I asked this question. Since I am not familiar with the characteristic of DLL, I'd like to know what kind of mechanism I have to design to overcome the clock difference of DLL... Should it be asynchronous FIFO, or double buffer or different clock edge sampling, or something... Of course, I knew the asynchronous FIFO is safest, but the size is also largest. "Nachiket Kapre" <nachikap@yahoo.com> > why dont you try synchroniser across the two domains since that will > make your deisgn safer and independent of jitter which as ray > mentioned is suscptibel to rpocess vaiations and other physical > factors like temeperature.. > > Nachiket Kapre > Design Engineer > Paxonet Communications > > > "louis" <n2684172@ms17.hinet.net> wrote in message news:<arcgqh$3og@netnews.hinet.net>... > > There's a external clock input (20MHz) on my system, and I multiply > > it to 2X (40MHz) by DLL as the working clock. > > However, I have to exchange data in several > > modules between these two clock domains. I don't know if it safe to sample data > > on both positive edges of these two clocks? > > Will the clock jitter cause the metastability? Or I have to generate data > > on positive edge and retrieve data on negative edge instead? > > The target chip is SpartanIIE. Any comment and suggestion will be very > > appreciated. > > > > louisArticle: 50119
Check the number of port connections in the behavorial module, post-PAR module, as well as in the instantiated version of the same module in the test fixture. Sometimes they are different. Why? Don't know! "Cisa" <yxjiang2002@sina.com> wrote in message news:ee7ab64.-1@WebX.sUN8CHnE... I use several 32*16bits Distributed RAM core in my program.Behavioral simulation is ok,but in post-place and route simultation,Modelsim informs me that "Too few port connections",and the outputs is in High-Z states.What does the question lies in ? # WARNING: testR.tf(46): [TFMPC] - Too few port connections. # Region: /testbench/uut Thans very much!!!Article: 50121
If I understand what you want to do its convert a decimal string such as "1234" to 16 bit number? Off the top of my head I'd do something like going digit by digit, MS digit down to LS digit, subtracting the ASCI code for '0' from each digit, then adding it into an accumulator, then multiplying the accumulator times 10, repeat. A 10X multiply takes one adder. Regards President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- "zhengyu" <zhengyu@attbi.com> wrote in message news:<F_uG9.201727$QZ.29995@sccrnsc02>... > does anyone have any idea on the complexity of implementing a string to > integer conversion is hardware? > It's got to be quite complicated. > > JimmyArticle: 50122
Hi, Putting the resistor directly to the pin is best but mostly not applicable. Put it as near to the case of the FPGA as possible. Also the layering of the PCB is important. 4 layer boards are usually OK. Be aware to have a power plane next to the signal layer that the elecrical field can close to the power plane. Thomas Anand wrote: > Hi everybody, > > I came across this statement with reference to a series termination > resistor in a book called "EMC and the Printed Circuit Board ......." > by Mark Montrose. > > The book says: > > "This resistor must be located directly at the output of the driver > without the use of a via between component and resistor." > > But in my design I have a large BGA part (FPGA). [ placed on the top > layer] > Because of so many I/O signals and the the required series termination > I am forced to use vias between component driver output and the > termination resistor (placed on bottom layer). > Is this acceptable ? > > The design is maximum 100 Mhz. > please do reply with your comments and suggestions ... > thanks very much , > > Anand KulkarniArticle: 50123
Does any know the difference between block and distributed RAM in terms of application and functionality. The question seems trivial but please enlighten just to verify my doubt. Thanks. There is no where to find the difference.Article: 50124
"zhengyu" <zhengyu@attbi.com> wrote in message news:<6VuG9.196753$NH2.11766@sccrnsc01>... > I am looking for C behavior model for Content addressable memory. > > Also does anyone have links to tutorials of CAM? For CAM links, look at makers' sites. Most of them will have some white-papers, including tutorials about general CAM operation (sorry - don't have links available; been some time since I've used a CAM). There are also some CAM white-papers and application notes in the Xilinx and Altera sites. Writing a C model yourself is easy, and you will surely learn more than from using a model from someone else: * define an Key array of N items (N = CAM depth), each as wide as the CAM word (some C compilers do and some don't support 64-bit integers; most don't support wider words - you may want to make each Key item an array of bytes for very wide word). * define an additional State array of of N words; minimal states are empty and not-empty; you may want to add aging information etc. depending on the complexity of your CAM. * Initialize the array by setting all state words to empty. * Search operations run a loop from 0 to N-1, comparing the input value with each non-empty word in the Key array; if a match is found, return the index of the item in the array. The compare operation may use a mask for a Trinary operation (which is a fancy name for a search with mask - each bit has three states). * Insert operations search for an empty entry in the array and write the value in it (if found); if can't find an empty entry, may fail or overwrite an existing entry (this is where aging information is useful). Insertion policy is different between CAM types, and may also be programmable for some CAMs. * Delete operations can be either by key or by index. Delete by key search for a key to get the index; when you have the index, change the state to empty. * Flush operations mark all keys as empty. * Search for a multiple occurences of a key start a new search from the index of the previous match. These are the basic CAM operations; you can define more operations from combinations of these operations. Regards Assaf Sarfati
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z