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Hi, I think it's a 1:16 demux,but not a 16:1 mux. Zhou On Sat, 7 Dec 2002, Nicholas C. Weaver wrote: > In article <Pine.SOL.3.96.1021207160333.7392A-100000@vcmr-86.server.rpi.edu>, > Jingjing (Amy) Hu <huj5@rpi.edu> wrote: > >Hi, > > I am having some questions on Virtex 2.5 V architecture now. > >If you look at the Xilinx databook on pg5 (ds003-2.pdf), what's the > >function of CE and REV on the Flip-flop block? > > CE is clock enable. REV, do you mean SR (set reset)? > > > When Xilinx implements the LUT in the CLB,it needs a 4-16 decoder > >inside.Is there a good decoder design available to the public? > > Its a 16-1 mux, nothing really special. > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu > >Article: 50301
In article <Pine.SOL.3.96.1021208114534.15707A-100000@vcmr-86.server.rpi.edu>, Kuan Zhou <zhouk@rpi.edu> wrote: >Hi, > I think it's a 1:16 demux,but not a 16:1 mux. 16-1 mux, it selects 1 bit out of 16 SRAM cells. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 50302
Take a look at our Hotman Software. It can read in an Altera Raw file and it runs under Linux. You can port your cable and you can also support Xilinx devices. Steve "James Wang" <minfordtec@aol.com> wrote in message news:9ed66736.0212070741.1c02bae8@posting.google.com... > Hi Friends, > > We are making Altera FPGA and EPLD download BYTEBlaster. It can > replace Altera ByteBlaster and ByteBlaster MV to program/configure > various PLD device, reliable and affordable with the price of only > US$30.00. We also sell FPGA demo board. > For detail information or buy on-line, please check at http://www.minford.ca. > > Our new product USB JTAG download cable for Altera device is coming soon. > > Thanks, > > James Wang > Minford Technology > E-mail: minfordtec@aol.com > http://www.minford.caArticle: 50303
"Jingjing (Amy) Hu" <huj5@rpi.edu> wrote in message news:Pine.SOL.3.96.1021207160333.7392A-100000@vcmr-86.server.rpi.edu... > Hi, > I am having some questions on Virtex 2.5 V architecture now. > If you look at the Xilinx databook on pg5 (ds003-2.pdf), what's the > function of CE and REV on the Flip-flop block? CE (pin to the CLB) or EC (label on the flop) is the clock enable input. The REV on the flop is connected to BY while the INIT on the flop is connected to the CLB's SR line. When you're implementing a register with a synchronous reset (asynchronous clear) or a synchronous set (asynchronous preset) you use the single SR line to INIT the register value. When you use both set and reset (or clear and preset) you need two control lines - the second comes in on the REV signal. I believe the INIT always takes precedence over the REV, but you can see the particulars in the Xilinx library guide in the Software Manuals section of their site. > When Xilinx implements the LUT in the CLB,it needs a 4-16 decoder > inside.Is there a good decoder design available to the public? > > > Amy The decoder is conceptually just a simple SRAM. There are 16 bits addressed through 4 "address" bits that gives you a single data output. A major advantage in the Xilinx architecture is that they added a little extra silicon to not only allow a read of this 16 bit RAM, but also a write if you use the CLB SelectRAM primitives (or properly infer the structures in your HDL design). There's even a shift register mode these simple lookup tables can produce that uses the four "address" bits to give you a 16:1 mux from the serially linked memory elements. When you wonder about a good "decoder design" I can't be sure if you're trying to understand the operation of the LUT a little more or if you want to apply the function. If you want to understand the operation, looking into SRAM operation might be the best bet: 6 transistor cells and all that.Article: 50304
Hi,
But when you initialize the LUTs,you need 4:16 demux to select the RAM
and write 1 or 0 inside.
sincerely
-------------
Kuan Zhou
ECSE department
On Sun, 8 Dec 2002, Nicholas C. Weaver wrote:
> In article <Pine.SOL.3.96.1021208114534.15707A-100000@vcmr-86.server.rpi.edu>,
> Kuan Zhou <zhouk@rpi.edu> wrote:
> >Hi,
> > I think it's a 1:16 demux,but not a 16:1 mux.
>
> 16-1 mux, it selects 1 bit out of 16 SRAM cells.
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
>
>
Article: 50305Dear All, I have completed my work on a radix-4 booth multiplier. Now I have to complete its vlsi layout. Unfortunately, I have only some vhdl knowledge and completely new to vlsi design. Which free or low-priced vhdl design software is suitable for my needs. ThanksArticle: 50306
Hello, We have incorporated Maxim max1617a temperature sensor chips onto a new board we just designed. We have a 1617 for each Virtex and Virtex 2 chip on the board. We are finding that the temperature measurement jumps around a lot when we are actually processing data in the sensed Virtex 2 fpga. Does anyone know if the max1617a is affected by switching noise or ground bounce in such a way that it is innacurate when the sensed fpga is in heavy operation? -- Pete Dudley Arroyo Grande SystemsArticle: 50307
Prashant You are not alone. We have encountered the same problem with quartusII and their lpm synchronous rams. We spent quite a bit of time trying to determine the cause of the problem. Unfortunately the quartus tool just does not give the necesary unambiguous timing report that is necesary to get to the bottom of this. We could never determine the source of the error or even if really was an error. Give me Xilinx ISE anytime over QuartusII. If you figure it out please post the answer. -- Pete Dudley Arroyo Grande Systems "Prashant" <prashantj@usa.net> wrote in message news:ea62e09.0212061100.79167be6@posting.google.com... > Hi, > I have a very simple piece of code pasted below. This code has hold > time violations in it when I synthesize it in Quartus II 2.0. I > understand why the code shows the violations but can't see a way to > fix it. Any help would be appreciated. > > -------------------------------------------------------------------------- ----- > LIBRARY ieee; > USE ieee.std_logic_1164.all; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > use ieee.std_logic_arith.all; > > entity sync_we32_ram_18_wrap is > port ( > address : IN STD_LOGIC_VECTOR (3 DOWNTO 0); > we : IN STD_LOGIC := '1'; > inclock : IN STD_LOGIC ; > outclock : IN STD_LOGIC ; > data : IN SIGNED (17 DOWNTO 0); > s_q_signed : OUT SIGNED (17 DOWNTO 0) > ); > end sync_we32_ram_18_wrap; > > architecture RTL of sync_we32_ram_18_wrap is > > component sync_we32_ram_18 > PORT > ( > address : IN STD_LOGIC_VECTOR (3 DOWNTO 0); > we : IN STD_LOGIC := '1'; > inclock : IN STD_LOGIC ; > outclock : IN STD_LOGIC := '1'; > data : IN STD_LOGIC_VECTOR (17 downto 0); > q : OUT STD_LOGIC_VECTOR (17 downto 0) > ); > END component; > > signal s_data : std_logic_vector(17 downto 0); > signal s_q : std_logic_vector(17 downto 0); > begin > > sync_ram_18 : sync_we32_ram_18 port map (address, we, inclock, > outclock, s_data, s_q); > > process (inclock) > begin > if inclock'EVENT and inclock = '1' then > s_data <= CONV_STD_LOGIC_VECTOR((CONV_INTEGER(s_q)),18); > s_q_signed <= CONV_SIGNED((CONV_INTEGER(s_q)),18); > end if; > end process; > end RTL; > -------------------------------------------------------------------------- ----- > > The ram instantiated in the design is created automatically using the > Megawizard (create lpm_ram_dq) in Quartus II 2.0. > > Thanks, > PrashantArticle: 50308
I beleive the LUT configuration bits are transferred from a shift register in once
clock cycle during configuration. As far as the user is concerned, it is 16
flip-flops with a 16:1 selector (mux) on the Q's. A write decode (demux) selects
which flip-flop gets written when the LUT is operated in ram mode, or data can be
shifted through in SRL16 mode or just left static if in LUT mode.
Kuan Zhou wrote:
> Hi,
> But when you initialize the LUTs,you need 4:16 demux to select the RAM
> and write 1 or 0 inside.
>
> sincerely
> -------------
> Kuan Zhou
> ECSE department
>
> On Sun, 8 Dec 2002, Nicholas C. Weaver wrote:
>
> > In article <Pine.SOL.3.96.1021208114534.15707A-100000@vcmr-86.server.rpi.edu>,
> > Kuan Zhou <zhouk@rpi.edu> wrote:
> > >Hi,
> > > I think it's a 1:16 demux,but not a 16:1 mux.
> >
> > 16-1 mux, it selects 1 bit out of 16 SRAM cells.
> > --
> > Nicholas C. Weaver nweaver@cs.berkeley.edu
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50309Hi, Do you have detailed architecture of LUT implementation?Where can I find detailed description? Do you mean all the D fli flops in the LUT are connected serially? Otherwise you can't implement the shifters in LUT. sincerely ------------- Kuan Zhou ECSE department On Sun, 8 Dec 2002, Ray Andraka wrote: > I beleive the LUT configuration bits are transferred from a shift register in once > clock cycle during configuration. As far as the user is concerned, it is 16 > flip-flops with a 16:1 selector (mux) on the Q's. A write decode (demux) selects > which flip-flop gets written when the LUT is operated in ram mode, or data can be > shifted through in SRL16 mode or just left static if in LUT mode. > > Kuan Zhou wrote: > > > Hi, > > But when you initialize the LUTs,you need 4:16 demux to select the RAM > > and write 1 or 0 inside. > > > > sincerely > > ------------- > > Kuan Zhou > > ECSE department > > > > On Sun, 8 Dec 2002, Nicholas C. Weaver wrote: > > > > > In article <Pine.SOL.3.96.1021208114534.15707A-100000@vcmr-86.server.rpi.edu>, > > > Kuan Zhou <zhouk@rpi.edu> wrote: > > > >Hi, > > > > I think it's a 1:16 demux,but not a 16:1 mux. > > > > > > 16-1 mux, it selects 1 bit out of 16 SRAM cells. > > > -- > > > Nicholas C. Weaver nweaver@cs.berkeley.edu > > > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > > >Article: 50310
siriuswmx wrote: > Hi, everyone, > Must i turn to symbol entry window to assign the pins? > thanks a lot! You can assign pin in the VHDL via attributes, but this is not a good idea. YOUR VHDL MUST STAY GENERIC Laurent Gauch, AmontecArticle: 50311
Hi, To use an FPGA's DLL do you need to feed the DLL pin with an external signal or can you use an internal signal to feed the DLL? cheers, Jamie MorkenArticle: 50312
Hi, > As Ray explains in his comment, a better solution is an analog PLL with > divider, in a separate component. Unless you are constrained by power Could you recommend a PLL part that would be good for this? > issues, you can also feed the ADC with 120 MHz, and do a digital down > conversion in the FPGA. I like this solution the best I think. But if the sampling rate on the ADC goes up so does the sampling noise doesn't it? cheers, JamieArticle: 50313
In article <Pine.SOL.3.96.1021208163814.20942B-100000@vcmr-86.server.rpi.edu>, Kuan Zhou <zhouk@rpi.edu> wrote: >Hi, > Do you have detailed architecture of LUT implementation?Where can I >find detailed description? > Do you mean all the D fli flops in the LUT are connected serially? >Otherwise you can't implement the shifters in LUT. There really isn't that much interesting. There is a 16-1 mux for SRAM cells for the output, a 1-16 demux for the write select line when used in RAM mode, and my guess is the 16 SRAM cells are connected as a 2-phase shift chain for SRL16 mode using pulse generators for the clocking. If you want INTERESTING FPGA circuits, look at the interconnect. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 50314
Most fpga's require a special voltages not used by any other component on the board. You can often measure the fpga current by inserting a current viewing resistor on the input side of the switching or linear regulator. The regulator will compensate for any voltage drop accross the viewing resistor so the circuit will still operate. In the case of the switching regulator you have to account for the inefficiency of the regulator. Linear regulators pass virtually all the input current to the load. -- Pete Dudley Arroyo Grande Systems "Kolin Paul" <kolin@cs.colostate.edu> wrote in message news:3DEE573F.5020001@cs.colostate.edu... > Hi, > > I want to measure the actual power in a FPGA Board. > Any Ideas on how to do it. > > Kolin >Article: 50315
I'm scheming about building a hobby/hack project that needs an FPGA on a PCI card. Volumes will be very low. My straw man is Spartan-II. Even with a big one, the cost of the PCB will be more than the cost of the FPGA. Is it reasonable to get away with only 4 layers? I'm thinking of using a PQ208, dedicated layers for 3.3V and GND, and filling the top layer inside the pad ring with copper for the 2.5V core power "plane". I think everything else on the board will run at 3.3V, or I can fudge it. There won't be much routing so if the PCI works, I should be able to get away with 2 signal layers. Does that seem reasonable? Is there a better approach I've missed? I'm still keeping an eye open for an existing prototype board that I can adapt to what I need, but I haven't seen one that looks close yet. If I have to build a daughter card to plug into an existing card, I might as well do the whole thing and get exactly what I want. Did 3V PCI ever take off? Can I get PC motherboards and/or a reasonable collection of plug in cards? That would allow using a Spartan-IIE (Virtex) with DLLs. I'm assuming it flopped since I don't remember seeing ads for mother boards nor do I remember seeing cards that had the second slot. I'm assuming lots of people would build them if there was any interest. Do people who want to use 3V PCI just use a PCI-PCI bridge chip? Or another FPGA? Anybody have a list of PCI-some-simple-bus type chips? I'm only interested in ones that are cheap and reasonably available in small quantities. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50316
Hello, I'm (sadly) not an EE type, but I need to confirm something and was hoping someone here could help. I have a polynomial 1 + x^3 + x^4 and an initial vector(z0=1;z1=0;z2=0;z3=0) that characterize an LFSR based stream cipher. I am trying to determine the feedback coefficients, and to do this, I computed the values of z4, z5, z6 and z7 from the LFSR as 0,0,0 and 1 respectively. However, attemepting to find the feedback coefficients doesn't work because somewhere along the line, I end up with a singular matrix - so I have to assume I did something wrong is calculating the values above. Does anyone see where I am messing up? I've checked and rechecked ..Article: 50317
Hello all, I am building an oscillator in a Cypress 37128 device which is the standard inverter parallel resonant circuit. I have done this dozens of times in other programmable logic devices, as well as discrete gates. The frequency of operation is 32.768kHz. I have a 1 Megohm resistor across the crystal to start it up, standard load capacitors yielding the required 12.5 pF load, and a resistor in series with the crystal to limit the power. This resistor, in a previous job required >>> 100k <<<< which was high in my experience. I have experimented with this resistor and the startup one, but cannot get the oscillator to go. I have tried 0 to 100 K for the series resistor. Does anyone here have experience with a Pierce oscillator at this frequency in this device? I did not expect this problem at all.... or I would have designed in a discrete transistor oscillator that I know works. ClydeArticle: 50318
I don't know what synthesis tool you are using, or if it matters, (I am using Synplicity) but I got around this using a constraint in the .UCF file that ties the net to "uselowskewlines". In the Spartan IIE there are 24 dedicated lines for this purpose, if I remember correctly. Xilinx apps folk were really really vague on how to do this. I stumbled across this and it worked for me. What does this group think about this? I hope this helps you. Clyde Igor Orlovich wrote: > A bit offtopic: if I have a clock coming into Spartan IIE clock network, and > I need to feed it to an IO pin, > doing something like: io_pin<=clock_pin; > causes Mapper error saying I am trying to connect clock_pin and > clock_pin_ibuf. > What's the correct way? > > Thanks! > > Hal Murray wrote: > > >>I have a 120MHz clock being fed into a global clock pin and would like to > >>be able to send this clock to an ADC on my board using the DLL for more > >>clocking options. > > > > I think you want to consider that carefully. > > > > DLLs add jitter. That's generally bad when ADCs are involved. > > > > There was a lot of discussion about this here a while ago. > > Google-groups might be interesting. > >Article: 50319
Hi, Obviously hierarchy is essential when building and managing any large design. But I'm curious how synthesis tools use hierarchy during the optimization process? Just how critical is hierarchical partitioning of a design for quality synthesis? I remember talking to a Mentor rep a few years ago. At the time he said the major advantage of Leonardo over Synplicity was Leo's use of design hierarchy compared to Synplify which just optimizes a flattened design. If this was true, is it still the case? Just in terms of synthesis, is hierarchy and partioning important or not? Thanks, TomArticle: 50320
Steve wrote:
> Hello,
> I'm (sadly) not an EE type,
There's still hope since, you found this newsgroup.
> but I need to confirm something and was hoping
> someone here could help.
>
> I have a polynomial 1 + x^3 + x^4 and an initial vector(z0=1;z1=0;z2=0;z3=0)
> that characterize an LFSR based stream cipher.
>
> I am trying to determine the feedback coefficients, and to do this, I
> computed the values of z4, z5, z6 and z7 from the LFSR as 0,0,0 and 1
> respectively.
> However, attemepting to find the feedback coefficients doesn't work because
> somewhere along the line, I end up with a singular matrix - so I have to
> assume I did something wrong is calculating the values above.
I wouldn't know a singular matrix if it bit my ankle,
but I do know that a lfsr with a poly of 1 + x^3 + x^4
is four bits long:
x3 x2 x1 x0
with an inversion mask of
1 0 0 1
applied when the data in or x3 is 1(but not both)
Maybe these are your "feedback coefficients"
so if we start with all zeros,
0 0 0 0 = init
and shift in a 1 (from the right end) we get
0 0 0 1 now invert the x3 and x0 mask locations
1 0 0 0 = first shift result
because the data but not x3
was active at the start
if we shift in another 1 we would get
0 0 0 1 = second shift result
-- just an plain shift (no inversion) because
both x3 and data were active at the start.
Repeat this process for each data bit,
and what remains is the remainder.
Hope the next one is an odd numbered problem.
-- Mike Treseler
Article: 50321Hi you can try for "IC Station" from Mentor Graphics. You can check Parasitic Extraction also using this tool. Sanjay Patil "transformer" <compresstransform2002@hotmail.com> wrote in message news:4a96bae1.0212081216.60ca70bf@posting.google.com... > Dear All, > I have completed my work on a radix-4 booth multiplier. Now I have to > complete its vlsi layout. Unfortunately, I have only some vhdl > knowledge and completely new to vlsi design. Which free or low-priced > vhdl design software is suitable for my needs. > ThanksArticle: 50322
Hi, Do you want to write the code yourself? or do you want to generate the code base on your vlsi design? If you just want the former, I have a software VHDLmg developed by my university which is free of charge. There is a tutorial for you to learn also. Basically, you create the module in the software and it will generate the vhdl code for you itself. Mail me if you want the software and we can arrange something about it. rgds KEv "Sanjay Patil" <sanjay@cg-coreel.com> wrote in message news:at13oa$vkiv4$1@ID-164436.news.dfncis.de... > Hi > you can try for "IC Station" from Mentor Graphics. > You can check Parasitic Extraction also using this tool. > > Sanjay Patil > > "transformer" <compresstransform2002@hotmail.com> wrote in message > news:4a96bae1.0212081216.60ca70bf@posting.google.com... > > Dear All, > > I have completed my work on a radix-4 booth multiplier. Now I have to > > complete its vlsi layout. Unfortunately, I have only some vhdl > > knowledge and completely new to vlsi design. Which free or low-priced > > vhdl design software is suitable for my needs. > > Thanks > >Article: 50323
I hope you haven't been doing this in production designs. The inverter used
in the Pierce oscillator is used as a gain stage by biasing it to the linear
region, which works fine for simple inverters (in fact when doing this with
7404's you should use the Hcu7404, which is unbuffered). The problem with
doing this with programmable logic is that you no longer have a simple
inverter, rather you have a series of several buffer or inverter stages.
Unfortunately with the cascaded stages the linear region becomes very device
dependent, will generally shift considerably over process, temp and voltage
if it exists at all. While you can probably get such a circuit working in
the lab, making it reliable over a production run is not easy nor very
likely. Having to tweak the series resistor should be a red flag. Do
yourself a favor and either use an unbuffered inverter (eg, your discrete
transistor circuit) or use a packaged crystal oscillator.
"Clyde R. Shappee" wrote:
> Hello all,
>
> I am building an oscillator in a Cypress 37128 device which is the
> standard inverter parallel resonant circuit. I have done this dozens of
> times in other programmable logic devices, as well as discrete gates.
>
> The frequency of operation is 32.768kHz.
>
> I have a 1 Megohm resistor across the crystal to start it up, standard
> load capacitors yielding the required 12.5 pF load, and a resistor in
> series with the crystal to limit the power. This resistor, in a
> previous job required >>> 100k <<<< which was high in my experience. I
> have experimented with this resistor and the startup one, but cannot get
> the oscillator to go. I have tried 0 to 100 K for the series resistor.
>
> Does anyone here have experience with a Pierce oscillator at this
> frequency in this device? I did not expect this problem at all.... or I
> would have designed in a discrete transistor oscillator that I know
> works.
>
> Clyde
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50324On Sun, 08 Dec 2002 19:44:14 -0800, Mike Treseler <tres@fluke.com> wrote: >Steve wrote: > >> Hello, >> I'm (sadly) not an EE type, > > >There's still hope since, you found this newsgroup. > >> but I need to confirm something and was hoping >> someone here could help. >> >> I have a polynomial 1 + x^3 + x^4 and an initial vector(z0=1;z1=0;z2=0;z3=0) >> that characterize an LFSR based stream cipher. >> >> I am trying to determine the feedback coefficients, and to do this, I >> computed the values of z4, z5, z6 and z7 from the LFSR as 0,0,0 and 1 >> respectively. >> However, attemepting to find the feedback coefficients doesn't work because >> somewhere along the line, I end up with a singular matrix - so I have to >> assume I did something wrong is calculating the values above. > > >I wouldn't know a singular matrix if it bit my ankle, >but I do know that a lfsr with a poly of 1 + x^3 + x^4 >is four bits long: > > x3 x2 x1 x0 > with an inversion mask of > 1 0 0 1 > applied when the data in or x3 is 1(but not both) > Maybe these are your "feedback coefficients" > > so if we start with all zeros, > 0 0 0 0 = init > and shift in a 1 (from the right end) we get > 0 0 0 1 now invert the x3 and x0 mask locations > 1 0 0 0 = first shift result > because the data but not x3 > was active at the start > if we shift in another 1 we would get > 0 0 0 1 = second shift result > -- just an plain shift (no inversion) because > both x3 and data were active at the start. > > Repeat this process for each data bit, > and what remains is the remainder. > >Hope the next one is an odd numbered problem. > > > -- Mike Treseler This tool: http://www.logiccell.com/~jean/LFSR/ can be used to visualise the hardware and the generated sequence. Importantly, it allows conversion between the Galois and Fibonacci forms of an LFSR. Regards, Allan.
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