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Oh dear, There are to choices: Leave the FPGA output unterminated (driving full speed/power) and put a termination resistor in the middle. This works fine as long as the traces are short and the capacitive load is not that much. Or: Use impedance matching at the FPGA and put serial termination resistors close to the RAMs. I guess I saw an application note at Micron Technology http://www.micron.com Regards Thomas Peter Alfke wrote: > Interesting problem. > Here is a half-answer and half-promise: > You can use series termination with DCI as the FPGA driver, and then ( > strange idea! ) keep the FPGA output active ( High or Low) while > receiving data from the DRAM. That gives you a brute-force parallel > input termination to Vcc or to ground (your choice by manipulating the > FPGA Dout line). > The problem is that you may end up with poor receive logic levels, > depending on the DRAM output impedance and the FPGA I/O standard. The > promise is that we are working on configuration standards to solve that > issue... > DCI looks better every day. > Peter Alfke, Xilinx Applications > > jakab tanko wrote: > > > Hi Andy, > > > > This solves one half of my problem; if virtex2 drives the > > bidirectional line then DCI will probably work, what about the DRAM > > driving the same line (not the same time, of course). There is no > > built in series resistor in the DRAM !? > > --- > > jakab > > Andreas Schweizer <aschweiz@iiic.ethz.ch> wrote in message > > news:3e1458fc@core.inf.ethz.ch... > > > Hi Jakab, > > > > > > also a happy new year to you! > > > > > > > a Xilinx Virtex2 on one end and a DRAM on the other, > > > > > > These have built-in "resistors". You can configure the IO's as > > > DCI (digitally controlled impedance) and provide two reference > > > resistors per IO bank (VRN, VRP). > > > If you instantiate the correct IO buffers in your code, > > > probably LVDCI or LVDCI_DV2 (the former with 50 Ohm reference > > > resistors, the latter with 100 Ohm), the virtex-ii automatically > > > matches the impedance. > > > > > > HTH, > > > Andy > > > > > >Article: 51152
You may want to take a look at Advin, http://www.advin.com/ . I have had good results with a Pilot U40 that I bought when I was programming Pals & Gals. The software updates are free. Daniel Lang "Dave" <dfnr2@yahoo.com> wrote in message news:m34r8yao2s.fsf@yahoo.com... > Hello, > > I'm thinking of letting my Data I/O coast on without further software > updates, and put the money into a new BP programmer. I'm frustrated > by the lack of pricing information on the BP website, or any > distributors' sites. Would anyone who recently bought a BP-1200 care > to post some prices for the 1200, any of the extra modules, any > upgrades, and the software upgrade to generate serial numbers. > > Also, is it possible to write your own little program to generate > serial numbers, and have the free BP software call it, or do you still > have to pay for an "advanced features" package? > > It would be great if some kind soul posted some info here; > alternatively, I'd be grateful for a scanned pricelist by email. I've > contacted the local rep, but since there's no reply, I assume he's on > vacation. > > Thanks for any info, > > David. > -- > dave - dfnr2@yahoo.com >Article: 51153
I have a v2pro design under 5.1i sp3 including a fifo with a block ram directly instantiated in it (not inferred). The data outputs of the fifo drive a somewhat heavily loaded bus. It looks like XST is adding extra rams to the fifo during synthesis, which is causing our compile runs to fail, as the extra 8 rams it infers puts us over the limit of our part. Strangely XST is quiet about this replication in it's log file - I see no mention of it. We use this module in another design with less loading and see no replication. After looking in the xst log file, next I tried to look at the schematics generated by xst's rtlview keyword, but it doesn't seem to show replicated logic. We finally discovered it by pulling up good ol' chip editor un the unrouted design and listing all of the block rams. I wish we still had edif (or some text netlist) out... Viewing schematics that don't reflect reality is really annoying. As for a fix I could add a f/f stage after the fifo, but I don't want to add the gates and add another cycle of latency and more complexity to the control state machine. I tried adding a line like this: // synthesis attribute REGISTER_DUPLICATION of u_ram is NO to the code, but it seems to have no effect. Anybody seen this? Anyone know a fix? Please reply to (remove the dashes) a-d-y-e-r@enteract.comArticle: 51154
Hi all,
Anyone out there who knows what's the meaning of this error?
Error: F:/Floating Point Unit/wallace_4_2_comp.vhd line 66
Signal or port name expected as actual in association element. (VSS-806)
Error: F:/Floating Point Unit/wallace_4_2_comp.vhd line 69
Signal or port name expected as actual in association element. (VSS-806)
Error: F:/Floating Point Unit/wallace_4_2_comp.vhd line 72
Signal or port name expected as actual in association element. (VSS-806)
Error: F:/Floating Point Unit/wallace_4_2_comp.vhd line 92
Signal or port name expected as actual in association element. (VSS-806)
Error: F:/Floating Point Unit/wallace_4_2_comp.vhd line 95
Signal or port name expected as actual in association element. (VSS-806)
Error: F:/Floating Point Unit/wallace_4_2_comp.vhd line 98
Signal or port name expected as actual in association element. (VSS-806)
Error: F:/Floating Point Unit/wallace_4_2_comp.vhd line 101
Signal or port name expected as actual in association element. (VSS-806)
Error: F:/Floating Point Unit/wallace_4_2_comp.vhd line 104
Signal or port name expected as actual in association element. (VSS-806)
Error: F:/Floating Point Unit/wallace_4_2_comp.vhd line 107
Signal or port name expected as actual in association element. (VSS-806)
Error: F:/Floating Point Unit/wallace_4_2_comp.vhd line 110
Signal or port name expected as actual in association element. (VSS-806)
Error: F:/Floating Point Unit/wallace_4_2_comp.vhd line 113
Signal or port name expected as actual in association element. (VSS-806)
My source code is :
-- wallace_4_2_comp
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity wallace_4_2_comp is
port (
pp_0 : in BIT_VECTOR(25 downto 0);
pp_1 : in BIT_VECTOR(28 downto 3);
pp_2 : in BIT_VECTOR(31 downto 6);
pp_3 : in BIT_VECTOR(34 downto 9);
pp_4 : in BIT_VECTOR(37 downto 12);
pp_5 : in BIT_VECTOR(40 downto 15);
pp_6 : in BIT_VECTOR(43 downto 18);
pp_7 : in BIT_VECTOR(46 downto 21);
pp_8 : in BIT_VECTOR(49 downto 24);
neg : in BIT_VECTOR(8 downto 0);
wsuma : out BIT_VECTOR(49 downto 0);
wcarrya : out BIT_VECTOR(50 downto 1)
);
end wallace_4_2_comp;
architecture wallace_4_2_comp_arch of wallace_4_2_comp is
signal coi:BIT_VECTOR(49 downto 6);
signal negnot:BIT_VECTOR(8 downto 0);
-- VHDL Module Generator component declarations
component comp_4_2
port (
a : in BIT;
b : in BIT;
c : in BIT;
d : in BIT;
cin : in BIT;
cout : out BIT;
sum : out BIT;
carry : out BIT
);
end component;
begin
--First part of compressor
process(pp_0,neg,pp_1)
variable temp:BIT;
variable notneg:BIT_VECTOR(8 downto 0);
begin
for i in 0 to 8 loop
notneg(i):='1' xor neg(i);
end loop;
negnot<=notneg;
wsuma(0)<=neg(0)xor pp_0(0);
wcarrya(1)<=neg(0)and pp_0(0);
wsuma(1)<=pp_0(1);
wsuma(2)<=pp_0(2);
temp:=neg(1)xor pp_0(3);
wsuma(3)<=temp xor pp_1(3);
wcarrya(4)<=(neg(1) and pp_0(3))or(temp and pp_1(3));
wsuma(4)<=pp_0(4) xor pp_1(4);
wcarrya(5)<=pp_0(4)and pp_1(4);
wsuma(5)<=pp_0(5) xor pp_1(5);
wcarrya(6)<=pp_0(5) and pp_1(5);
end process;
cp6: comp_4_2 --the error occurs here
port map (pp_0(6), pp_1(6), pp_2(6), neg(2), '0', coi(6), wsuma(6),
wcarrya(7));
cp7: comp_4_2 --and also here and the rest of the components instantiation
port map (pp_0(7), pp_1(7), pp_2(7), '0', coi(6), coi(7), wsuma(7),
wcarrya(8));
cp8: comp_4_2
port map (pp_0(8), pp_1(8), pp_2(8), '0', coi(7), coi(8), wsuma(8),
wcarrya(9));
cp_9_25: for i in 9 to 25 generate
cp : comp_4_2 port map (pp_0(i), pp_1(i), pp_2(i), pp_3(i), coi(i-1),
coi(i), wsuma(i), wcarrya(i+1));
end generate;
cp26: comp_4_2
port map (neg(0), pp_1(26), pp_2(26), pp_3(26), coi(25), coi(26),
wsuma(26), wcarrya(27));
cp27: comp_4_2
port map (neg(0), pp_1(27), pp_2(27), pp_3(27), coi(26), coi(27),
wsuma(27), wcarrya(28));
cp28: comp_4_2
port map (neg(0), pp_1(28), pp_2(28), pp_3(28), coi(27), coi(28),
wsuma(28), wcarrya(29));
cp29: comp_4_2
port map (negnot(0), negnot(1), pp_2(29), pp_3(29), coi(28), coi(29),
wsuma(29), wcarrya(30));
cp30: comp_4_2
port map ('0', '1', pp_2(30), pp_3(30), coi(29), coi(30), wsuma(30),
wcarrya(31));
cp31: comp_4_2
port map ('0', '1', pp_2(31), pp_3(31), coi(30), coi(31), wsuma(31),
wcarrya(32));
cp32 : comp_4_2
port map ('0', '0', negnot(2), pp_3(32), coi(31), coi(32), wsuma(32),
wcarrya(33));
cp33 : comp_4_2
port map ('0', '0', '1', pp_3(33), coi(32), coi(33), wsuma(33),
wsuma(34));
cp34: comp_4_2
port map ('0', '0', '1', pp_3(34), coi(33), coi(34), wsuma(34),
wcarrya(35));
cp35: comp_4_2
port map ('0', '0', '0', negnot(3), coi(34), coi(35), wsuma(35),
wcarrya(36));
cp36: comp_4_2
port map ('0', '0', '0', '1', coi(35), coi(36), wsuma(36), wcarrya(37));
cp37: comp_4_2
port map ('0', '0', '0', '1', coi(36), coi(37), wsuma(37), wcarrya(38));
--Second part of compressor
-- Enter concurrent statements here
end wallace_4_2_comp_arch;
Article: 51155Hi Kate, Thank you very much for letting me know a feature which I have overlooked. XFLOW is not exactly something what I originally wanted. But surely it does the job. I will investigate further. BTW, I also thank you for giving me the pointer to the documentation, 'Development System Reference Guide' (dev.pdf). I found the documentation very useful. Thanks! Aki Niimura Kate Kelley <kate.kelley@xilinx.com> wrote in message > Aki, > > Check out XFLOW. > > http://toolbox.xilinx.com/docsan/xilinx5/pdf/docs/dev/dev.pdf > > Chapter 22. > > XFLOW is a command line tool similar to makefiles. It might be what > you want to do. > > KateArticle: 51156
Peter Alfke wrote: > > On a more sophisticated level, you can also use partial reconfiguration > to modify the logic functionality ( not just the data) in one part of the > FPGA, as determined by results from another ( or even the same) part of > the device. This can get quite esoteric... > This reminded me of a paragraph in Wirth's book "Algorithms + Data structures = Programs". I haven't the english version at hand, but in my version the paragraph is in section 5.6, right before Program 5.3, while explaining table-driven syntactic analysis. Wirth talks about the flexibility of table-driven analysis, which is able not only to translate a piece of code to its parsing tree, but also may be used for extendible languages: languages that allow modifying the language itself while analyzing code. Right after that, Wirth remarks that the idea wasn't too successful, because of semantics. Machine code must be finally generated, and including the semantic description of the <newly added language features> is difficult to formalize. Perhaps Wirth could have used an FPGA block library to formalize the semantic description... :-) Ahead of time -javierArticle: 51157
Hello. I am running into some weird timing skews on my clock signals in my post-route simulation. I believe that my clock signals are not on the clock nets. I am using a Virtex2, with Synplify 7.2, and Xilins ISE 4.2 SP3. Is there any way to tell if my clock signal is on the clock net or not? chris wangArticle: 51158
> I work on an altera MAX7000 & MAX+PLUS II. I want to use a D latch > sensitive to falling edge for clock & rising edge for reset. For the > clock it is not a problem but I don't find any lacth which is not > sensitive to level on reset pin. > > It can be made in VHDL but i don't have the license. Is it possible to > do it in an other way ? That coding paradigm used that makes latches or flops look sensitive to a reset "edge" is a hack in the languages to make asynchronous resets work, without actually handling it properly in the language. BTW they just appear to "work" - none of the simulators can actually model an asynchronous reset or set properly. So in answer, it only LOOKS like it can be done in VHDL. You need a flop with two clocks. Some libraries have them, but I guess the one you're using doesn't. If you can't get around absolutely needing this capability, you'll probably have to design an Asynchronous FSM to get it. You should be able to get a textbook that outlines the procedure. It's been about 15 years since I've done one and have more or less forgotton. Try a Web search. -StanArticle: 51159
Hi! I am new to Dynamic reconfigurable FPGAs, can anyone send me links that would clearly explain this concept with a suitable application. Thank you, Sumanth DonthiArticle: 51160
Peter Alfke wrote: > > rickman wrote: > > > However if they use an internal control for direction in > > the same way a tristate control works, then they can switch the > > resistance to match in both cases. > > > > Is this what Xilinx is thinking about doing? > > Yes, but it's even simpler. The resistance is not even switched around, and the > output is not 3-stated. It's just made active Low (or High). Intriguingly > simple. :-) > Peter Alfke I understand the simplicity. I was not suggesting that you tristate the output. I was suggesting that you use a control to switch the resistance between the input and output. If you don't change the resistance you have a poor compromise for the resistor value. As I said in the other post, the series resistance is set to a value equal to the trace impedance minus the output impedance of the driver. A parallel impedance is set equal to the trace impedance. Unless your output driver has an inherent output impedance that is near zero, the method you suggest will result in a poor match to one, the other or both resistors. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51161
Hi Peter! I'm very interested in partial reconfiguration, but I've always found few documentation about it, and above all, it seemed to me that there are very few parts that can implement it explicitly, is it true?!? Common FPGAs like the Xilinx Spartan2 can implement it too in some way? And if yes, how? (e.g. which software tools are needed?) Thank you in advance for your answer! Stevenson Peter Alfke <peter@xilinx.com> wrote in message 3E160A0B.6AFCAEBA@xilinx.com... > Yes, absolutely true. > But it needs an external piece of logic to maintain the control, since the > FPGA is "dead" during the whole reconfiguration process. That's not the fact > during partial reconfiguration, but it may require real finesse to take > advantage of that. > > Peter Alfke > ================== > Mike Treseler wrote: > > > Peter Alfke wrote: > > > > > On a more sophisticated level, you can also use partial reconfiguration > > > to modify the logic functionality ( not just the data) in one part of the > > > FPGA, as determined by results from another ( or even the same) part of > > > the device. This can get quite esoteric... > > > > In cases where your pcb has the flash and firmware to load > > the FPGA, you can keep multiple configurations > > in flash available to downloade in response to > > a system mode change. > > > > -- Mike Treseler >Article: 51162
Hi, Does anyone has experinces or know some tricky points on designing with hdmp-1032/34 gigabit Tx/Rx ICs? I want to design a card with them. Please let me know what you know. Best regards MasoudArticle: 51163
Hello All, I'm working on a rather trivial project for myself to help me get further acquainted with FPGAs and VHDL in particular (No I'm not a student, I'm educating myself, or trying to). I'm attempting to build a voltmeter. I'm using an ADC tied to the FPGA and then eventually I want to output the reading on a LCD display also tied to the FPGA. I'm a little bit confused as to the steps needed to get from one end to the other. Firstly my values coming from the ADC are binary values, so I have to convert them to an integer (I'm assuming) then I have to do some multiplication and division to get my final result which will be a fixed point number (again an assumption but I want at least one decimal place for accuracy). Then this value must be converted somehow so that I can send it to the LCD. I understand a BCD to hex converter for the display, but how does one convert say a 16 bit fixed point number to a unit that can be displayed. I would appreciate any pointers or useful links that may help me discover all of the steps required to do this. I know that there are ICs to do this already out there, but that isn't any fun, and they won't help me learn anything. Thanks for the help (in advance) JasonArticle: 51164
Sumanth Donthi wrote: > Hi! > > I am new to Dynamic reconfigurable FPGAs, can anyone send me links > that would clearly explain this concept with a suitable application. Some families of programmable logic is RAM based and therefore allows being reloaded when necessary. The manufacturers websites contain application notes. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 51165
Actually not so trivial a project on an FPGA, much simpler with a micro. You need to do arithmetic, you have plenty of time (FPGA's are very fast compared with the human reader), so you do everything with a serial (one bit at a time) adder/subtracter. It is possible to do everything with parallel logic of course, but that would require quite a lot of (FPGA) resources, besides being rather less fun. Multiplication is just repeated addition, division is repeated subtraction. To convert binary to decimal for the output, you divide by ten, the remainder (in the range 0 to 9) is the least significant digit. Now divide the quotient by ten, the new remainder is the next most significant digit, and so on. Dave "Jason Berringer" <jberringer@trace-logic.com.delete> wrote in message news:ptIR9.16736$VW5.1466136@news20.bellglobal.com... > Hello All, > > I'm working on a rather trivial project for myself to help me get further > acquainted with FPGAs and VHDL in particular (No I'm not a student, I'm > educating myself, or trying to). > > I'm attempting to build a voltmeter. I'm using an ADC tied to the FPGA and > then eventually I want to output the reading on a LCD display also tied to > the FPGA. I'm a little bit confused as to the steps needed to get from one > end to the other. Firstly my values coming from the ADC are binary values, > so I have to convert them to an integer (I'm assuming) then I have to do > some multiplication and division to get my final result which will be a > fixed point number (again an assumption but I want at least one decimal > place for accuracy). Then this value must be converted somehow so that I can > send it to the LCD. I understand a BCD to hex converter for the display, but > how does one convert say a 16 bit fixed point number to a unit that can be > displayed. > > I would appreciate any pointers or useful links that may help me discover > all of the steps required to do this. I know that there are ICs to do this > already out there, but that isn't any fun, and they won't help me learn > anything. > > Thanks for the help (in advance) > > Jason > >Article: 51166
chris wrote: > > Hello. > I am running into some weird timing skews on my clock signals in my > post-route simulation. I believe that my clock signals are not on the clock > nets. I am using a Virtex2, with Synplify 7.2, and Xilins ISE 4.2 SP3. Is > there any way to tell if my clock signal is on the clock net or not? > chris wang Run a static timing. TRCE -v 100 -u 100 your_design_name. Then look carefully at the resulting timing report. Make sure that all timings you care about are specified, and that you understand what you see. If you have HDL Analyst on Synplify, look at the "technology view" schematic. FPGA editor. -- Phil HaysArticle: 51167
Hello All, Every time i try to place and rote my design, I get this error: ERROR:Place:106 - Could not find an automatic placement for the following components: clkp of type GCLK IOB is unplaced. initilization_dll0 of type DLL is placed at DLL2. initilization_dll1 of type DLL is placed at DLL1. initilization_bufg2 of type GCLK BUFFER is placed at GCLKBUF2. initilization_bufg1 of type GCLK BUFFER is placed at GCLKBUF0. initilization_bufg0 of type GCLK BUFFER is placed at GCLKBUF1. ERROR:Place:107 - Xilinx requires using locate constraints to preplace such connected GCLK/GCLKIO/DLL components. Any one knows the solution? TalalArticle: 51168
"chris" <cjwang@notmyemail.net> wrote in message news:<av6g1p$lif$2@news01cd.so-net.ne.jp>... > Hello. > I am running into some weird timing skews on my clock signals in my > post-route simulation. I believe that my clock signals are not on the clock > nets. I am using a Virtex2, with Synplify 7.2, and Xilins ISE 4.2 SP3. Is > there any way to tell if my clock signal is on the clock net or not? > chris wang Did you gate the Clock?, if you did, you likely got a routed clock net. If you didn't, you shouldn't be seeing any routed clock nets. High speed clocks can't be gated on the wire since they are usually driven by PLL/DLL and distributed low skew buffers. If you really needed to gate the clock, use a hold mux instead.Article: 51169
rickman wrote: > I understand the simplicity. I was not suggesting that you tristate the > output. I was suggesting that you use a control to switch the > resistance between the input and output. If you don't change the > resistance you have a poor compromise for the resistor value. > > As I said in the other post, the series resistance is set to a value > equal to the trace impedance minus the output impedance of the driver. > A parallel impedance is set equal to the trace impedance. Unless your > output driver has an inherent output impedance that is near zero, the > method you suggest will result in a poor match to one, the other or both > resistors. Rick, I have to correct you: When you use DCI (digitally controlled impedance), the output impedance is exactly the way you program it. It is NOT the sum of two impedances or resistors. The output transistor ( the one pulling High as well as the other one pulling Low) are controlled to each have the appropriate resistance (whenever each one is activated), and the user should make that equal to the characteristic impedance of the line. Now you see that we have perfect series termination, and also perfect parallel termination. The beauty of a servo-controlled internally-defined output impedance... :-) Peter Alfke, Xilinx ApplicationsArticle: 51170
All so-called "SRAM-based" FPGA (mainly offered by Xilinx and Altera) must be configured by loading a bitstream ( or bytestream) into the device, and they can then be reconfigured with a different stream, as often as you want. The configuration takes milliseconds to seconds, and during the (re)configuration the device is not usable, i.e its outputs are 3-stated. The newer Xilinx devices go one step further, they allow partial reconfiguration, where part of the existing configuration is retained. Obviously faster, and avoiding the potential data loss in the preserved part of the device. Peter Alfke, Xilinx Applications =================================== Sumanth Donthi wrote: > Hi! > > I am new to Dynamic reconfigurable FPGAs, can anyone send me links > that would clearly explain this concept with a suitable application. > > Thank you, > Sumanth DonthiArticle: 51171
"chris" <cjwang@notmyemail.net> wrote in message news:av6g1p$lif$2@news01cd.so-net.ne.jp... > Hello. > I am running into some weird timing skews on my clock signals in my > post-route simulation. I believe that my clock signals are not on the clock > nets. I am using a Virtex2, with Synplify 7.2, and Xilins ISE 4.2 SP3. Is > there any way to tell if my clock signal is on the clock net or not? > chris wang Chris, The sure fire way to determine if your clock signal is actually on a clock net is to look at it using FPGA Editor in the Xilinx tool kit. In Design Mangler, the FPGA Editor icon is a chip looking thing on the right, second from bottom. Find a slice containing a flip flop that is in doubt and click on the net line that comes into its CLK input. Most likely it's the last input on the left of the slice. When you click on the net line, it will turn red. If it is a dedicated clock net, it will go many places and look like a grid. You can actually trace the driver of this grid back to a BUFG. BUFGs (and DLLs) are usually located at the top and bottom middles. If you see this grid-like net driven by a BUFG, then you will know that the "clock signal is on the clock net..." Regards and Happy New Year, Simon Ramirez Synchronous Design, Inc.Article: 51172
hi! How can you determine the reconfiguration time of the Xilinx virtex/virtex E FPGA and atmel AT40K FPGA? Thanks, Sumanth DonthiArticle: 51173
I depends on which version of the chip you have and number of gates and the speed of your programming system and the programming method (serial? select i/o parallel? jtag?). Read the tech notes on programming the chips. A quick example might be the Virtex 300k gate chip, with a config clock of 50 MHz, using SelectMAP programming mode. It can be programmed at up to 50mhz without having to worry about a 'wait i'm processing' signal from the virtex chip. As noted in the tech docs, the bit stream size is IIRC 297860 bytes. Using SelectMAP 8-bit interface you can send over 1 byte per cclk (configuration clock) for a rate of 50 megabytes per second. doing the math 297860 bytes / (50 MBps) = 5.9572 ms. add a few uS before and after to erase and start programming as well as init the device after programming, again these #'s are in the tech doc. Tony "Sumanth Donthi" <thetallman63@yahoo.com> wrote in message news:b43a630c.0301042013.275fc342@posting.google.com... > hi! > > How can you determine the reconfiguration time of the Xilinx > virtex/virtex E FPGA and atmel AT40K FPGA? > > Thanks, > Sumanth DonthiArticle: 51174
Hi Jason! > I'm attempting to build a voltmeter. I'm using an ADC tied to the FPGA and > then eventually I want to output the reading on a LCD display also tied to > the FPGA. I'm a little bit confused as to the steps needed to get from one > end to the other. Firstly my values coming from the ADC are binary values, > so I have to convert them to an integer (I'm assuming) You think like writing a software. The output of the ADC is a parallel/serial word. The word contains bits, that represent some value. You say, that the value is coded binary - fine. Every hardware uses these binary coded words. VHDL gives you the ability to convert the type of your data, but this does not change the representation of the date in hardware. - Example: signal A_sulv : std_ulogic_vector(7 downto 0); -- I assume, this is the output of the ADC - a 8 bit binary coded word. signal A_int : integer range 0 to 255; -- A_int will be the same data, like A_sulv. Now I can convert A_sulv to A_int: A_int <= to_integer( signed(A_sulv) ); The conversion is only for _you_. For hardware there is no difference between A_int and A_sulv. -> Hint: Work always with std_ulogic (better) or std_logic. If you want to do some arithmetic operations (e.g. A+B), convert the data to unsigned, signed, integer or whatever is nessecary and helpful. > I understand a BCD to hex converter for the display, but > how does one convert say a 16 bit fixed point number to a unit that can be > displayed. That depends on your display. How the data should be coded for it? If it accepts BCD, you have to write a binary-to-BCD-converter. (You mentioned, that the result of your operations will be a fixed point number - this means, it can be represented as std_ulogic_vector and should be coded binary.) Ralf
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