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John Larkin <jjlarkin@highSNIPlandTHIStechPLEASEnology.etc> wrote in message news:<ksd42v8a2u6flipga2i698c6uce58dl2a5@4ax.com>... > On Sun, 12 Jan 2003 22:54:13 GMT, Ray Andraka <ray@andraka.com> wrote: > > >IMHO, the way to express a design in VHDL is to first envision the > >schematic for the circuit you are creating, then write the VHDL to produce > >that logic. > > So: schematics allow one to visualize a design, then all you have to > do is hand-compile the schematic to VHDL. > > That leads directly to a wonderful product idea: software that > *automatically* generates VHDL from a schematic! Somebody should start > working on this. [1] > > John > > [1] yes, yes, I know... Surely didn't every schematic package have various HDL output? Last one I used Intergraph/Veribest/goneaway had Verilog, VHDL & couple of others but it was anal, wire by wire, pin by pin and not even always correct. I took a schematic project of 50-100 complex sheets for an 50k gate ASIC & dumped out the Verilog. The schematic when clean "saved as" was a meg or so & easy to read. The Verilog was a few megs or so & useful only for other tools. That Verilog when synthed to 4085 at the time was hopeless, far to many long paths. By the time the design was redone writing clean structural pipelined Verilog, it was 50x smaller code than sch2vlg and easy to read but did the same thing, basically same design. Message here is that if you use a schematic tool with HDL output, it will probably be useless to work with by hand. One tool I have always fancied having but doesn't seem to exist is the auto schematic generators that do exist that allows the auto schematics to be hand edited ie reorganise the placement of symbols by hand ala floor planner (but not the netlist). The tool would essentially use the HDL netlist as half the database and a hand drawn placement schematic as the other half, auto generating it the 1st time. With such a tool, I'd would hand redraw most datapaths & little else to look as much like a floor plan as possible. In another view mode the symbols would be sized relative to their actual estimated area costs, so now its a floor planner too. Best of both worlds, buts thats another project.Article: 51401
Thanks, unfortunately these devices are quite expensive. Are there any cheaper available? Thorsten "Austin Lesea" <austin.lesea@xilinx.com> schrieb im Newsbeitrag news:3E1EED1A.41F109A4@xilinx.com... > Thorsten, > > Virtex II and Virtex II Pro both have the DCM which does exactly that. > > http://www.support.xilinx.com/publications/products/v2pro/handbook/ug012_ug. pdf > > starting on page 71. > > Austin > > Thorsten Bunte wrote: > > > Hello, > > > > is it possible to create a clock (multipled by 4) CLK_B by an internal > > PLL/DLL from an internal clock (creating inside the chip) CLK_A which is > > available on a global clock net and in phase to a data signal. > > > > The new clock must be in phase with the clock on the global net. > > > > Routing CLK_A to an IO pin and feed it into a PLL/DLL will cause an > > unpredictable phase. > > > > Is there a possible in any available FPGA devices? I would prefer Altera or > > Xilinx devices. > > > > Thanks in advance, > > Thorsten >Article: 51402
Celoxica's White Paper on TripleDES describes
typedef rom unsigned 4 SBox[64];
static SBox SBoxes[8] =
{
SBox1, SBox2, SBox3, SBox4,
SBox5, SBox6, SBox7, SBox8
};
How can I initialize the SBox array and what are
SBox1, SBox2, .. ,SBox8?
Any assitance appreciated.
Astonish
Article: 51403Frederic, >I am using a TE-XC2S system. Could you please tell me exactly what >is wrong in the TE-BL documentation? The MODE pin is shown to be >connected to ground. What is exactly the problem and how should it be >solved on FPGA side? nothing is wrong with TE-BL documentation. As Caleb already mentioned, the problem is in TE-XC2Se documentation. > I will use it to implement USB on my Trenz > board and make it available as soon as it works. if you have more questions regarding our board, do not hesitate to contact me directly. Thorsten -- Dipl.-Ing. Thorsten Trenz Trenz Electronic GmbH, Brendel 20, 32257 Buende, Germany Tel.: +49 (0) 5223 41652, Fax.: +49 (0) 5223 48945 Mailto:t.trenz@trenz-electronic.de, http://www.trenz-electronic.de Amtsgericht Bünde, HR B 1747, Geschäftsführer/CEO: Thorsten TrenzArticle: 51404
Hi, I have my design in FPGA. I wish to migrate to a customized ASIC. Could anybody tell me some sites/companies which do this? They should give information about time taken/cost involved etc. regards, Nagaraj CSArticle: 51405
Thorsten Bunte <t.bunte@beckhoff.de> wrote: : Thanks, : unfortunately these devices are quite expensive. Are there any cheaper : available? A XC2V250 ist listed with about 80$. : Thorsten : "Austin Lesea" <austin.lesea@xilinx.com> schrieb im Newsbeitrag : news:3E1EED1A.41F109A4@xilinx.com... Please, no Top Text Bottom Full quotes (TOFU). Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 51406
Give fractional Integer Arithmetic a try. You can do amazing things with it. Or if you like overkill, use some IP for doint floating point numbers in a fpga. Raymund Hofmann "David" <gretzteam@hotmail.com> wrote in message news:WNlU9.9442$sn2.131167@wagner.videotron.net... > Hi > I'm having a hard time figuring out how to implement the coefficient > multiplication in a vhdl dsp design. Let's say every registers are 16 bits > wide in two's complement representation and suppose there are no overflow. > The input data is normalised betwen -1 and 1. How can I implement the > following block diagram in vhdl? How is the *0.1 implemented...I'm really > lost here thanks for any help. > > > x(n)-------------- * 0.1----------- +---------- y(n) > | | > | | > |______z^-1_________| > > > David > >Article: 51408
John Larkin wrote: > On Sun, 12 Jan 2003 22:54:13 GMT, Ray Andraka <ray@andraka.com> > wrote: > >>IMHO, the way to express a design in VHDL is to first envision the >>schematic for the circuit you are creating, then write the VHDL to >>produce that logic. Agreed. A good thing to add is to not only visualize it but to make a sketch of it. It's good for when you (or a reviewer) has to go through the code later. > So: schematics allow one to visualize a design, then all you have > to do is hand-compile the schematic to VHDL. > > That leads directly to a wonderful product idea: software that > *automatically* generates VHDL from a schematic! Somebody should > start working on this. [1] Viewlogic has had for years a program called EXPT1076 [or something similar] that does exactly this. I've used it for a few times for some chips that the tool flows that only accepted VHDL input and I had existing schematics that I wanted to port. -- rk, Just an OldEngineer "A good engineer gets stale very fast if he doesn't keep his hands dirty." -- Wernher von Braun, 1964Article: 51409
My experience: The Altera MySupport is useless, often slow and above all inapropriate in my experience. Looks like it's there just for marketing purposes - to be mentioned as superb on-line support for potential customers. When you (me) need help, usualy you get riduculous short answers that show they don't even try to read your whole message, not to mention answering it thoroughly and exactly. I often find the solution to my problems in this newsgroup (really prompt response!) or on my own before I get any info from MySupport that makes any sense. Regards, Matjaz "Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3E1C4F1E.1BD53CBD@xilinx.com... > Rene, > > Please, do not discourage people from using internet based support tools. > > I can not speak for Altera (obviously), but email and web-based support is > becoming a major means of asking and answering customer questions in a timely > fashion. > > The fact that Altera has someone who watches the comp.arch.fpga forum indicates > that they really do care about customer service, and 'caught' your inquiry in this > forum. > > Our hotline group would prefer that a case gets entered into their system, as they > will answer it quicker that way. But for those that wish to get other opinions, > this newsgroup is also valuable. > > I know that Xilinx takes this all very seriously, and watches response time vs. > how the case is entered to maintain quality of service target levels. > > > > Austin > > Rene Tschaggelar wrote: > > > Thanks for the quick reply. > > Amazingly quicker than the mentioned 'MySupport', > > but then again not - proves my point. > > > > Rene > > > > Subroto Datta wrote: > > > Rene, > > > A fix for this problem is under development. More details about its > > > availability will be posted as soon as the fix is tested and released in the > > > very near future (no later than end of this week). Thanks for bringing this > > > problem to our attention. > > > > > > - Subroto Datta > > > Altera Corporation > > > > > > "Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message > > > news:3E1B4021.2090607@dplanet.ch... > > > > > >>I found a bug in quartus2 Web V2.2. > > >>When tring to place legacy components in schematic editor, > > >>such as the 74165b shiftregister, its connectors are off > > >>grid. This makes it somewhat hard to connect. > > >> > > >>Did anyone figure a workaround ? > > >> > > >>Their support is useless : login(!), place a question, > > >>relogin(!) to get a reply, so I didn't ask there. >Article: 51410
"2Penny" <LW_Rogers@sbcglobal.net> wrote in message news:3E22425C.5000403@sbcglobal.net... > Gentlement: > > I've built a small computer board for a small local college (mostly > from one of the professor's designs and partly from designs in the > book). The machine uses PLDs in several places and I figured I could > simplify the board some (and improve by skills) by (learning about and) > using FPGAs, but I don't know where to get the initial software or > download equipment. > > TIA(Thanks In Advance) > > 2Penny(2cents worth of opinion) which plds did you use? The manufacturers of the plds usually have free software packages that you can download. see the faq for lists of all the manufacturers http://www.optimagic.com/faq.html http://www.optimagic.com/ manufacturers http://www.optimagic.com/companies.html http://www.actel.com/ http://www.atmel.com/ http://www.altera.com/ http://www.lucent.com/micro/fpga http://www.xilinx.com/ lowcost software http://www.optimagic.com/lowcost.shtml AlexArticle: 51411
In article <56147fd4.0301110622.77a47d0@posting.google.com>,
arvind <arvindstomar@india.com> wrote:
>Hi,
> I want a 16mhz clock synchronous to Hsync of the video.I want my 16mhz
>clock should lock on the rising edge of the Hsync.
>I want a pixel clock for Xilinx Spartan 2 Fpga for Video frame
>storage Application.
Are you actually storing a video frame, and does your output need to be
synced to the input? The easiest way to get clean output is to generate new
H/V sync from the same source as your pixel clock. This moves the
synchronization problem to the video memory interface.
>I am using oscillator for generating the 16mhz Clock but my video out
>is not stable it have some color problem on the top of the frame
>manse on the first 100 lines of the video and it vary on changing
>of source, first I thought it is a clock stability problem so that I
>changed the oscillator to 5ppm but the problem is still there so I
>want a clock synchronous to video Hsync.
If the output must be in sync with some other video signal, your 16 MHz
oscillator will have to be "st 100 lines of the video and it vary on changing" to that signal. An analog PLL would
probably be the easiest solution. But once again, for best results you
should regenerate Hsync from your pixel clock.
>Can u help me, How can I get the clock synchronous to the video
>because it is affecting the performance of video.
>If u have some idea how we can generate in Fpga so pl'z help me out.I
>Need your urgent Help.
>Thanks For any suggestion.
>
>Regards
>Arvind.
--
Caleb Hess hess@cs.indiana.edu
Article: 51412In article <avuipe$rq1$1@rainier.uits.indiana.edu>, Caleb Hess <hess@cs.indiana.edu> wrote: >If the output must be in sync with some other video signal, your 16 MHz >oscillator will have to be "st 100 lines of the video and it vary on >changing" to that signal. An analog PLL would >probably be the easiest solution. But once again, for best results you >should regenerate Hsync from your pixel clock. My editor hiccuped. That should be "... your 16 MHz oscillator will have to be genlocked to that signal." -- Caleb Hess hess@cs.indiana.eduArticle: 51413
Astonish,
SBOXes are arrays of constants used to encrypt/decrypt data as part of
DES algorithm. The input data to be encrypted/decrypted goes through
S-Box substitution upto 16 times in DES (48 times in Triple-DES). SBOX
values can be found in NIST's DES documents at
http://csrc.nist.gov/encryption/tkencryption.html
"FIPS 46-3, Data Encryption Standard (DES)" document has detailed
information on DES algorithm.
I haven't looked at the Celoxica's white paper. You can also take a look
at XAPP270 @ http://support.xilinx.com/xapp/xapp270.pdf for FPGA
implementation of DES and Triple-DES.
-Vikram
astonish wrote:
> Celoxica's White Paper on TripleDES describes
>
> typedef rom unsigned 4 SBox[64];
>
> static SBox SBoxes[8] =
> {
> SBox1, SBox2, SBox3, SBox4,
> SBox5, SBox6, SBox7, SBox8
> };
>
> How can I initialize the SBox array and what are
> SBox1, SBox2, .. ,SBox8?
>
> Any assitance appreciated.
>
> Astonish
Article: 51414gregs@altera.com (Greg Steinke) writes: Thank you for your reply. I'm happy to see that Altera is answering questions in comp.arch.fpga. > However, there is another way that you could consider - > Instead of changing the delay of the data pin to the register, you > could change the delay of the clock to the register. This has a > similar effect of adjusting the TSU/TH window. The Stratix Enhanced > PLL has feature called "PLL Reconfiguration" where certain PLL > attributes can be modified by system logic, without loading a new > programming file. One of these attributes is a programmable delay on > the PLL output. So you would have the ability to change this delay > without device configuration, which would have much the same effect as > changing the data delay. This is what I've been doing (simulation only) up to now. The problem is that the number of PLL's is limited. I was hoping to be able to configure the input delay separately (using some training logic) for each of the 17 bits x 3 ports. This would be possible it was a run-time programmable delay in each IOE. Thanks Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 51415
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<avu63i$18t$1@news.tu-darmstadt.de>... > Thorsten Bunte <t.bunte@beckhoff.de> wrote: > : Thanks, > > : unfortunately these devices are quite expensive. Are there any cheaper > : available? > > A XC2V250 ist listed with about 80$. $80 may be expensive to some people. Thorsten can cascade two DLL's on a Virtex-E or Spartan-IIE to get a multiply by 4. More info can be found in app note 132. MarcArticle: 51416
Bob Fischer wrote: > I will be testing an FPGA design that is intended to drive a PC for > initial checkout and later to an embedded computer using parallel > port. I selected the EPP protocol as it looks like it can support > what I need to do. > > The FPGA will output 10 bytes of data to the PC each cycle of > operation. The data consists of five 14 bit values output in two > bytes each. The FPGA will be performing about 40,000 cycles per > second. Think of each cycle as a 25 us frame. Data collection (about > 4 us), processing (about 7-8 us) occurs for the first 11-12 us of each > frame. When the data is ready the parallel port Interrupt line is > asserted. > > The burst rate during the available 13 us data output portion is > around 770 Khz. The times have already been verified in the > simulations. For the simulation I used an 800 ns byte cycle. The > testbench emulates the PC by responding to the Interrupt, invoking the > byte cycle timing as expected from the PC by cycling the Data Strobe > line (400 ns low then 400 ns high for each byte). The FPGA responds > with Waits and presentation of data bytes at the time defined for the > EPP port. I used the timing found in web site > www.beyondlogic.org/epp/epp.htm > > The output of the FPGA is configured for TTL levels, slow transitions. > I intend to pipe the FPGA directly to the DB connector and through a > 3 ft parallel cable to the PC parallel port. > > In the PC we will DMA the data to memory and accumulate it for several > seconds. A display program will access that memory and generate > graphs, etc for visual analysis of the performance and results. > > Does this approach to PC interfaceing sound feasible? Has anyone out > there any prior experience they would like to share? Some Do's and > Don'ts? > > Bob Fischer > FPGA independent designer You are pushing it... Most PCs don't go faster than 1us/Byte in EPP mode. Also, EPP doesn't support DMA, you need ECP for that. You may be able to use EPP, if you can buffer the data for a few complete cycles. Interrupt latency is 10-50us plus whatever your OS adds to that. You may get away with a shorter buffer if you use a RTOS. Kind regards, IwoArticle: 51417
Tiger growled-
>Is it possible to implement a bidirectional digital switch
>in a CPLD ? I want to cut off a databus ...
>
sure! I/O on most CPLDs is tristate-able -
here is a snippet of code fer-instance -
port ( data_a, data_b :inout std_logic;
a__to_b, b_to_a : in std_logic)
.
.
.
.architecture
.
begin
data_a <= data_b when b_to_a else 'Z';
data_b <= data_a when a_to_b else 'Z';
end;
Article: 51418In article <3E22425C.5000403@sbcglobal.net>, LW_Rogers@sbcglobal.net says... > Gentlement: > > I've built a small computer board for a small local college (mostly > from one of the professor's designs and partly from designs in the > book). The machine uses PLDs in several places and I figured I could > simplify the board some (and improve by skills) by (learning about and) > using FPGAs, but I don't know where to get the initial software or > download equipment. > > TIA(Thanks In Advance) > > 2Penny(2cents worth of opinion) > > I have been using the Altera chips and their MAX2 Plus software. I have a direct link to the software download page in this pdf file http://www.hvwtech.com/downloads/other/fpga_software_info.pdf -- Dan Henne DAN.nospam@HVWTECH.COM HVW Technologies Inc. www.HVWTech.comArticle: 51419
Thanks, I will give your suggestions a shot and post my results soon. Prashant rickman <spamgoeshere4@yahoo.com> wrote in message news:<3E1F1F12.A6722E19@yahoo.com>... > Prashant wrote: > > > > Hi everyone, > > > > A few days back I had posted a message about my problems with an > > asynchronous RAM on my FPGA board. I received a lot of help from group > > members and I managed to fix my code...well, partly. > > > > To refresh the problem, I read/write data to n fro from an > > asynchronous RAM external to the FPGA on my prototype board. My > > initial design involves reading 64000 8 bit values from the board and > > writing 64000 values back. These are done in bursts of 512 values each > > and then there is a break before the read/write starts again. > > > > The async RAM is able to run @ 100MHz according to its specs. The code > > runs @ 10 MHz. The board clock is @ 40MHz and by using a pll in my > > FPGA, I run the code @ 10MHz. > > > > I have found after having run several runs of my code that > > approximately 44500 values of the 64000 are read/written correctly. > > After that something goes wrong and the rest of the values are > > incorrect. > > > > Initially I had problems with all 64K values, but then with some > > advice from the group, I took two cycles (instead of one) to read and > > write data from the async RAM and things improved, but only for 45000 > > values. > > > > Any ideas on what could be going wrong ? I checked my code and it is > > completely synchronous (except for the external RAM). > > The issue is not whether the code is synchronous or not. An asynch ram > is not synch by nature. So what you need to pay attention to are the > various timing specs for the address, data and read/write strobes. > Since you are running way slower than what the RAM can do, you should be > able to implement a very simple design to allow reading and writing of > the RAM. I don't know what you were told before, so I will assume > nothing. > > The main issue is to keep the address and data stable while the write > strobe is asserted. The other issue is to read the data after it is > stable but before you remove the read strobe. So to make certain that > all of these timing restrictions are met, I would use the 40 MHz clock > and use four clock cycles for a read or a write. Like this, view in a > fixed width font... > > | Write | Read | > FPGA Clock --__--__--__--__--__--__--__--__--__--__--_ > RAM Addr ====<--addr-stable--><-addr-stable-->====== > RAM Data ====<--data-stable-->zzzzzzzzzzzzzzz>====== > RAM WR ---------________-------------------------- > RAM OE -------------------------________---------- > RAM CS ---------________--------________---------- > ^ > FPGA Reads Data | > > For a Write cycle, the Address and Data should be output during the > first clock cycle and remain stable for the entire four clock cycles. > The WR strobe should be asserted during the second and third clock > cycles and removed for the fourth clock cycle. This will give you lots > of setup and hold time on your address lines. If you are seeing write > problems, this is most likely where it is. > > For a Read cycle, the Address is set up for all four cycles like in a > Write cycle, but the data bus is tristated for all four cycles. The > read strobe should be asserted for the second and third clock cycles. > Since the RAM is very fast you can read the data in the middle of the OE > strobe on the rising edge of the third clock. This will give the FPGA > lots of setup and hold time on the data. Removing the CS and OE at that > start of the fourth clock cycle gives an entire clock cycle for the RAM > output to go tristate to prevent any contention on the data bus. > > These timings are very, very conservative given your 10 nS async RAM. > If this does not work, I expect you have a ground bounce or other signal > integrity issue that is double clocking the write strobe and trashing > data after it is written. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51420
John Tan wrote:
>
> Hi, what is the merit & constraint of each of these design entry
> methods
>
> - schematic design
> - VHDL
>
I am sure I will be scolded by regulars of comp.arch.fpga who
have 10+ years experience and often have schematic background unlike
myself, but here is my take.
Schematics:
* More effort
* Time consuming
* Have more control of the design
* Less portable to another platform (i.e., Xilinx to Altera)
* No one uses it for large designs anymore because using HDL is more
efficient
VHDL (or HDL in general):
* Easier to make modifications (i.e., expanding the bus size)
* The synthesis tool does the hard stuff (i.e., Synthesizing logic from
the text)
* Easier to port to another platform (As long as vendor specific
primitives are not used.)
* Have less control of the design (The synthesis tool may not do a good
job synthesizing the design.)
* As far as I know, almost all ASIC designs nowadays use some kind of
HDL
> i have heard pple saying any changes in schematic entry, will cause
> all timing to be changed and you got to check your timing again; is
> this true ? ANd how about VHDL; is it really better?
>
Whether or not you will have to check the timing in a schematic
design after making changes will depend on how much changes you make to
the design.
I will say that problem will likely be worse in VHDL because the fact
that the logic gets synthesized in VHDL.
> I have last done a uni. project to implement a convolutional codec
> using schematic entry method; and frankly i i can't imagine to program
> the design in VHDL ...it's just too enormous the codes!
I don't know how much experience you have with HDL (Verilog or
VHDL), but my guess is that you haven't really had the opportunity to
experience how much more powerful HDL is compared to schematics.
In my case, I developed a PCI IP core using Verilog, and looking at it,
I cannot imagine myself doing that in schematics.
Yes, I am aware that there are several implementations of PCI IP core
that used schematics, but still, I will never consider using schematics
because the effort I would have had to put in would have been enormous
compared to using Verilog.
Especially, implementing a state machine is much harder in schematics,
but is really easy in HDL.
If you have looked at VHDL, and thought that the syntax isn't
for yourself, try Verilog instead.
I find Verilog simpler to use than VHDL, and the Verilog's syntax is
less annoying than VHDL.
Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
Article: 51421That depends on the vendor and the device family. Actel and Quicklogic have one-time programmable FPGAs, which I have not used but I presume you would want to socket them while you are developing code. Xilinx and Altera have SRAM-based FPGAs which reload their programming every time they power-up. You can load them from a PROM, from an ISP EEPROM, or from a JTAG cable. Check the vendors' web sites for all the possibilities. "2Penny" <LW_Rogers@sbcglobal.net> wrote in message news:3E20C539.6010403@sbcglobal.net... > Gentlement: > > I've built a small computer board I've made for a small college here. > I'd like to simplify the design by putting the glue logic into an > fpga, but I know nothing about fpgas. I think I can ask the college > to spring for the software if it isn't too much, but how do I download > this to the chip. I do this fairly regularly with ABEL and PLDs, but > I think I should update my skills, but I don't know where to turn. > I'm looking for clues. Please point me in the right direction. > > TIA > > 2Penny >Article: 51422
hi,
I am having problem in simulating the Virtex's Primitive (e.g CLKDLL,
BUFG...) using Modelsim. Could anyone tell me how to do it? I got errors
in the Modelsim like
# WARNING[1]: main.vhd(244): No default binding for component: "ibufg".
(No entity named "ibufg" was found)
# WARNING[1]: main.vhd(247): No default binding for component: "clkdll". (No
entity named "clkdll" was found)
# WARNING[1]: main.vhd(248): No default binding for component: "bufg". (No
entity named "bufg" was found)
Thanks.....
Chris
Article: 51423If you do not need the Rocket I/Os (multi-gigabit transceivers), just disable them, and they only consume microamps. No problem! Peter Alfke, Xilinx Applications ============================== Valeri Serebrianski wrote: > Well, I really need some kind of processor inside, but what about > excessive power consumption in case I don't need to use RocketIO's? In > VirtexII-Pro datasheet stated that EACH RocketIO channel consumes 310 > mW for 2.5 Gb/s and 230 mW for 1.25 Gb/s operations. I may surmise > that for 0 Gb/s operations each RocketIO will consume next 80 mW less > power: 230 - 80 = 150 mW. Multiplying it by 4 (at least) we get > 4*150=600 mW! For embedded applications that excessive power > consumption may be critical (at least for my case it is true). >Article: 51424
Even without the tristate, an internal bidirectional switch can be emulated. Look into the Xilinx documentation on their internal tristate lines. The newer parts (I forget if it was the Virtex or Virtex-II datasheets that I first saw the writeup) don't have real tristate drivers feeding the internal "tristate lines" but have digital circuitry to emulate the tristate resulting in defined "no driver" and "contending driver" behavior. The effective circuitry was detailed on one of those functional data sheets. "Mikeandmax" <mikeandmax@aol.com> wrote in message news:20030113105644.02086.00000360@mb-mq.aol.com... > Tiger growled- > >Is it possible to implement a bidirectional digital switch > >in a CPLD ? I want to cut off a databus ... > > > > sure! I/O on most CPLDs is tristate-able - > here is a snippet of code fer-instance - > > port ( data_a, data_b :inout std_logic; > a__to_b, b_to_a : in std_logic) > . > . > . > .architecture > . > begin > data_a <= data_b when b_to_a else 'Z'; > data_b <= data_a when a_to_b else 'Z'; > > end;
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