Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Dear experts, VQM(Verilog Quartus Mapping File) is the Quartus II's input netlist format. Does anybody know the spec. book of VQM? Does anybody know how to convert VQM to EDIF netlist? Thanks, Kwon. -- -*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-* Young-Su Kwon Ph. D Student. VLSI Systems Lab, KAIST yskwon@vslab.kaist.ac.kr -*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*Article: 52201
Hello Jing, you can find more info on XDL in the command line and if I remember you can use a switch like xdl / help (for e.g) to obtain more info. I used this utility a while ago and it is used to convert the binary file (.ncd) into an ascii file (to obtain the netlist of an implemented design in the device). Cheers Anup Jing wrote: > Does anyone know where I can find the documentation for XDL(Xilinx > Description Language)? It should be a utility that comes with ISE, but > I can't find anything about XDL on the ISE software documentation on > www.xilinx.com. Thanks a lot.Article: 52202
Jonathan Bromley wrote: > "S. Ramirez" <sramirez@cfl.rr.com> wrote > > >>>plz let me know complete Difference between : CPLD , FPGA , ASICS >> >>CPLD - Complex Programmable Logic Device >>FPGA - Field Programmable Gate Array >>ASICS-Application Specific Integrated Circuits > > > While Simon's gloss is clearly correct, it's perhaps not very > informative to a newby. A sideways view might be more helpful. > > How about... > CPLD: Middling-to-big programmable doohickey marketed by people > who still think 22V10s are a pretty neat idea. > FPGA: Big-to-huge programmable doohickey marketed by people who > think that it's a pretty neat idea to spend 75 million > transistors in order to create a million gates of logic. > ASIC: Huge-to-gigantic non-programmable doohickey designed by > machos who think that modifying a gate level netlist > with a 10,000-line Perl script in order to fix one missing > inverter is a pretty neat way of doing an ECO. Addition : Sometimes the EEPROM(self) configured devices are refered to as CPLD, while the SRAM (not self configured) devices are refered to as FPGA. An ASIC doesn't have to be big in number of gates, nor does it have to be fabricated in huge numbers. It may just be something not available in other technologies. ReneArticle: 52204
sadik wrote:
> When i run the tcl script
?
Post the script.
> quartus II 1.0
Consider version II 2.2
> gives the error called
> "Can't start server quartus_cmp Beginning attempt 1 of 3 attempts to start server"
> But the same project got completed in when fired through GUI!
> What could be the problem???
Perhaps the GUI is running different scripts than you are.
Run a TCL debugger or just use the GUI as is.
-- Mike Treseler
Article: 52205Ray, Having tools place and route one instance of a module then replicating that placement and routing for other instances of the same module is on the roadmap. We do see this as an excellent flow but don't have enough software engineers to do everything we want!!! Of course, having more and more customers ask for this flow can help the priority and get it done sooner so a CR isn't a bad thing. Another approach would be the Incremental Design flow. Check out: http://support.xilinx.com/xapp/xapp418.pdf for more information. This isn't exactly what you want but it should help assuming you aren't changing the module that is replicated. Once you get a placed and routed design, the tools will only re-place and route the changed modules. The unchanged modules use the previous placement and routing information. We have seen great improvements in PAR runtimes. Kate Ray Andraka wrote: > It is an excellent approach, unfortunately, the xilinx tools do not support > it. Basically what you want is a hierarchical place and route so that each > identical submodule is placed and routed once, then those are stitched > together at the top level. It is a rather radical departure from the current > Xilinx strategy of flattening the design for place and route, so it is a > fairly major undertaking for Xilinx to change it. Please, Please, Please, > Please, open a case with Xilinx and make your case about needing this > capability. The more customers that ask for it, the more likely it will be > addressed in our lifetimes (this is something a number of frequent users have > been asking for for quite some time). > > In the mean time, you can reduce the placement time by doing the > floorplanning. The 5.1 floorplanner includes a 'hierarchical' placement, > although I am not sure how well it really works. You can put placement in > your source code for the macro to make each instance into an RPM, and then > place the RPMs in the flat floorplanner or through a UCF file. Unfortunately, > there is little you can currently do about the routing. Also, the router in > 4.1 and later won't necessarily make the direct route to neighboring cells > even though those are there. The router algorithm changed, and now only tries > to get a non-negative slack. As a result, the low hanging fruit in the > nearest neighbor connections is often overlooked and a long serpentine route > is used instead. See the floorplan for the sonar processor in the gallery on > my website for an example of a design that has many (in that case 50) similar > 'tiles' that were floorplanned hierachically with RLOCs. > > Johannes Sandvall wrote: > > > In order to shorten the place and route processor time I am looking into > > ways to modulize the design. > > I'm using a virtex-II 8000, which have 168 multerpliers / block selectram, > > in a 28x6 layout. The design consists of 168 equivalent cell, which has > > exactly the same vhdl-code. All cells only talk to the neighboring cells > > so routing between cells should not be that hard. > > > > What I would like to do is to compile one of the cells as a module and > > do the local place and route once for all. > > > > One thing I've tried is to open floorplanner and set a constraint-box > > for each cell, save the file as .mpf and retry with place and route. > > Problem with this seems to be that place & route still takes very long > > time. > > > > Is there as possibility to generate a rpm for one module and then place > > the modules and only route them. I realize that if you look at the > > physical layout of the chip, there is 3 different cases. If all blocks > > have the same size, there is 3 different constraint-boxes. One with > > the multiplier to the left in the cell, one in the midle and one to > > the right. > > > > Since all cells just talk to there neighbors there should be a > > possibility of placing the 3 different cells and route them together. > > > > Is this a good approach, is it even possible to do? > > What are the alternatives? What about module something from xilinx? > > > > All response is welcome! > > > > Regards Johannes > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 52206
David wrote:
> I have a design that I synthetize in Leonardo and then compile/fit in
> MaxplusII (I would use QuartusII but the web edition doesn't support the
> EPF10K20RC240 which is on the University dev. board....I don't get that
> one.)
> Anyway, I don't understand why MaxplusII says it doesn't fit. Here is the
> report from Leonardo (quite encouraring):
>
> ***********************************************
> Device Utilization for EPF10K20RC240
> ***********************************************
> Resource Used Avail Utilization
> -----------------------------------------------
> IOs 35 189 18.52%
> LCs 347 1152 30.12%
>
> MaxplusII says that it uses too many logic cells (1978/1152). This number is
> way off what leonardo expected. I'm using the .edf file produced by leonardo
> and compile it in MaxPlus. I guess this is the usual way to proceed. Could
> it be because the design uses LPM components?
Perhaps leo black-boxed the LPMs and didn't count their contents.
Consider starting with a simpler example to learn the tools.
Consider learning the numeric_std library and coding
your own counters etc. This will make leo do some work for you.
-- Mike Treseler
Article: 52207Praveen, The .VHF/.VF files will be generated when you run synthesis or view VHDL/Verilog functional model in the process window. You can see what flow you use by taking a look at your source window. The window on the upper left hand of ISE gui, the second line(if there are no unrelated files) should tell you the device as well as the design flow you're running. (ie. XST VHDL/XST Verilog) The files should be located in your project files folder. Regards, Wei bams wrote: > Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<3E3EE856.8F0C8739@xilinx.com>... > > Bams, > > > > With ISE, it always generate VHDL or Verilog file depending on which flow you > > use. XST VHDL generate .VHF(equivalent of .vhd) while XST VERILOG generates .VF > > file(equivalent of .v). > > > > Regards, Wei > > Hello Wei, > thanks for your input.I couldn't locate .vhf file. where do i find > that file inside my project.I didn't get what you mean by "which flow > i use".your help will be greatly appreciated. > > regards, > Praveen > > > > bams wrote: > > > > > I want to know if we can convert a schematic design to a VHDL file inside a > > > xilinx project.Do I need any external software to do that? > > > > > > --bamsArticle: 52208
Hi all, First of all, am I correct in thinking that longlines in Xilinx Virtex and Virtex-II devices cannot be partitioned in the same way that the routing for 3-state buses can be? If they can't, then it seems to me that as device capacities rise, unless signals are routed over longer and longer distancs, an increasing proportion of the tracking will end up not being used. Would it therefore be beneficial to be able to partition these lines, in order to provide a greater amount of shorter-distance routing to alleviate congestion and device utilsation rises? If pass transistors were used to provide this segmenation (I guess this how the 3-state buses are segmented - let me know if there are better ways), I realise that this would have an impact on performance when transmitting over very long distances, due to their on-resistance. Apart from a (slight?) loss in performance (obvisouly, depending on the number of segements a line had) and the silicon overhead of the pass transistors and their associated configuration stores, are there any other ways in which performance would be affected? Do people think this is a good idea, a bad idea, or one which (due to the sheer amount of shorter routing in Xilinx chips anyway), isn't likely to have a significant impact? Thanks for your help, SteveArticle: 52209
It is good to hear that it is on the roadmap. Folks, if you think hierarchical place
and route is important (I do), please let Xilinx hear about it. The more customers
they hear want it, the higher priority they'll assign to making it so. Personally,
I'm surprised the folks migrating from ASICs to FPGAs haven't screamed over not having
it.
Kate Kelley wrote:
> Ray,
>
> Having tools place and route one instance of a module then replicating that
> placement and routing for other instances of the same module is on the roadmap.
> We do see this as an excellent flow but don't have enough software engineers to do
> everything we want!!! Of course, having more and more customers ask for this flow
> can help the priority and get it done sooner so a CR isn't a bad thing.
>
> Another approach would be the Incremental Design flow. Check out:
> http://support.xilinx.com/xapp/xapp418.pdf
>
> for more information.
>
> This isn't exactly what you want but it should help assuming you aren't changing
> the module that is replicated. Once you get a placed and routed design, the
> tools will only re-place and route the changed modules. The unchanged modules use
> the previous placement and routing information. We have seen great improvements
> in PAR runtimes.
>
> Kate
>
> Ray Andraka wrote:
>
> > It is an excellent approach, unfortunately, the xilinx tools do not support
> > it. Basically what you want is a hierarchical place and route so that each
> > identical submodule is placed and routed once, then those are stitched
> > together at the top level. It is a rather radical departure from the current
> > Xilinx strategy of flattening the design for place and route, so it is a
> > fairly major undertaking for Xilinx to change it. Please, Please, Please,
> > Please, open a case with Xilinx and make your case about needing this
> > capability. The more customers that ask for it, the more likely it will be
> > addressed in our lifetimes (this is something a number of frequent users have
> > been asking for for quite some time).
> >
> > In the mean time, you can reduce the placement time by doing the
> > floorplanning. The 5.1 floorplanner includes a 'hierarchical' placement,
> > although I am not sure how well it really works. You can put placement in
> > your source code for the macro to make each instance into an RPM, and then
> > place the RPMs in the flat floorplanner or through a UCF file. Unfortunately,
> > there is little you can currently do about the routing. Also, the router in
> > 4.1 and later won't necessarily make the direct route to neighboring cells
> > even though those are there. The router algorithm changed, and now only tries
> > to get a non-negative slack. As a result, the low hanging fruit in the
> > nearest neighbor connections is often overlooked and a long serpentine route
> > is used instead. See the floorplan for the sonar processor in the gallery on
> > my website for an example of a design that has many (in that case 50) similar
> > 'tiles' that were floorplanned hierachically with RLOCs.
> >
> > Johannes Sandvall wrote:
> >
> > > In order to shorten the place and route processor time I am looking into
> > > ways to modulize the design.
> > > I'm using a virtex-II 8000, which have 168 multerpliers / block selectram,
> > > in a 28x6 layout. The design consists of 168 equivalent cell, which has
> > > exactly the same vhdl-code. All cells only talk to the neighboring cells
> > > so routing between cells should not be that hard.
> > >
> > > What I would like to do is to compile one of the cells as a module and
> > > do the local place and route once for all.
> > >
> > > One thing I've tried is to open floorplanner and set a constraint-box
> > > for each cell, save the file as .mpf and retry with place and route.
> > > Problem with this seems to be that place & route still takes very long
> > > time.
> > >
> > > Is there as possibility to generate a rpm for one module and then place
> > > the modules and only route them. I realize that if you look at the
> > > physical layout of the chip, there is 3 different cases. If all blocks
> > > have the same size, there is 3 different constraint-boxes. One with
> > > the multiplier to the left in the cell, one in the midle and one to
> > > the right.
> > >
> > > Since all cells just talk to there neighbors there should be a
> > > possibility of placing the 3 different cells and route them together.
> > >
> > > Is this a good approach, is it even possible to do?
> > > What are the alternatives? What about module something from xilinx?
> > >
> > > All response is welcome!
> > >
> > > Regards Johannes
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52210Steve, The longlines in V-II/V-IIPro are partitioned. You can look at FPGA Editor to see where the pips are located. I am not sure about Virtex/VirtexE. Kate Steve Charlwood wrote: > Hi all, > > First of all, am I correct in thinking that longlines in Xilinx Virtex > and Virtex-II devices cannot be partitioned in the same way that the > routing for 3-state buses can be? > > If they can't, then it seems to me that as device capacities rise, > unless signals are routed over longer and longer distancs, an increasing > proportion of the tracking will end up not being used. > > Would it therefore be beneficial to be able to partition these lines, in > order to provide a greater amount of shorter-distance routing to > alleviate congestion and device utilsation rises? > > If pass transistors were used to provide this segmenation (I guess this > how the 3-state buses are segmented - let me know if there are better > ways), I realise that this would have an impact on performance when > transmitting over very long distances, due to their on-resistance. > > Apart from a (slight?) loss in performance (obvisouly, depending on the > number of segements a line had) and the silicon overhead of the pass > transistors and their associated configuration stores, are there any > other ways in which performance would be affected? > > Do people think this is a good idea, a bad idea, or one which (due to > the sheer amount of shorter routing in Xilinx chips anyway), isn't > likely to have a significant impact? > > Thanks for your help, > > SteveArticle: 52211
"azim premji" <azim_premjii@yahoo.com> wrote in message news:9afc0e91.0302032125.ba021f1@posting.google.com... > hi > plz let me know complete Difference between : CPLD , FPGA , ASICS How about DYOH... Do your own homework.Article: 52212
Can i instantiate a library component(schematic) in VHDL code ? regards, bamsArticle: 52213
You didn't specify which device type you were using. But as an example, see http://www.xilinx.com/publications/products/v2/ug_pdf/ug002_ch2.pdf (Virtex 2 users guide, chapter 2) for examples of instantiating DCM's, multipliers, etc. in VHDL. I'm sure other device types and their user guides have similar examples. bams wrote: > Can i instantiate a library component(schematic) in VHDL code ? > > regards, > bamsArticle: 52214
Hello, I am in the process of floorplanning an FPGA design which contains an adder tree. The Xilinx documentation mention that datapaths should flow horizontally in order to make the best use of routing resources. Is there also a preference for left to right flow vs right to left? Thanks, DougArticle: 52215
I will say that the difference between 2.1 and 2.2 isn't that big. The PCI's protocol largely remain the same since PCI 2.0. Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.) praveen wrote: > > Hello Friends/Sir, > I wanted to know what is the difference between PCI rev 2.1 and PCI rev. 2.2. > > Waiting for Reply > Thanks in advance > PraveenArticle: 52216
Some documentation can be found at XILINX\help\data\xdl\ where XILINX is the location of your ISE installation. hjing@ece.neu.edu (Jing) wrote in message news:<c4b9775f.0302010839.3a953499@posting.google.com>... > Does anyone know where I can find the documentation for XDL(Xilinx > Description Language)? It should be a utility that comes with ISE, but > I can't find anything about XDL on the ISE software documentation on > www.xilinx.com. Thanks a lot.Article: 52217
I am not surprised that you didn't think Opencores.org's PCI IP was that
helpful.
I have seen the RTL code too, and the authors have gone too much into
handcrafting the design, making it really hard for someone else to
understand what goes on within it (I have done a PCI IP core of my own,
but it was still very hard to understand what goes on within
Opencores.org PCI IP core.).
Anyhow, this EE Times article discusses about PCI target state
machine.
http://www.eedesign.com/editorial/1995/fpgafeature9502.html
You can also download simple PCI interfaces from Xilinx and
Lattice Semiconductor.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=cc7b0b5f.0210172126.2db7758%40posting.google.com&rnum=5
Some time ago, I commented about how to implement a PCI IP core.
That should help somewhat.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=cc7b0b5f.0210172126.2db7758%40posting.google.com&rnum=5
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=d134a01690d324cf64b16af0371b5f51.52472%40mygate.mailgate.org&rnum=7
Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
praveen wrote:
>
> Hello Mr.Kevin,
> I have all documents of PLX 9050. Its little difficult to start about.
> Which one to implement????.....this type of question keeps buging me.
> It will good if i can get was reference PCI core detail(internal
> design details), do u have any idea where i can get?????. I tried
> opencore.com but he doesnot explain properly.
> If anyone have any details regarding it . Please do tell
>
> waiting for reply
>
> praveen
Article: 52218Austin, To make a correction of what you said, if bit 0 of a BAR is 1, that will indicate that BAR is for IO space, and if so, bit 2 and 1 will not indicate 64 bit addressing. For IO space, bit 2 can only be a register or hardwired to 0, and bit 1 is currently reserved (Has to be hardwired to 0.). Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.) Austin Franklin wrote: > > > You get a 4k space starting at 0x0200_0xxx. BUT, why are you setting bit 0 > to 1 for? You are asking for 4k of I/O space...and you probably really want > memory space. Why are you setting bit 2? Setting bit 2 and 1 to 10b asks > the system to locate you in 64 bit address space... >Article: 52219
Not really any preference left to right. The horizontal flow is desired
because of the vertical orientation of the carry chains
douglas fast wrote:
> Hello,
>
> I am in the process of floorplanning an FPGA design which contains an
> adder tree. The Xilinx documentation mention that datapaths should
> flow horizontally in order to make the best use of routing resources.
> Is there also a preference for left to right flow vs right to left?
>
> Thanks,
>
> Doug
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52220
Yes. If it is from your own schematic, the component gets
black-boxed in the VHDL, then the black box gets filled with the
edif netlist for the schematic when you do the translate step in
the xilinx back end tools. You won't be able to simulate the VHDL
source it unless you have a suitable model for the schematic.
bams wrote:
> Can i instantiate a library component(schematic) in VHDL code ?
>
> regards,
> bams
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52221Robert, Use ROMs as Mike suggests. You can create ROMs very easily using the MEGAfunction wizard in the Quartus II toolset. This will take inputs such as data bitwidth and address bitwidth from you and create a ROM for you without you needing to write any code. Such a ROM will use the FPGA ESBs, just as you want it. You can then instantiate these ROMs to be used in your code as lookup tables. You can also use RAMs incase you need dynamically changing tables. Prashant "Roberto Gallo" <robertogallofilho@hotmail.com> wrote in message news:<b1mlk4$q0d$1@aracaju.ic.unicamp.br>... > Hello there, > > I am desiging a device that uses table lookups on processing of > information (Writing an AES core). However as many as sixteen 256x8 bits > tables should be used. These tables are equal in content, however they have > independent indexing. > I was wondering about how to group them, so that I could use FPGA´s > memory intead of registers. Is it possible to use a multi-output memory? How > to? > I am using a APEX20K200 with Quartus II 2.0 and Leonardo and writing in > VHDL. > > Thank you, > Roberto Gallo.Article: 52222
hey praveen,
u can find all the files in xilinx/iseexamples/projectname/*.*
directory . there will b one on ur system.
u can c those files using "open file" and using the file
type:"all files"
regards
naveen
bamini222@yahoo.com (bams) wrote in message news:<4306d0af.0302032252.41e3b2b7@posting.google.com>...
> Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<3E3EE856.8F0C8739@xilinx.com>...
> > Bams,
> >
> > With ISE, it always generate VHDL or Verilog file depending on which flow you
> > use. XST VHDL generate .VHF(equivalent of .vhd) while XST VERILOG generates .VF
> > file(equivalent of .v).
> >
> > Regards, Wei
>
> Hello Wei,
> thanks for your input.I couldn't locate .vhf file. where do i find
> that file inside my project.I didn't get what you mean by "which flow
> i use".your help will be greatly appreciated.
>
> regards,
> Praveen
> >
> > bams wrote:
> >
> > > I want to know if we can convert a schematic design to a VHDL file inside a
> > > xilinx project.Do I need any external software to do that?
> > >
> > > --bams
Article: 52223I have asked this same questions to FAEs and they used to recomend left to right for data flow on the 4000s series since you didn't want the output of a flip flop to have to route "back". For Virtex they say that the improved routing resources make this a non-factor as usual you want to make sure that any adders, counters, etc make use of the carry chain which is vertically oriented. "douglas fast" <d@vcom.com> wrote in message news:981fe2ba.0302041214.42e759e6@posting.google.com... > Hello, > > I am in the process of floorplanning an FPGA design which contains an > adder tree. The Xilinx documentation mention that datapaths should > flow horizontally in order to make the best use of routing resources. > Is there also a preference for left to right flow vs right to left? > > Thanks, > > DougArticle: 52224
Steve, Sorry, I had a misunderstanding about the vertical longlines. You are correct, you can't partion them. Kate Kate Kelley wrote: > Steve, > > The longlines in V-II/V-IIPro are partitioned. You can look at FPGA Editor > to see where the pips are located. I am not sure about Virtex/VirtexE. > > Kate > > Steve Charlwood wrote: > > > Hi all, > > > > First of all, am I correct in thinking that longlines in Xilinx Virtex > > and Virtex-II devices cannot be partitioned in the same way that the > > routing for 3-state buses can be? > > > > If they can't, then it seems to me that as device capacities rise, > > unless signals are routed over longer and longer distancs, an increasing > > proportion of the tracking will end up not being used. > > > > Would it therefore be beneficial to be able to partition these lines, in > > order to provide a greater amount of shorter-distance routing to > > alleviate congestion and device utilsation rises? > > > > If pass transistors were used to provide this segmenation (I guess this > > how the 3-state buses are segmented - let me know if there are better > > ways), I realise that this would have an impact on performance when > > transmitting over very long distances, due to their on-resistance. > > > > Apart from a (slight?) loss in performance (obvisouly, depending on the > > number of segements a line had) and the silicon overhead of the pass > > transistors and their associated configuration stores, are there any > > other ways in which performance would be affected? > > > > Do people think this is a good idea, a bad idea, or one which (due to > > the sheer amount of shorter routing in Xilinx chips anyway), isn't > > likely to have a significant impact? > > > > Thanks for your help, > > > > Steve
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z