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Messages from 53975

Article: 53975
Subject: Problems useing ISE4.2
From: "DeSheng Li" <dsli@mail.ustc.edu.cn>
Date: Fri, 28 Mar 2003 17:16:54 -0800
Links: << >>  << T >>  << A >>
I have writen some VHDL using ISE4.2 and edit the UCF file like this. But it doesn't work. 

what is suppressed is that two days ago it worked correctly. So I think there must be some change with my the software settings, will anyone who knows the answer please mail me? thank you very
much. 

I paste the Entity defination and UCF file below: 

entity top is 
    Port( 
sysclk :in std_logic; 
  stn_clk: out std_logic; 
hs: out std_logic; 
vs : out std_logic; 
stn_data :out std_logic_vector(7 downto 0); 
rxd :in std_logic 
   ); 
end top; 

UCF file: 

NET "sysclk" LOC = "p88"; 
NET "stn_data<0>" LOC = "p6"; 
NET "stn_data<1>" LOC = "p7"; 
NET "stn_data<2>" LOC = "p10"; 
NET "stn_data<3>" LOC = "p11"; 
NET "stn_data<4>" LOC = "p12"; 
NET "stn_data<5>" LOC = "p13"; 
NET "stn_data<6>" LOC = "p19"; 
NET "stn_data<7>" LOC = "p20"; 
NET "rxd" LOC = "p91"; 
NET "stn_clk" LOC = "p4"; 
NET "hs" LOC = "p3"; 
NET "vs" LOC = "p5"; 

the error is: 
ERROR:NgdBuild:397 - Could not find NET 'rxd' in design 'top'. NET entry is 
   'NET "rxd" LOC = "p91"; 
   ' 
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. 
ERROR:NgdBuild:19 - Errors found while parsing constraint file "top.ucf". 





Article: 53976
Subject: Re: Spartan vs. Cyclone for arithmetic functions
From: Ray Andraka <ray@andraka.com>
Date: Sat, 29 Mar 2003 01:46:11 GMT
Links: << >>  << T >>  << A >>
Cyclone is certainly usable.  The mapping efficiency is going to depend on
whether you are just doing a simple add or if there is more functionality
in front of the add such as a mux.  It does have the direct connects
between LABs, and it also has extra gating to allow a controllable
add/subtract without going to a second level of logic.  The Xilinx
structure is still a bit more flexible going into a carry chain (you get
a  4 input LUT and a separate dedicated carry as opposed to 3 LUTs for
carry and sum plus a bit of gating for add/subtract).  The biggest
advantage the spartan has IMHO is the SRL16, which can be used as a
reloadable LUT (which is great for reprogrammable DA filters), as a delay
queue, as a reorder queue or other things.  The cyclone is closer to the
Xilinx functionality than 10K or 20K devices.

Matt Ettus wrote:

> I've seen this question answered in the FAQ, but only for older
> devices.
>
> I have a design which is mostly composed of adder-subtractors (i.e.
> you add or subtract depending on a third data input) of between 16 and
> 32 bits wide.  Some of these need to run as fast as 120 MHz.  Previous
> posts seem to indicate that Xilinx is much better for things of this
> type, but the posts were pre-Cyclone.  Does this still apply?
>
> We were planning on using the Spartan 2E with 300K-gates, but we are
> constrained to use a non-BGA part, and thus have become pin-limited.
> The Cyclone parts have more I/Os in the PQFP packages, so the EP1C6
> and EP1C12 looked interesting.  If Cyclone is usable for this sort of
> application, which part is closest in functionality to the SpartanII
> 300?
>
> Thanks
> Matt

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 53977
Subject: Re: CLKDLL synthesized with synplify pro
From: hamish@cloud.net.au
Date: 29 Mar 2003 04:08:16 GMT
Links: << >>  << T >>  << A >>
In comp.arch.fpga Barry Brown <barry_brown@agilent.com> wrote:
> I believe I have heard that the latest version of Synplify can also use the
> Xilinx
> Unisim library, as ModelSim does, but I have not yet upgraded, so I have to
> hide it with pragmas for synthesis:
> 
> -- synthesis translate_off
> library unisim;
> use unisim.vcomponents.all;
> -- synthesis translate_on

Why hide it? You can compile unisim_vcomp.vhd into your Synplify project
without trouble. (Except in 7.2 and later, where it'll conflict with the
built-in Synplify library.)

hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 53978
Subject: Re: Spartan vs. Cyclone for arithmetic functions
From: mrand@my-deja.com (Marc Randolph)
Date: 28 Mar 2003 20:58:04 -0800
Links: << >>  << T >>  << A >>
matt@ettus.com (Matt Ettus) wrote in message news:<e8fd79ea.0303281453.1a94c2f0@posting.google.com>...
> I've seen this question answered in the FAQ, but only for older
> devices.
> 
> I have a design which is mostly composed of adder-subtractors (i.e.
> you add or subtract depending on a third data input) of between 16 and
> 32 bits wide.  Some of these need to run as fast as 120 MHz.  Previous
> posts seem to indicate that Xilinx is much better for things of this
> type, but the posts were pre-Cyclone.  Does this still apply?

Howdy Matt,

Most likely not.  But the only way to determine with certainty if the
design is going to fit and meet timing in any part is to put it
through the tools and see.

The Cyclone is a much newer part and could likely outperform the
not-so-new Spartan 2E.  Later this year the Spartan III will come out,
which may leapfrog the Cyclone slightly.  That's how the competition
goes.
 
> We were planning on using the Spartan 2E with 300K-gates, but we are
> constrained to use a non-BGA part, and thus have become pin-limited. 
> The Cyclone parts have more I/Os in the PQFP packages, so the EP1C6
> and EP1C12 looked interesting.  If Cyclone is usable for this sort of
> application, which part is closest in functionality to the SpartanII
> 300?

It appears that you are correct - although Xilinx has parts with
considerably more I/O, you must use a fine pitch BGA to get them.  The
Spartan 2E (XC2S300E) has 7000 logic cells.  Ignoring all other
factors that might influence your choice (like core voltage, I/O
support, PLL vs. DLL, etc) this obviously falls between an EP1C6 and
an EP1C12, which have 6000 and 12000 logic cells respectively.

The key to comparing parts is to ignore the Xilinx marketing gate
counts and look at logic cells.  Altera has thankfully started putting
the logic count in their part number.

Now, a question:  What makes you think you need a 300K-gate FPGA for
this design?

Have fun!

   Marc

Article: 53979
Subject: Re: Spartan vs. Cyclone for arithmetic functions
From: "sanjay" <sanjay@cg-coreel.com>
Date: Sat, 29 Mar 2003 11:39:02 +0530
Links: << >>  << T >>  << A >>
Hi Matt,
what Ray says is perfect.
There is no competition to Spartan-IIE when it comes to arithmatic
operations.
Apart from SRL [ which according to Ray is biggest plus point of Xilinx ],
LUT can be configured as Distributed RAM which may be useful to you.
This you can't do with Cyclone.
Also 3 operand arithmatic Function [Sum = A+B+C]  goes in one Logic Block in
Spartan-IIE, which takes two Logic Blocks with Cyclone.
Apart from that Spartan-II E has Mult-AND for doing Fast Multiplications.

So I don't think there can be a any substitute for Spartan-IIE for your app.
--Sanjay

"Ray Andraka" <ray@andraka.com> wrote in message
news:3E84FB53.F9E1D5EA@andraka.com...
> Cyclone is certainly usable.  The mapping efficiency is going to depend on
> whether you are just doing a simple add or if there is more functionality
> in front of the add such as a mux.  It does have the direct connects
> between LABs, and it also has extra gating to allow a controllable
> add/subtract without going to a second level of logic.  The Xilinx
> structure is still a bit more flexible going into a carry chain (you get
> a  4 input LUT and a separate dedicated carry as opposed to 3 LUTs for
> carry and sum plus a bit of gating for add/subtract).  The biggest
> advantage the spartan has IMHO is the SRL16, which can be used as a
> reloadable LUT (which is great for reprogrammable DA filters), as a delay
> queue, as a reorder queue or other things.  The cyclone is closer to the
> Xilinx functionality than 10K or 20K devices.
>
> Matt Ettus wrote:
>
> > I've seen this question answered in the FAQ, but only for older
> > devices.
> >
> > I have a design which is mostly composed of adder-subtractors (i.e.
> > you add or subtract depending on a third data input) of between 16 and
> > 32 bits wide.  Some of these need to run as fast as 120 MHz.  Previous
> > posts seem to indicate that Xilinx is much better for things of this
> > type, but the posts were pre-Cyclone.  Does this still apply?
> >
> > We were planning on using the Spartan 2E with 300K-gates, but we are
> > constrained to use a non-BGA part, and thus have become pin-limited.
> > The Cyclone parts have more I/Os in the PQFP packages, so the EP1C6
> > and EP1C12 looked interesting.  If Cyclone is usable for this sort of
> > application, which part is closest in functionality to the SpartanII
> > 300?
> >
> > Thanks
> > Matt
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 53980
Subject: microblaze gnu tool info ?
From: Muzaffer Kal <kal@dspia.com>
Date: Sat, 29 Mar 2003 07:41:39 GMT
Links: << >>  << T >>  << A >>
Hi,
I guess some people here must be working with Microblaze processors. I
understand that Microblaze EDK ships with a port of GNU tools. Are the
sources for these tools available (from the GPL I understand that they
must be). When one gets the EDK, do you get the sources on the CD ?


Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations



Article: 53981
Subject: Re: DSP-FPGA interface
From: Joe <>
Date: Sat, 29 Mar 2003 03:53:55 -0800
Links: << >>  << T >>  << A >>
Im sure this question fills the mind of most PLD users since they mostly end up dealing with DSP/uC for control. 

however, I have been doing plenty of research on this topic, so I thought I should share some of my results 

<note: im a lousy designer as my collegues say, I end up making italian macarony instead of an interface, take the risk if you will> 

Fortunately you can find Processor/FPGA interfaces here on Xilinx-Application Notes, which surely gives an example and some ideas of how you can do it. ther is also an example on interfacing a
monster Pentium Processor to some FPGAs. im sure reading it several times will give you a good clue on your own interface. 

theres 99% chance the FPGA is slave to DSP in your design, in which the main factors that used to determine how the interface will look like were: 

1-DSP access to FPGA data storage? 
2-synchronous/asynchronous data flow? 
3-FPGA mapping on DSP? (ie IS/DS) 
4-number of functions the FPGA will do?, if its a single streamed one, you might try to read FIFO implementations also shown for almost every device in Xilinx Application notes. 
5-FPGA necessary at power-up? you might map the FPGA in two places on the DSP 

--- some examples 
(2) I used both synch/asynch. its obvious that when using asynch you dont need to use the same clock, but i think a number of wait statements in the DSP will improve data transfer. 
when using synchronous design, you need the same clock between the devices. better using PLL/DLL from the DSP to control clock skew. 
--- 
see part (3) this is an important part, I used an interface where the FPGA was mapped on a single IO-port from the DSP, address 7000. I also used a State-Machine in the FPGA to determine
wheather Im storing data,address or command words. this critically decreased the amount of RAM storage I needed in the DSP to map the FPGA. as opposed to typically mapping the whole
FPGA RAM in the DSP RAM and using "paging" methods used when you have more than one external RAM outside the DSP. 
--- 

Id like to hear more discussion on interfacing the FPGA to external devices. please throw in whatever gives inspiration. 

Regards, 
JA 



Article: 53982
Subject: More xilinx webpack verilog questions: always @(clock) legal?
From: Jan Panteltje <panteltje@yahoo.com>
Date: Sat, 29 Mar 2003 18:34:32 GMT
Links: << >>  << T >>  << A >>
Xilinx webpack 4.1, some question:
If  I use:
always  @(clock)
it is optimized away (and subsequently no output at test)..
if I use 
always @(posedge clock)
things work, OK, then you get half the freq at test.

I looked always() up in some verilog tutorial, and it seems to be legal 
to write always @(clock)

So is Xilinx wrong, or am I wrong, or what gives guys?


module lcd_text_driver(clock, text, text_strobe,
        lcd_rst,
        lcd_read_data,
        lcd_e, lcd_rw, lcd_rs,
        lcd_write_data, lcd_dir, test);

input         clock;
output test;

// other in and outputs snipped

reg [7:0] fstate;
reg lcd_initialized;
reg us_clock;
wire test;

// THIS 
//generate micro second clock (from 50 MHz)
//always @(posedge clock)
always @(clock)
begin
fstate = fstate + 1;
if(fstate >= 50)
        begin
        fstate = 0;
        us_clock = !us_clock;
        end 
end // always

assign test = us_clock;
endmodule

look at ..map:

 The signal "clock" is loadless and has been removed.
  Loadless block "clock" (PAD) removed.


Article: 53983
Subject: Re: More xilinx webpack verilog questions: always @(clock) legal?
From: "Stan Zaborowski" <stan@zaborowski.org>
Date: Sat, 29 Mar 2003 14:06:07 -0500
Links: << >>  << T >>  << A >>
If you are doing a simulation, then you should have the code executed on any
change in clock.

If you are doing synthesis, then you will only see changes on either a
posedge or negedge.  Synthesis will only do sensitivity analysis on edges.
It won't do it for just signal changes.

"Jan Panteltje" <panteltje@yahoo.com> wrote in message
news:b64p0p$qe2$1@reader1.tiscali.nl...
> Xilinx webpack 4.1, some question:
> If  I use:
> always  @(clock)
> it is optimized away (and subsequently no output at test)..
> if I use
> always @(posedge clock)
> things work, OK, then you get half the freq at test.
>
> I looked always() up in some verilog tutorial, and it seems to be legal
> to write always @(clock)
>
> So is Xilinx wrong, or am I wrong, or what gives guys?
>
>
> module lcd_text_driver(clock, text, text_strobe,
>         lcd_rst,
>         lcd_read_data,
>         lcd_e, lcd_rw, lcd_rs,
>         lcd_write_data, lcd_dir, test);
>
> input         clock;
> output test;
>
> // other in and outputs snipped
>
> reg [7:0] fstate;
> reg lcd_initialized;
> reg us_clock;
> wire test;
>
> // THIS
> //generate micro second clock (from 50 MHz)
> //always @(posedge clock)
> always @(clock)
> begin
> fstate = fstate + 1;
> if(fstate >= 50)
>         begin
>         fstate = 0;
>         us_clock = !us_clock;
>         end
> end // always
>
> assign test = us_clock;
> endmodule
>
> look at ..map:
>
>  The signal "clock" is loadless and has been removed.
>   Loadless block "clock" (PAD) removed.
>



Article: 53984
Subject: Re: DSP-FPGA interface
From: Mike Treseler <tres@fluke.com>
Date: Sat, 29 Mar 2003 12:25:21 -0800
Links: << >>  << T >>  << A >>
ii wrote:

> What are the best design practices for synchronous design? Do I use the
> same clock for both devices? or different ones? 

Same clock whenever possible

> Use the FPGA's built-in DPRAM or build registers?

Registers are easier if you have them to spare.

  -- Mike Treseler


Article: 53985
Subject: Re: More xilinx webpack verilog questions: always @(clock) legal?
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Sat, 29 Mar 2003 20:33:19 GMT
Links: << >>  << T >>  << A >>
Hi - 

To better understand the problem, ask yourself this: what logic
(gates, FFs) would you expect the synthesizer to emit?  Using the
structures available in a Xilinx part, how would you implement a
counter that clocks on both edges?

Bob Perlman
Cambrian Design Works 

On Sat, 29 Mar 2003 18:34:32 GMT, Jan Panteltje <panteltje@yahoo.com>
wrote:

>Xilinx webpack 4.1, some question:
>If  I use:
>always  @(clock)
>it is optimized away (and subsequently no output at test)..
>if I use 
>always @(posedge clock)
>things work, OK, then you get half the freq at test.
>
>I looked always() up in some verilog tutorial, and it seems to be legal 
>to write always @(clock)
>
>So is Xilinx wrong, or am I wrong, or what gives guys?
>
>
>module lcd_text_driver(clock, text, text_strobe,
>        lcd_rst,
>        lcd_read_data,
>        lcd_e, lcd_rw, lcd_rs,
>        lcd_write_data, lcd_dir, test);
>
>input         clock;
>output test;
>
>// other in and outputs snipped
>
>reg [7:0] fstate;
>reg lcd_initialized;
>reg us_clock;
>wire test;
>
>// THIS 
>//generate micro second clock (from 50 MHz)
>//always @(posedge clock)
>always @(clock)
>begin
>fstate = fstate + 1;
>if(fstate >= 50)
>        begin
>        fstate = 0;
>        us_clock = !us_clock;
>        end 
>end // always
>
>assign test = us_clock;
>endmodule
>
>look at ..map:
>
> The signal "clock" is loadless and has been removed.
>  Loadless block "clock" (PAD) removed.


Article: 53986
Subject: Re: More xilinx webpack verilog questions: always @(clock) legal?
From: Jan Panteltje <panteltje@yahoo.com>
Date: Sun, 30 Mar 2003 00:09:42 GMT
Links: << >>  << T >>  << A >>
On a sunny day (Sat, 29 Mar 2003 14:06:07 -0500) it happened "Stan Zaborowski"
<stan@zaborowski.org> wrote in <v8brkj5djf3vf6@corp.supernews.com>:

>If you are doing a simulation, then you should have the code executed on any
>change in clock.
>
>If you are doing synthesis, then you will only see changes on either a
>posedge or negedge.  Synthesis will only do sensitivity analysis on edges.
>It won't do it for just signal changes.
Thank you!

Article: 53987
Subject: Re: More xilinx webpack verilog questions: always @(clock) legal?
From: Jan Panteltje <panteltje@yahoo.com>
Date: Sun, 30 Mar 2003 00:09:42 GMT
Links: << >>  << T >>  << A >>
On a sunny day (Sat, 29 Mar 2003 20:33:19 GMT) it happened Bob Perlman
<bobsrefusebin@hotmail.com> wrote in
<be0c8vkukf9o2o1uthtdh3gpbo5trmq0li@4ax.com>:

>Hi - 
>
>To better understand the problem, ask yourself this: what logic
>(gates, FFs) would you expect the synthesizer to emit?  Using the
>structures available in a Xilinx part, how would you implement a
>counter that clocks on both edges?
Yes of cause I thought about hat, was also curious what webpack
would do, normally it would not be simple, some xor with some gate delay
in one input would give you pulses on each clock change.
I was sort of hoping the xst would arrange that 4 me...
Hey,  what is the use if simulation runs it and reality (synthesizing)
does not?
Should there not simply be a warning?
Anyways the error report is the webpack makes no sense.
JP

Article: 53988
Subject: Re: Question about case statement in XilinX webpack
From: Jan Panteltje <panteltje@yahoo.com>
Date: Sun, 30 Mar 2003 00:09:42 GMT
Links: << >>  << T >>  << A >>
On a sunny day (28 Mar 2003 16:04:16 -0800) it happened
chopra_vikram@excite.com (Vikram) wrote in
<b6a2818d.0303281604.24b16cba@posting.google.com>:

>Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om> wrote in message news:<b60g8m$g92$1@newsreader.mailgate.org>...
>> Jan,
>> 
>> I am not exactly sure what is causing this problem, but there are there
>> things I don't like with your RTL code.
>> 
>
><snip>
>
>Same here, but would like to go one step further - 
>
>1. It would be nice to seperate the combinational and sequential parts
>into seperate always blocks -
>
>________________________________________________________________________________
>
>always @ (posedge clock or negedge reset_n) 
>begin
>  if (~reset_n)
>    state <= #1 lcd_function;
>  else 
>    state <= #1 next_state ; //will need to define the next state reg
>end
>
>always @(// fill in all signals to which this block is sensitive)
>begin
>  case(state)
>    lcd_idle: .......
>    other states : ......
>    default : ......
>  endcase
>end
>
>________________________________________________________________________________
>
>2. Remember to assign all outputs in all branches of the case
>statement, else you might get unwanted latches inferred.
>
>
>Hope this helps,
>Vikram.
>
Yes it is a cool idea.
Just getting to grip with the verilog and webpack.
LCD is now scrolling all characters.....
Later I will have it report the key if it finds a match in the DES search:-)

Thanks all you people for the help, now for the next problem....
Regards
JP

Article: 53989
Subject: Re: More xilinx webpack verilog questions: always @(clock) legal?
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Sun, 30 Mar 2003 00:45:39 GMT
Links: << >>  << T >>  << A >>
On Sun, 30 Mar 2003 00:09:42 GMT, Jan Panteltje <panteltje@yahoo.com>
wrote:

>On a sunny day (Sat, 29 Mar 2003 20:33:19 GMT) it happened Bob Perlman
><bobsrefusebin@hotmail.com> wrote in
><be0c8vkukf9o2o1uthtdh3gpbo5trmq0li@4ax.com>:

You're right.  It's sunny and nearly 80 degrees here in San Jose.

>>Hi - 
>>
>>To better understand the problem, ask yourself this: what logic
>>(gates, FFs) would you expect the synthesizer to emit?  Using the
>>structures available in a Xilinx part, how would you implement a
>>counter that clocks on both edges?
>Yes of cause I thought about hat, was also curious what webpack
>would do, normally it would not be simple, some xor with some gate delay
>in one input would give you pulses on each clock change.
>I was sort of hoping the xst would arrange that 4 me...

Believe me, the last thing you want is a synthesis tool that creates a
glitch generator to drive the clock line.  This would definitely be a
bug, not a feature.   Using gate delays to generate glitches is not
good design practice.

If you want to use both edges of the clock, instantiate something like
a DCM and use the 2X output.

>Hey,  what is the use if simulation runs it and reality (synthesizing)
>does not?

Anyone who simulates anything must have a healthy skepticism regarding
the results.  There are any number of ways in which simulators can
produce results that differ from the logic that the synthesis tool
emits.  The trick is to learn how to avoid the differences; once
you've done that, simulation is *extremely* useful.

>Should there not simply be a warning?
>Anyways the error report is the webpack makes no sense.

Not having used the Xilinx synthesizer, I can't comment, other than to
say that I would be shocked, shocked to find out that a design tool
generates a, shall we say, enigmatic message.

Bob Perlman
Cambrian Design Works


Article: 53990
Subject: [Question] FPGA/PLX9054
From: "Garrett Mace" <g.ryan@macetech.com>
Date: Sun, 30 Mar 2003 01:23:04 -0600
Links: << >>  << T >>  << A >>
Simple question, for those who've done it before:

How many I/O's are required to implement an interface to PLX9054?

I'm running pretty tight on I/O right now, and this may not be a high-volume
project, so the customer may prefer $18 extra per board as opposed to $2000
for a Xilinx core (still fuzzy on that, you can use and sell the $2000 IP on
one project, right?).

I can get by with the ~50 pins needed for in-FPGA PCI; do I need much more
than that to use a PLX chip?

If I tried to use an open core, do I run up against GNU if I sell the board,
or does simply attributing the core source satisfy licensing?

Ok, that was more than one question.



Article: 53991
Subject: Re: Anyone have difficulty downloading this core?
From: "Arie de Muynck" <no-please@no-spam>
Date: Sun, 30 Mar 2003 11:52:33 +0100
Links: << >>  << T >>  << A >>

"Alex Rast" wrote
> (Arie de Muynck) wrote :
> >Left-click fails.
> >Right-click and "save as..." works.

> Did you check the actual file that was downloaded when you tried this
> technique? You might be in for a surprise. I already tested that
> possibility before posting and discovered that it seems to work, but in
> fact all it did is download the HTML page with the "Forbidden" message.

Yes. A ZIP file with a PIC core and it seems to compile fine at a friend of
mine.
Only the readme.txt is in Japanese ;-(

> FWIW, my environment is as follows:
>
> I'm using a PC-platform (AMD Athlon) computer running Windows 2000. I have
> the NetWare client loaded. Communication to NetWare servers is via IPX
> only, so I use TCP/IP exclusively for the Internet connection. This is
> through a DSL modem, NAT enabled so that the only visible external IP
> address is that of the modem.

Also behind a ADLS+NAT modem on a PII-233 + WIN2K. No IPX in sight here.

> Meanwhile, browser-wise I've tried using both Opera 7.02 and Netscape
4.08.
> I've tried both enabling and disabling cookies, security blocking, etc.

Internet Exploder, latest version, latest patches.

Regards,
Arie de Muynck




Article: 53992
Subject: Re: Anyone have difficulty downloading this core?
From: "Arie de Muynck" <no-please@no-spam>
Date: Sun, 30 Mar 2003 12:15:11 +0100
Links: << >>  << T >>  << A >>
I put a mirror file at:

    www.ademu.com/download/cqpic100c.zip

Regards,
Arie de Muynck



Article: 53993
Subject: Re: How can I fix module inputs
From: mhelshou@yahoo.com (Mohammed Hamed)
Date: 30 Mar 2003 04:58:06 -0800
Links: << >>  << T >>  << A >>
Sorry for that. My ignorance made it seem like an easy task that I
needn't post extra info.

I'm using XESS XSA-50 board containing Xilinx spartan II. I'm using
Webpack 4.2 for development, the Verilog flow.

spam_hater_7@email.com (Spam Hater 7) wrote in message news:<e9486eb9.0303280839.436e89b@posting.google.com>...
> Hi,
> 
> It changes from language to language, and from tool to tool.
> 
> Yes, there is a way to fix the pins in the HDL.  There is also a way
> to fix the pins in the FPGA tool.
> 
> You need to tell us which tools you are using!
> 
> SH
> 
> 
> mhelshou@yahoo.com (Mohammed Hamed) wrote in message news:<e0d0cbd0.0303271013.46580125@posting.google.com>...
> > Hi All,
> > 
> > Sorry I'm new to this. Can I fix a certain input to a module or a
> > certain FPGA pin using constraints file or in HDL code? I want to do
> > this for testing, so that for example when implementing DES encryption
> > I don't have to connect real FPGA pins to logic 1 or 0. Instead I want
> > to fix those pins from the Verilog/VHDL code and reprogram it.
> > 
> > I hope this is not a homework thing, if so just point me to where to
> > look.
> > 
> > Thank you,

Article: 53994
Subject: Re: How can I fix module inputs
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Sun, 30 Mar 2003 13:07:12 +0000 (UTC)
Links: << >>  << T >>  << A >>
Mohammed Hamed <mhelshou@yahoo.com> wrote:
: Sorry for that. My ignorance made it seem like an easy task that I
: needn't post extra info.

: I'm using XESS XSA-50 board containing Xilinx spartan II. I'm using
: Webpack 4.2 for development, the Verilog flow.

Look at the constraint guide for the "LOC" constraint. For the XST flow,
place those constraints in a .ucf file and  connect to your project.

: spam_hater_7@email.com (Spam Hater 7) wrote in message news:<e9486eb9.0303280839.436e89b@posting.google.com>...
:> Hi,

And please, no botoom full quote.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 53995
Subject: Re: [Question] FPGA/PLX9054
From: Peter Wallace <pcw@karpy.com>
Date: Sun, 30 Mar 2003 06:46:16 -0800
Links: << >>  << T >>  << A >>
On Sat, 29 Mar 2003 23:23:04 -0800, Garrett Mace wrote:

> Simple question, for those who've done it before:
> 
> How many I/O's are required to implement an interface to PLX9054?
> 
> I'm running pretty tight on I/O right now, and this may not be a
> high-volume project, so the customer may prefer $18 extra per board as
> opposed to $2000 for a Xilinx core (still fuzzy on that, you can use and
> sell the $2000 IP on one project, right?).
> 
> I can get by with the ~50 pins needed for in-FPGA PCI; do I need much
> more than that to use a PLX chip?
>

50 is more than enough.....
 
> If I tried to use an open core, do I run up against GNU if I sell the
> board, or does simply attributing the core source satisfy licensing?
> 
> Ok, that was more than one question.
 
PCW

Article: 53996
Subject: Help reg Target device & synthesis
From: prasanth_cit@yahoo.com (Prasanth Anbalagan)
Date: 30 Mar 2003 07:15:22 -0800
Links: << >>  << T >>  << A >>
Hai
     I have a problem regarding the synthesis part.I'm using Xilinx
Foundation series 3.1i & I 've set the Taget device family as
XC3000.Device:3020APC68...Speed -6.But the synthesis takes more than
an hour to complete.Is that there is a problem with my code or the
taget device specification ?

Bye
Prasanth

Article: 53997
Subject: Re: [Question] FPGA/PLX9054
From: "Garrett Mace" <g.ryan@macetech.com>
Date: Sun, 30 Mar 2003 12:25:11 -0600
Links: << >>  << T >>  << A >>
> > I can get by with the ~50 pins needed for in-FPGA PCI; do I need much
> > more than that to use a PLX chip?
> >
>
> 50 is more than enough.....
>

Thanks...

Just in the quote stage at this point, and need to know what rabbit holes
not to chase down.



Article: 53998
Subject: Re: Increased Wafer yield by row adjusted placement
From: johnjakson@yahoo.com (john jakson)
Date: 30 Mar 2003 11:57:51 -0800
Links: << >>  << T >>  << A >>
johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0303261957.4fc7f2df@posting.google.com>...
> > 
> > You'd break too many in the process, which nullifies the advantage.
> > Besides, you can't just nilly willy offset the rows against each other
> >...
> > 
> > Achim.
> 


Apparently I was absolutely correct, just didn't know someone else
already doing it.

http://www.waferyield.com/products.html     see WAMA Dies

Next big thing is sharing critical masks onto a fewer, WAMA Mask

That would be somewhere between full wafer & shuttle for the mask
cost, but slightly more expensive stepping.

So someone else got crazy idea before me, I should get more crazy.

Article: 53999
Subject: Re: microblaze gnu tool info ?
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 31 Mar 2003 07:33:40 +1000
Links: << >>  << T >>  << A >>
Muzaffer Kal wrote:
> Hi,
> I guess some people here must be working with Microblaze processors. I
> understand that Microblaze EDK ships with a port of GNU tools. Are the
> sources for these tools available (from the GPL I understand that they
> must be). When one gets the EDK, do you get the sources on the CD ?
> 
Hi Muzaffer,

The EDK runs on top of a modified version of Cygwin, called Xygwin[1]. 
The gnu tools (mb-gcc, mb-ld, etc etc) run within Xygwin.  The source 
for these tools is publicly available for download from Xilinx.  You 
don't need to be an EDK customer to obtain it.

I have a copy here, it's several hundred megabytes.  I looked but can't 
find the place on xilinx's website where I downloaded it.

John

[1] The chances from Cygwin->Xygwin are very small - it's possible to 
make the microblaze tools run under normal cygwin, which is what I'm 
doing here.




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