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Messages from 55775

Article: 55775
Subject: New book on PSL/SUGAR with Verilog and VHDL
From: vhdlcohen@aol.com (ben cohen)
Date: 19 May 2003 11:03:44 -0700
Links: << >>  << T >>  << A >>
I am pleased to announce a new book "Using PSL/SUGAR with Verilog and
VHDL Guide to Property Specification Language for Assertion-Based
Verification" (ISBN 0-9705-3944-4).

This book focuses on the practical use of assertions and use ABV with
PSL in a simulation environment.

  "Any designer wanting to ramp up on ABV in general and PSL in
   particular should read this book"
     - Rahul Razdan, Cadence Design Systems, Inc.

  "Book not only explains the details of the PSL Foundation Language,
   it also walks through PSL applications within an assertion-based
   methodology.  This is a wonderful book that will help the reader
   come up to speed on the emerging PSL standard"
     - Harry Foster, Accellera PSL Formal Verification Technical
       Committee chair.

For book information/purchase see http://www.vhdlcohen.com/
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 
http://www.vhdlcohen.com/ vhdlcohen@aol.com 
Author of following textbooks: 
* Using PSL/SUGAR with Verilog and VHDL
   Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

Article: 55776
Subject: Re: a (PC) workstation for FPGA development
From: fred <not@for.mail>
Date: Mon, 19 May 2003 18:14:05 GMT
Links: << >>  << T >>  << A >>
In article <a688cfa9.0305190101.79cfedaa@posting.google.com>, Tsvika
Hirst <tsvika.hirst@minicom.com> writes
>I need to specify a workstation that will use for FPGA development
>(around 300K gates) i.e. simulate, synth, place and route flow (e.g.
>Foundation ISE + ModelSim XE). I plan to use RedHat Linux, as I was
>told it improves stability and 30% performance relative to
>Windows2000.
>
>I'm trying to set priorities to and find the tradeoffs between:
>Processor:  Single or Dual (e.g. Pentium IV 2.4GHz) 
>HDD type and speed: SCSI or ATA/EIDE (e.g. 18GB SCSI 10,000rpm or
>15,000 rpm vs. 80GB ATA 7200rpm)
>RAM size: 512MB/1GB
I don't think you need to be at bleeding edge of pc technology to get
acceptable results these days. I have used a sub 1GHz box with 256M
RAM to work on a 600k gate design and found it _just_ acceptable. The
same design on a 1.8G Athlon, 512M RAM and 7200rpm ATA100 machine
whizzes along quite merrily, but then again I simulate with Active HDL, not
Modelsim ;-). Next upgrade 1G RAM.

While all designs are different, small simulations take just a few mins,
deep, full chip (600k gate) sim of 250,000 clock duration takes 30mins.
Full chip synthesis, route & timing is 60-90mins.

HTH
-- 
fred

Article: 55777
Subject: Re: about simulation
From: Ralf Hildebrandt <Ralf-Hildebrandt@gmx.de>
Date: Mon, 19 May 2003 20:38:33 +0200
Links: << >>  << T >>  << A >>
Hi "newbie"!


> I designed an fir filter and simulated in quartusII.
> but I found that the function simulation result  differ from the timing
> result.Would someone give me some possible reasons.

Every (real) digital circuit has (real) delays. In behavioral simulation 
only delta-delays are simulated. (Delta-delays are something like 
"infinitesimal short delays".)

In behavioral simulation, it is known, that the result of something like
a<= b OR C;
comes "later". It is modelled to be "infinitesimal later".

After synthesis it is known "how much later" it is. This is a real time.


f'up comp.lang.vhdl


Ralf


Article: 55778
Subject: Re: smallest embedded cpu....and the most pain?
From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Date: Mon, 19 May 2003 19:00:22 GMT
Links: << >>  << T >>  << A >>

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3EC8FDDE.5A313E48@xilinx.com...
> Is $500 really too much money? It's less than one man-day of your cost
> to your employer, and when you figure "lost opportunity cost", spending
> $500 to save an hour or two may look like a good investment.

If its someone else's money, it isn't, but if I am paying it out of my
pocket it is.

Say, for example, that I have an idea for a project.  There is no funding
yet, but I want to try out some ideas to see if they might work.   I might
know someone that would fund it, but I need some proof that the ideas are
reasonable.   In the days when one could sit down with a pad of paper and
draw logic diagrams, things were easier.

-- glen



Article: 55779
Subject: Re: smallest embedded cpu....and the most pain?
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Mon, 19 May 2003 19:01:44 +0000 (UTC)
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote:
: Is $500 really too much money? It's less than one man-day of your cost
: to your employer, and when you figure "lost opportunity cost", spending
: $500 to save an hour or two may look like a good investment. Have you
: looked at what a plumber or a dentist charges per hour, let alone a
: lawyer or a psychiatrist? You may need one after you knitted your own
: cpu  Just kidding....

Mostly procurement processes also take some time, eating up those hours
saved by buying help. It's a complex world ...

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 55780
Subject: Re: Output switching time
From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Date: Mon, 19 May 2003 19:06:41 GMT
Links: << >>  << T >>  << A >>

"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
news:748ya.5354$FJ4.55228@news.chello.at...

>
> I think I don't want to terminate 5-10 mm traces.
> That makes no sense for me.

> We can talk about series resistors to reduce the initial current.
> But this takes to many components and is better achieved by
> using the proper driving strength in the FPGA.

Probably that is fine.  Though be careful when faster devices come out.

There were stories many years ago about DEC specifications for bus drivers
that specified a maximum slew rate, so that they wouldn't have this kind of
problems.  They didn't want them to be too fast, just fast enough.

Anyway, for a tranmission line the series inductance of the wire balances
the capacitance, which is why you don't see it.

-- glen



Article: 55781
Subject: Re: smallest embedded cpu....and the most pain?
From: tom1@launchbird.com (Tom Hawkins)
Date: 19 May 2003 12:12:46 -0700
Links: << >>  << T >>  << A >>
lc wrote:
> 
> What would be the simplest and smallest CPU core for an FPGA ?
> I saw a lot of cores that mimic existing controllers
> but I would not mind to have something simpler.
> Low LE count is my goal.
> 
> P.S. - The application is logic intensive (a very large correlator)
> however the system output happens only once every second.
> Using logic for the output processing become tremendously big,
> a total waist of resources for something that happens only once
> every second.

We recently built an ultra-small processor designed for
hard-real time linear computation.  It's currently being used
as a high speed motion controller implemented on a tiny Altera fpga.

It only has 9 instructions and 16 general purpose registers --
both the data width and the instruction address width are configurable.

There are no conditional branch or jump instructions, so the
processor is not Turing Complete.  However, this does provide for
deterministic program execution time.

Even with only 9 instructions, the processor can do quite a bit with
very little.  Our client using it for motion control has programmed
it to perform a multi-stage CORDIC calculation in front of
the linear control law (adds, multiplies, limiting, decisions, etc.).

The core has a BSD license and can be found at opencores.

  http://www.opencores.org/projects/cf_ssp/

Regards,
Tom


--
Tom Hawkins
Launchbird Design Systems, Inc.
952-200-3790
tom1@launchbird.com
http://www.launchbird.com/

Article: 55782
Subject: Re: FPGA: Feasibility of Memory testing
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 19 May 2003 13:54:04 -0700
Links: << >>  << T >>  << A >>
Henning, 
You can go one step further and do sophisticated and accurate timing
analysis, if you use a Virte-II FPGA, where you can step the clock in 50
picosecond increments.
Just a thought....
Peter Alfke, Xilinx
======================
Henning Bahr wrote:
> 
> Hello there!
> 
> We are working on a project to test memories under high temperature.
> Basically we are placing up to 9 memory chips in an oven, apply test
> patterns and read out the results. The idea is to use an FPGA to
> generate the patterns and employ it to send the output signals further
> to Labview for analysis. This means that the FPGA needs the following
> I/O's:
> 
> - 144 = 9 memories x 16 bit bidirectional data signals
> - approx. 10 address and control signals
> - possibly 16 output signals to connect to the Labview DAQ-board,
> 
> The system should run at a frequency of at least 10 MHz.
> Do you think this is a feasible and reasonable application for an
> FPGA?
> Is it a problem for the FPGA to drive 9 memories in parallel? If it's
> feasible to use an FPGA, which products would be most suitable?
> Many thanks in advance for your help.
> Kindest Regards,
> Henning

Article: 55783
Subject: Re: SID chip describtion
From: "MikeJ" <support@{nospam}fpgaarcade.com>
Date: Mon, 19 May 2003 22:13:33 +0100
Links: << >>  << T >>  << A >>
Try a patent search on it, the original patent is (almost) detailed enough
to write a model.
http://www.delphion.com/details?pn=US04677890__

/MikeJ



Article: 55784
Subject: Re: SID chip describtion
From: "Tim Boescke" <tboescke@uwaterloo.ca>
Date: Tue, 20 May 2003 00:08:37 +0200
Links: << >>  << T >>  << A >>

> Try a patent search on it, the original patent is (almost) detailed enough
> to write a model.
> http://www.delphion.com/details?pn=US04677890__

I know that one, actually it is very far from being detailed enough.
Additional and important information on the digital part of the SID
is available in the interview with Bob Yannes somewhere one the web.
However, there are still open questions about the more analog parts
of the SID.



Article: 55785
Subject: downloading a VHDL design on a XSV board ?
From: bkm_gmps@hotmail.com (vicky)
Date: 19 May 2003 15:39:55 -0700
Links: << >>  << T >>  << A >>
Hello all,
I am trying to download a sequential design with an input size 32
bits.Where as the XSV board has 8 input pins(dip switches) which i can
use.PLease somebody explain me how i can send the inputs to the board?

--vicky

Article: 55786
Subject: verilog question
From: Shalin Sheth <Shalin.Sheth@xilinx.com>
Date: Mon, 19 May 2003 16:03:50 -0700
Links: << >>  << T >>  << A >>
Is there a way to assign the values to a vector in one line of Verilog code?

For exmaple, I know that I can do the following
wire[31:0] den_coeffs [3:0];
wire [31:0] d0 = 32'h3;
wire [31:0] d1 = 32'h1;
wire [31:0] d2 = 32'h4;
wire [31:0] d3 = 32'h1;
assign den_coeffs [3] = d0;
assign den_coeffs [1] =d1;
assign den_coeffs [2] =d2;
assign den_coeffs [3] =d3;

Now can I replace the last 4 lines (the assign statements) with one line 
of Verilog?

Thanks.

Shalin-


Article: 55787
Subject: Re: downloading a VHDL design on a XSV board ?
From: "Jon Beniston" <jon@beniston.com>
Date: Mon, 19 May 2003 23:20:45 GMT
Links: << >>  << T >>  << A >>

"vicky" <bkm_gmps@hotmail.com> wrote in message
news:c0d0455b.0305191439.7caf535c@posting.google.com...
> Hello all,
> I am trying to download a sequential design with an input size 32
> bits.Where as the XSV board has 8 input pins(dip switches) which i can
> use.PLease somebody explain me how i can send the inputs to the board?
>
> --vicky

How about a using one dip switch as a control for a shift register, which
shifts in the the other 7 bits. That should be fun. 5 toggles of that baby
and you're done.

Cheers,
JonB



Article: 55788
Subject: Re: about simulation
From: "Jon Beniston" <jon@beniston.com>
Date: Mon, 19 May 2003 23:24:26 GMT
Links: << >>  << T >>  << A >>

"Ralf Hildebrandt" <Ralf-Hildebrandt@gmx.de> wrote in message
news:baba4t$rgu3k$2@ID-8609.news.dfncis.de...
> Hi "newbie"!
>
>
> > I designed an fir filter and simulated in quartusII.
> > but I found that the function simulation result  differ from the timing
> > result.Would someone give me some possible reasons.
>
> Every (real) digital circuit has (real) delays. In behavioral simulation
> only delta-delays are simulated. (Delta-delays are something like
> "infinitesimal short delays".)
>
> In behavioral simulation, it is known, that the result of something like
> a<= b OR C;
> comes "later". It is modelled to be "infinitesimal later".
>
> After synthesis it is known "how much later" it is. This is a real time.
>
>
> f'up comp.lang.vhdl
>
>
> Ralf
>

To make it work: make sure that the clock period used in the timing
simulation is longer than the minimum clock period (or longest path delay)
as reported by your synthesis tool.

Cheers,
JonB



Article: 55789
Subject: Re: a (PC) workstation for FPGA development
From: Ray Andraka <ray@andraka.com>
Date: Tue, 20 May 2003 01:15:40 GMT
Links: << >>  << T >>  << A >>
A dual processor isn't going to buy any improvement in synthesis, place and route
times, but if you are using the machine for other things too, it wil let you stay
productive while these tasks complete.  The CAE tools are all single threaded, so
they don't take advantage of that extra processor hanging out there.  For a 300K
gate device, you aren't going to be seriously taxing most modern machines.  Fill
up the memory slots before resorting to high speed drives.

Tsvika Hirst wrote:

>
> Please comment on the hardware (single/dual, SCSI/IDE, RAM) priorities
> & tradeoffs

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 55790
Subject: Re: verilog question
From: "Peng Cong" <pc_dragon@sohu.com>
Date: Tue, 20 May 2003 09:35:07 +0800
Links: << >>  << T >>  << A >>
assign {den_coeffs[0],den_coeffs[1],den_coeffs[2],den_coeffs[3]} =
{d0,d1,d2,d3};

"Shalin Sheth" <Shalin.Sheth@xilinx.com> 写入消息新闻
:3EC962D6.7060804@xilinx.com...
> Is there a way to assign the values to a vector in one line of Verilog
code?
>
> For exmaple, I know that I can do the following
> wire[31:0] den_coeffs [3:0];
> wire [31:0] d0 = 32'h3;
> wire [31:0] d1 = 32'h1;
> wire [31:0] d2 = 32'h4;
> wire [31:0] d3 = 32'h1;
> assign den_coeffs [3] = d0;
> assign den_coeffs [1] =d1;
> assign den_coeffs [2] =d2;
> assign den_coeffs [3] =d3;
>
> Now can I replace the last 4 lines (the assign statements) with one line
> of Verilog?
>
> Thanks.
>
> Shalin-
>



Article: 55791
Subject: Re: smallest embedded cpu....and the most pain?
From: <invalid@invalid.com>
Date: Mon, 19 May 2003 21:07:59 -0500
Links: << >>  << T >>  << A >>
(Did I "top post" in this response?)

In article <aR9ya.905669$F1.112483@sccrnsc04>, gah@ugcs says...

> If its someone else's money, it isn't, but if I am paying it out of my
> pocket it is.
> 
> Say, for example, that I have an idea for a project.  There is no funding
> yet, but I want to try out some ideas to see if they might work.   I might
> know someone that would fund it, but I need some proof that the ideas are
> reasonable.   In the days when one could sit down with a pad of paper and
> draw logic diagrams, things were easier.
> 

This is exactly my line of reasoning. In this instance, it would be 
money out of my pocket, not my employer's. Secondly, even though with 
$500 you get the uP/uC(and no long term pricing penalty apparently), 
you're still tied down to a particular FPGA brand/vendor.

> "Peter A" <peter@ wrote in message
> news:3EC8FDDE.5A313E48@xilinx.com...
> > Is $500 really too much money? It's less than one man-day of your cost
> > to your employer, and when you figure "lost opportunity cost", spending
> > $500 to save an hour or two may look like a good investment.
> > Have you looked at what a plumber or a dentist charges per hour, let alone a
> > lawyer or a psychiatrist? You may need one after you knitted your own
> > cpu  Just kidding....

In my case I'm either considering the soft core processors or a 
dedicated processor. This means I'm not re-inventing the wheel, making 
my own core if the existing ones don't work out. I know others here have 
needed to design their own core, but I agree Peter, for a general 
purpose 32-bit RISC machine, creating one from scratch would be a waste 
if you can get one for $500.


Article: 55792
Subject: Re: a (PC) workstation for FPGA development
From: hmurray@suespammers.org (Hal Murray)
Date: Tue, 20 May 2003 02:33:47 -0000
Links: << >>  << T >>  << A >>
>A dual processor isn't going to buy any improvement in synthesis, place and route
>times, but if you are using the machine for other things too, it wil let you stay
>productive while these tasks complete.

Only if you have enough memory for both the CAD tools and whatever
else you want to do.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 55793
Subject: Re: about simulation
From: "newbie" <305liuzg@163.net>
Date: Tue, 20 May 2003 10:38:17 +0800
Links: << >>  << T >>  << A >>
Oh!I got it.
I have neglected the fmax.
thanks.
> To make it work: make sure that the clock period used in the timing
> simulation is longer than the minimum clock period (or longest path delay)
> as reported by your synthesis tool.
>
> Cheers,
> JonB
>
>



Article: 55794
Subject: Re: a (PC) workstation for FPGA development
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Tue, 20 May 2003 02:41:20 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <vcj50bhle8hrff@corp.supernews.com>,
Hal Murray <hmurray@suespammers.org> wrote:
>>A dual processor isn't going to buy any improvement in synthesis, place
>and route
>>times, but if you are using the machine for other things too, it wil
>let you stay
>>productive while these tasks complete.
>
>Only if you have enough memory for both the CAD tools and whatever
>else you want to do.

But if you are swapping, things are going to be miserably slow,
period.


-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 55795
Subject: 8253 vhdl code
From: bhdipu@yahoo.com (dipu bhaskar)
Date: 19 May 2003 22:39:09 -0700
Links: << >>  << T >>  << A >>
i would be thankful if any one could send me a vhdl code for 8253
programmable interval timer.


thanking you
dipu

Article: 55796
Subject: Re: a (PC) workstation for FPGA development
From: Petter Gustad <newsmailcomp5@gustad.com>
Date: 20 May 2003 08:31:31 +0200
Links: << >>  << T >>  << A >>
nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) writes:

> Dual processor has a big advantage: you can get other work done on the
> same system without (mostly) bogging down your CAD flow.  It's a tough
> call.  The other option is a KVM switch and a "dinky system" so you
> can do web browsing or something while waiting for the tools to run.

Personally I think uniprocessor systems gives you best price/
performance. If you run UNIX/Linux you can simply submit your
synthesis and par job into a cluster and free your desktop for
interactive work.

If your tool takes advantage of multiple CPU then it's a different
story. 


Petter
-- 
________________________________________________________________________
Petter Gustad         8'h2B | ~8'h2B        http://www.gustad.com/petter

Article: 55797
Subject: Re: High-Speed Clock & Data Recovery
From: hmurray@suespammers.org (Hal Murray)
Date: Tue, 20 May 2003 07:23:38 -0000
Links: << >>  << T >>  << A >>
>Is there a good way to do clock recovery (from, say, an 8B/10B data stream)
>on a 300Mbps data using a Xilinx without the use of any external PLL or
>analog components?

I haven't seen any responses yet, so I'll toss in my 2 cents...

If you had a clock that was 8x or 10x or 16x the bit rate, then
it's a reasonable state machine to watch the input line and
recover the data bits.  It isn't really clock recovery.  The output
of the state machine is a data-valid flag (clock enable for the
next stage) and the data bit.

It will be obvious after you see it.  Play with graph paper if it
doesn't make sense.  The state is the number of clocks since the
start of the bit cell and the value of the previous data sample.
If you get a transition on clock N, you are still lined up.  If
you get a transition on clock N-1 or N+1, your clocks have
drifted off a cycle and you need to adjust by one.  Clocks in
other slots are errors.  Or maybe your analog section rounded
up/down too much and you have to be more tolerant.

Maybe the state needs another bit for line-dead.  (no carrier,
no transitions recently)

But you don't have an 8x clock.  If you could get 8 samples
staggered by 1/8th of a clock each, then you could write a
state machine that would process 8 samples at a time.  It's
probably easier to think about the 2 samples at a time first.
If you are processing 8 samples/clock you have to worry about
the case where the state machine puts out 2 bits on one clock.

I'm not quite sure how to build that state machine, but it might
be possible.  Perhaps a preprocessor to compress 8 bits to 4 or 5?
(the only legal patterns are stay low, go lo-hi in slot x, go hi
in slot 0 and back lo in slot 7.  And the flips.

Of course, that still leaves the problem of how to capture 8
samples on 1/8th of a clock.  You might be able to do it cleanly
with the new clock stuff - 4 clocks, both edges.

You might be able to do it with an external delay line, say
a trace on a PCB. I think that's about  2 inches between pin.
Probably need to correct for the cap loading.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 55798
Subject: Re: Xilinx Coregen FFT64
From: tempedele@catcha.com (Tempe Dele)
Date: 20 May 2003 00:46:54 -0700
Links: << >>  << T >>  << A >>
Hi all,

I  manage to solve this problem and you're right something wrong in my
Matlab code.

Another problem which I have is that : I repeat the input of my FFT
64, so the data every 64 data sequence [1 set] will be repeated.
[1,2...64,1,2,..,64, ...]

The first 64 sequence from my FFT are correct, and I am expecting the
next 64 sequence will be the same as the first 64 sequence. However,
the 2nd set of FFT output are different.

Any advices ? as I can't do much since it is a coregen.

Thanks.

"Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message news:<p8rejynGDHA.3272@exchnews1.main.ntu.edu.sg>...
> Normally, if the timing diagram has matched with the Xilinx datasheet 
> then it should be alright. Maybe it is the time to check your matlab 
> session.
> 
> Best regards.
> 
> Basuki
> 
> -----Original Message-----
> From: Sandeep [mailto:smukthav@yahoo.com]
> Posted At: Thursday, May 15, 2003 12:17 AM
> Posted To: fpga
> Conversation: Xilinx Coregen FFT64
> Subject: Re: Xilinx Coregen FFT64
> 
> 
> tempedele@catcha.com (Tempe Dele) wrote in message 
> news:<1093bfae.0305131904.5f285af5@posting.google.com>...
> Have you checked to see if the output is bit-reversed (if using
> 2-point butterfly core) or digit-reversed (dragonFly core). I think
> Xilinx uses dragongly core. So the output might be in the
> digit-reveresed order.
> > I have used Xilinx Coregen FFT 64 points using Triple Memory Space
> > (TMS) configuration.
> > 
> > The timing diagram gave me correct information and confirm similar
> > with the timing diagram in the datasheet.
> > 
> > The problem is on the result value, especially the sequence. I compare
> > the result with Matlab calculation. later I found, the value from
> > Xilinx coregen shows weird results. ( I used Modelsim).
> > 
> > e.g : the data value for address 48 is appeared in address 16, data
> > value for address 1 is appeared in address 63.
> > 
> > Anyone has the similar experience ?
> > 
> > pls advice.
> > 
> > Rgds.
> > 
> > Tempe

Article: 55799
Subject: Xilinx : Tools
From: "Vlsi Champ" <vlsi_champ@indiatimes.com>
Date: Tue, 20 May 2003 00:46:55 -0700
Links: << >>  << T >>  << A >>
Hello, 

Can anybody please tell me the difference between the Xilinx ISE (Foundation) tool & Xilinx Webpack tool? The GUI appears to be the same... 

Also if possible, please mention the costwise difference too. 

Thanks in advance, 

Regards, 

Rajesh.... 




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