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Whenever you are chaining two DLL's or DCM's make sure that you get the second DLL's out of reset only after the first one has achieved lock. Preferably after some delay. A xilinx App note concerning the use of DLL's talks about this requirement. In the example they are generating 4x clock using 2 DLL's. I had the same problem generating 4x clock. Now with the delayed reset it works fine. Hope that helps. Brijesh Johan wrote: > Hi > I have a 50 MHz clock that I would like to run in 5 MHz. Thus making it > neccessary to use two clkdlls in serial. > > If I set the generic CLKDV_DIVIDE to 2 or use the default value, 2, the > lock signal appears. But if I use any other valid number than 2 the lock > signal does not appear even though the division of the clock seams ok in > the wavetrace. > > The same problem occurs both in ncsim and modelsim. > > My code and testbench can be found at http://bart.sm.luth.se/~johmat-8/ > > Regards > Johan >Article: 55901
Hi folks,
I haven't used the DCM before, and am just trying something simple -
downsampling a 100MHz clock to, say, 67 MHz.
To complicate matters however, at the same time I'm trying to wrap all
of this into an EDK IP core so I can use it easily in my microblaze
projects.
I basically mapped all of the DCM component generic parameters into
EDK-style parameters, and that all looks fine so far - the problem is
after bitgen completes it says:
WARNING:Bitgen:242 - CLKIN_PERIOD is set to 0 ps which is less than the
minimum
of 2000 ps. The CLKIN_PERIOD is the period of the input clock to the
DCM. The
CLKIN_PERIOD is used by the DCM for frequency synthesis. To set the
CLKIN_PERIOD in the UCF use the syntax: INST "DCM instance name"
CLKIN_PERIOD=X ns;
This happens despite the fact that the vhdl entity is being provided
with a parameter called "CLKIN_PERIOD" for this DCM component, and it
has a value (10.0 in this case).
This suggests to me that the DCM's CLKIN_PERIOD can *only* be expressed
as a constraint, rather than a generic VHDL parameter? If so, that's a
bit of a pain because I don't see how I could then use the EDK parameter
entry dialogs to control this - the user will always have to hand-edit
their ucf file for each project.
Any comments?
Thanks,
John
Article: 55902
I had done a design with QuartusII2.1,fit to EP1K50-3,
and got Fmax at 61MHz.
Today when I try to fit it again with QuartusII 2.2SP2,
I can get Fmax at 58MHz ONLY!
So stupid!!!
leon
Article: 55903Hi Leon, I don't know whether or not anything at all changed about the timing models or optimization techniques for the EP1K devices between these two releases. But the most likely explanation for the "problem" you're seeing is random noise. All place and route algorithms suffer from random noise. It is impossible to solve these NP problems perfectly -- so heuristics and various stoichastic optimization techniques are employed. One by-product of this is that if anything at all changes about the problem -- the netlist, the timing model, the algorithm cost functions, your timing constraints, even the way floating-point numbers are truncated/rounded -- then the algorithms may get different results. To observe this first-hand, make a slight change to your Fmax target (try 59.9, 59.95, 60, 60.05, 60.10). What you should see is a "small" (5-10%???) random variation in final results uncorrelated with your Fmax target. If you do this for both releases of Quartus and average each of the runs, you will probably find that the difference goes away. For some or all devices in Quartus (I honestly don't know :-)) you can back-annote (or save) the placement and routing from one release and import it into the next. This would eliminate the random noise between two releases and limits Fmax changes to those arising from timing models. The down-side of doing this is that you forego any algorithm enhancements between releases as we are constantly improving the quality of place and route, primarily for our newer families. Regards, Paul Leventis Altera Corp. [This is from spammable account] "leon qin" <leon.qin@2911.net> wrote in message news:bak4hi$jjag$1@ID-185326.news.dfncis.de... > I had done a design with QuartusII2.1,fit to EP1K50-3, > and got Fmax at 61MHz. > Today when I try to fit it again with QuartusII 2.2SP2, > I can get Fmax at 58MHz ONLY! > So stupid!!! > > leon > >Article: 55904
Ray Andraka wrote: > Problem is I need 100% compatibility to the MS office stuff, most of my > customers use it and expect me to be able to read/write without hiccups. The > free pdf writer doesn't do so well with graphics, for that the distiller is the > preferred, and for the financial, quickbooks wasn't my choice, it is my > accountant's preference (plus I now have 9 years of business records in > quickbooks, so any new system would have to be able to read quickbooks files). > Yes, there are equivalent functions available for Linux, but not exact > equivalents. I do have a Linux machine running here, so far only for a backup > on a different OS to help guard against a fast moving virus. > > Ben Twijnstra wrote: > >>Hi Ray, >> Most things that can run in win98 will run no problem in win4lin. With win4lin, you install a *real* win98 cd of windoze, then install the windoze apps using the windoze installer like on a 'real' windoze box. The best thing is that when a windoze install reboots the pc, all that happens is that win4lin shuts down and restarts the windoze environment in 5 secs! You can also backup the windoze win4lin environment in linux, so if you break windoze, you can revert to the last backup in a few seconds. I keep my old windoze eprom programmer running in win4lin, which uses the parallel port. Win4lin makes your pc a more tolerable windoze box than a native windoze install! NT or win2k apps won't work unless they're installable in win98.Article: 55905
Thank you Fredrick for your responce. There is one issue that remains unclear: you've described your usage of GERMS monitor on different boards, but as I understand they are all Altera Development Boards. I'm using non-Altera board (without any peripherials whatsoever), and the question is can this cause some troubles in case of GERMS? Is it possible that Altera's dev. boards have some "default" peripherial device that is required by GERMS? (I know that this sounds weird, but I'm really run out of ideas on how to make it work...) Thanks in advance, Yevgeny fredrik_he_lang@hotmail.com (Fredrik) wrote in message news:<77a94d51.0305202311.477f49f7@posting.google.com>... > Hi Yevgeny, > Usally I put the Germs monitor into my bootrom (M4k or ESB depending > if I am using APEX or Cyclone/Stratix) block in the FPGA. This is done > by adding a on-chip memory (RAM/ROM. Then select size to 2kByte and > add content GERMS monitor. When you then do a build the germs monitor > will be compiled and put into this memory content. Germs do not need > FLASH to function and I can help with storing sw into exteral flash > but can also be used to start your own SREC files. > Cheers > Fredrik > > > syevgen1@hotmail.com (Yevgeny K.) wrote in message > news:<6c3628cf.0305201149.15e36883@posting.google.com>... > > Hello all. > > > > We are using Altera NIOS CPU with non-Altera PCI card with Altera FPGA > > (Gidel PROC20K board without flash memory). > > We are trying to use GERMS monitor, but it doesn't work - the "nios-run" > > script doesn't find a target (no responce from the GERMS). > > All the "hardware" was checked over and over - it's OK for sure. > > We looked at the GERMS source code, and it looks like it requires flash > > memory to exist and the program that GERMS receives is uploaded to flash, > > so this maybe the explanation why in our case (no flash on board) it > > doesn't work. > > The question is, can the GERMS monitor be somehow "reconfigured"? > > In other words, can we make it work somehow without flash, by uploading the > > program to the RAM on the FPGA itself? > > Has anybody tried something like this? > > > > Thanks in advanceArticle: 55906
Ray Andraka wrote: > Perhaps, but it is different from the more traditional software in that there > are concurrency and timing issues that do not apply for traditional software. > The design flow is hardware, the result is perhaps software. For that reason, > it does make sense to differentiate it. I am constantly fighting the problems > introduced by people treating the FPGA contents as software when they do their > designs, and we see a fair amount of the results of that mentality here too. If > for no other reason than to avoid that leap, I think it is prudent to call it > something other than software. Seems to me (as a software guy who dabbles :-) that it's much of a muchness. The issues you raise seem similar (to me) to the concurrency issues with parallel languages... Even (elementary) multithreaded programming needs synchronisation between functional blocks, and timing certinly rears its' ugly head. I read the above opinion a lot on these newsgroups. Either I don't understand the issues (and am hence guilty as charged :-)) or it's like saying that arts and science don't mix. It's possible to be (do) both... It took me a few hours to learn verilog syntax, (it took me about a day to decide I prefer the concise nature of verilog over the verbose nature of VHDL :-). Understanding the basics of what you're doing when you write an HDL description of h/w took another day or so. I've never had the time to get into the "deep voodoo" of mastering the various "extra bits" (the details of the CLB logic, various randomly-labelled [grin] inputs and outputs to the CLB's etc.) but I doubt it's beyond me. Frankly I've not needed it yet - I started playing with FPGA's when they became cheap and powerful - my largest project to-date has been a jpeg encoder, which fits quite easily into a 300k Spartan-2. I guess I've been spoilt :-) I can see there *are* times when you'd need this sort of knowledge, and there has to be a "yes!" feeling to doing something neat within the hardware restrictions... I've done h/w design at college (I'm a physicist, for my sins), and I've written device-drivers for hardware cards, so perhaps I had a head start, but it doesn't seem any harder to mentally map blocks of HDL code and consider their interactions, than to mentally map competing and co-operating threads / processes within a (single or multiple CPU) s/w environment and consider *their* interactions... OTOH, a basic C programmer would probably feel all-at-sea when presented with an HDL source :-) Just my thoughts. Simon.Article: 55907
Hi, I am using a FPGA to interface the signals between 2 ICs. One IC (transmitter) will transmit the signals through the FPGA to another IC (Receiver). These signals are synchronous and have different timings (setup and hold time) between the ICs. So if the signals pass through the FPGA directly, there will be setup and hold time violation issues. So the only way to fix this is to add some control to the signals, any ideas/algorithms ? Any suggestion is welcome, thanks !Article: 55908
> >Are you using XP? How did you get it working? I'm using XP and for now I am rather glad. I had to wait for Maxplus2 ver 10.2 because of Bateblaster drivers (in v10.1 are only for win2k and NT). I dont install Quartus Web v2.2 but i downloaded it and in free time i will try it. I work with 512MB and this is minimum, OS takes a lots of memory.... :( Regards, PawelT Pozdrawiam, PawelTArticle: 55909
You may (or may not) be interested in ESA's definition of firmware in ECSS-P-001 (www.ecss.nl) which I presume is derived from the definition in ISO/IEC 9126:1991 Firmware : Hardware that contains a computer program or data that cannot be changed in its user environment. The computer program and data contained in firmware are classified as software; the circuitry containing the computer program and data is classified as hardware (ISO/IEC 9126:1991). It is not really clear to me wether they mean to include FPGAs in this definition. If you then read ECSS-Q-80 Space product assurance - Software product assurance and ECSS-E-40 Space engineering - Software they seem extremely "computer" software biased. They don't say much more than "Software includes the software component of firmware" and a few lines about device programming in ECSS-Q-80. Kate "Joe Frese" <joefrese@hotmail.com> wrote in message news:c176b8c2.0305211126.6e642649@posting.google.com... > I've got a question of terminology for the group: is FPGA design > generally classified as hardware, firmware, or neither? Most of the > designs I've worked on have served to interface firmware with > hardware. It seems that firmware engineers like to think of FPGA > designs as more firmware, and that hardware engineers like to think of > FPGA designs as more hardware. As an FPGA developer, though, I'm of > the mind that the unique design considerations of the technology > justify a new and separate category . . . > > A coworker suggested the term "coreware," but apparently that's a > registered trademark of LSI Logic. Is there another term with the > -ware suffix commonly used to refer to code (VHDL, Verilog, or > otherwise) intended to be implemented in an FPGA? > > JoeArticle: 55910
Hi Markus
What about the syntax example given in the Constraint Guide?
attribute uselowskewlines: string;
attribute uselowskewlines of signal_name: signal is "yes";
Regards
Francisco Rodriguez
================================================================
Francisco Rodriguez Ballester (prodrig@disca.upv.es)
Postal address: Dept. DISCA, EUI - Univ. Politecnica de Valencia
c/Camino de Vera s/n, E-46022, VALENCIA (SPAIN)
tlf: +(34) 96 387 70 07 ext. 75759 - fax: +(34) 96 387 75 79
================================================================
"Markus Meng" <meng.engineering@bluewin.ch> escribió en el mensaje
news:3ecdeeb7$1_8@corp.newsgroups.com...
> Hi all,
>
> I would like to add design attributes for the use of the attributte:
>
> USELOWSKEWLINES
>
> Adding this tho dedicated reset and clock lines within the design
> hierarchy, doesn't seems to take effect during P&R.
>
> What I managed so far is to add this attribute for signals that route
> to an IOB. This works as expected. However I don't want to
> specify a netname - from the design hierarchy - within the UCF File.
> There must be a way to specify within the VHDL code that this net must be
> routed using a low skew line.
>
> A hint or a tipp would be appreciated. Thank's in advance.
>
> Best Regards
> Markus Meng
>
> --
> Mit freundlichen Grüssen
> Markus Meng
>
> P.S. Achtung wir haben eine neue FAX-Nummer
> ********************************************************************
> ** Meng Engineering Telefon 056 222 44 10 **
> ** Markus Meng Natel 079 230 93 86 **
> ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! **
> ** CH-5400 Baden Email meng.engineering@bluewin.ch **
> ** Web www.meng-engineering.ch **
> ********************************************************************
> ** You cannot create experience. You must undergo it. Albert Camus**
>
>
>
>
>
>
>
> -----= Posted via Newsfeeds.Com, Uncensored Usenet News =-----
> http://www.newsfeeds.com - The #1 Newsgroup Service in the World!
> -----== Over 80,000 Newsgroups - 16 Different Servers! =-----
Article: 55911syevgen1@hotmail.com (Yevgeny K.) wrote in message news:<6c3628cf.0305222258.7e39a6c5@posting.google.com>... Hi Yevgeny, You are right in your assumption I have all Altera Nios dev boards. The only default device you need for GERMS (if I am not misstaken) is a UART to send and revive commands over. Cheers Fredrik > Thank you Fredrick for your responce. > There is one issue that remains unclear: you've described your usage > of GERMS monitor on different boards, but as I understand they are > all Altera Development Boards. > I'm using non-Altera board (without any peripherials whatsoever), > and the question is can this cause some troubles in case of GERMS? > Is it possible that Altera's dev. boards have some "default" peripherial > device that is required by GERMS? > (I know that this sounds weird, but I'm really run out of ideas on > how to make it work...) > > Thanks in advance, > Yevgeny > > fredrik_he_lang@hotmail.com (Fredrik) wrote in message news:<77a94d51.0305202311.477f49f7@posting.google.com>... > .. snipArticle: 55912
Hi all, I would like to add design attributes for the use of the attributte: USELOWSKEWLINES Adding this tho dedicated reset and clock lines within the design hierarchy, doesn't seems to take effect during P&R. What I managed so far is to add this attribute for signals that route to an IOB. This works as expected. However I don't want to specify a netname - from the design hierarchy - within the UCF File. There must be a way to specify within the VHDL code that this net must be routed using a low skew line. A hint or a tipp would be appreciated. Thank's in advance. Best Regards Markus Meng -- Mit freundlichen Grüssen Markus Meng P.S. Achtung wir haben eine neue FAX-Nummer ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ** Web www.meng-engineering.ch ** ******************************************************************** ** You cannot create experience. You must undergo it. Albert Camus** -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 55913
Hi Patrik! Thank you. It did solve the problem if I connected CLK2x to CLKFB through a BUFG. The funny (?) part is that the divison worked with CLKDIV connected to CLKFB if I divided with 2. It even worked if I divided the clock again, thus making it a division by 4 from the original clock. Regards JohanArticle: 55914
A basic "noise" generator would be a long (relative to the bandwidth you need to cover) length LFSR. Xilinx has an app note on how to fit these into a remakabply small area using SRL16's, but it can be done on any chip. Then feed it to one input of a mixer and feed a tone onto another. What you're doing is creating a random BPSK modulated signal whose bandwidth is controlled by the clock speed of your LFSR. I believe this is a decent approximation of Gaussian noise for many applications. I'd be interested if there are easy methods of creating nondeterministic random binary numbers, either in an FPGA, or through a few pin connections. --Josh MIT/LL "Peter Alfke" <peter@xilinx.com> wrote in message news:3ECD5DAD.181EFB65@xilinx.com...> You have to be more specific. > What kind of noise spectrum, what frequencies? > And what is the application? > Peter Alfke > ========== > Klix wrote: > > > > Hi > > > > I'm looking for project of nois generator in Xilinx. > > > > Kind regards.Article: 55915
PawelT wrote: >> Are you using XP? How did you get it working? > > I'm using XP and for now I am rather glad. > I had to wait for Maxplus2 ver 10.2 because of Bateblaster drivers (in > v10.1 are only for win2k and NT). Yes, that must be the problem because I've only got the Maxplus2 v9.23 off the CD-ROM and it won't recognise files properly. I've tried downloading the newer version off the net but it's a big file and I've got a 56k modem and my ISP cuts me off after 2 hours which makes it impossible to download it in time. :( I think I might ring up Altera in the UK to see if they'll send me a CD. -- DAB sounds worse than FM, Freeview, Digital Satellite and Cable -- http://www.digitalradiotech.co.uk/ Subscribe for free to the Digital Radio Listeners' Group NewsletterArticle: 55916
IF you've successfully dabbled with hardware, you certainly are ahead of the game.
Software folks who understand basic digital hardware are relatively scarce. I've run
into many that have a lot of difficulty designing hardware because they are writing
the VHDL like software with no consideration of what the circuit they are creating
might be. A common trouble encountered with software folks doing hardware is the
concept of propagation delays and how that affects the design timing.
Simon wrote:
> Ray Andraka wrote:
> > Perhaps, but it is different from the more traditional software in that there
> > are concurrency and timing issues that do not apply for traditional software.
> > The design flow is hardware, the result is perhaps software. For that reason,
> > it does make sense to differentiate it. I am constantly fighting the problems
> > introduced by people treating the FPGA contents as software when they do their
> > designs, and we see a fair amount of the results of that mentality here too. If
> > for no other reason than to avoid that leap, I think it is prudent to call it
> > something other than software.
>
> Seems to me (as a software guy who dabbles :-) that it's much of a
> muchness. The issues you raise seem similar (to me) to the concurrency
> issues with parallel languages... Even (elementary) multithreaded
> programming needs synchronisation between functional blocks, and timing
> certinly rears its' ugly head.
>
<stuff snipped>
>
> I've done h/w design at college (I'm a physicist, for my sins), and I've
> written device-drivers for hardware cards, so perhaps I had a head
> start, but it doesn't seem any harder to mentally map blocks of HDL code
> and consider their interactions, than to mentally map competing and
> co-operating threads / processes within a (single or multiple CPU) s/w
> environment and consider *their* interactions...
>
> OTOH, a basic C programmer would probably feel all-at-sea when presented
> with an HDL source :-)
>
> Just my thoughts.
>
> Simon.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55917>I've tried downloading the newer version off the net but it's a big file and >I've got a 56k modem and my ISP cuts me off after 2 hours which makes it >impossible to download it in time. :( maybe some kind of dowload manager can help, if the connection is beak. I use flashget, but (fortunately) i've got "permanent" connection to the Internet. > >I think I might ring up Altera in the UK to see if they'll send me a CD. Try to subscribe Digital Library from Altera - there is a Baseline, and other digital data. Or just call to lokal representative, or other firm with sell software for digital circuits. Regards, PawelT Pozdrawiam, PawelTArticle: 55918
Describing hardware with text doesn't make it software.... To me, the big difference is that a software designer describes the behavior he wants. That behavioral description is turned into instructions to be executed by pre-defined hardware. A hardware designer takes the same problem and solves it by describing the hardware that he wants. He could describe that hardware with a schematic for ICs on a PCB, a schematic for a FPGA, HDL for a FPGA, or whatever. It doesn't matter, he's still describing the same hardware. The FPGA (or CPLD) just gives us a way to implement that hardware without using a solding iron to make changes :)Article: 55919
Hi everybody,
Please help,
I design the behvioral below wich contains a simple multiplication
between a signal and a constant;
My behavioral is :
entity mult is
Port (a : in INT16; clk : std_logic; s : out INT16 );
end mult;
architecture Behavioral of mult is
constant alpha INT16 := 123;
begin
mul: process(clk)
begin
if clk'event AND clk='1' then
s<=a*alpha;
end if;
end process mul;
end Behavioral;
I use xilinx ISE 5.2 with XST to synthesis it and Modelsim to simulate
it.
The behavioral simulation is good, but the post-map simulation is
totally wrong.
A part of my HDL Synthesis Report is::
Macro Statistics
# Registers : 1
16-bit register : 1
# Multipliers : 1
16x8-bit multiplier : 1
I think that after the synthesis my positive constant 123=(1111011)b
is sign extended on 16 bits to use 16*16 bits multiplier and the
value 1 is extended on MSB rather than 0.
Note that I want to use lut or block multiplier of the Virtex. I give
this simple design to light up the synthesis problem of constant
mapping on signed multiplier.
WHAT KIND OF SOLUTION IN VHDL EXIST TO REALLY FIX THE BIT WIDTH OF A
CONSTANT TO AVOID THE PROBLEM OF SIGN EXTENTION??
I wich I expose my problem clearly
Regards,
Jean Philippe,
Article: 55920
Well said.
Synthesis can and does increase the level of abstraction, which tends to
hide the hardware details from the designer. Because of that, the design
can start to look like software in the context you describe below. With
that in mind, the state of 'hardware compilers' is about where we were
with software in the early '80s (when there was a lot more assembly level
programming than there is now). I submit that the move to higher levels
of abstraction in software has led to the current state of affairs where a
word processor occupies many MB's of memory. I recall having very real
limits not so long ago of only a couple KB of memory and only paper tape
for storing programs.
Brian wrote:
> Describing hardware with text doesn't make it software....
>
> To me, the big difference is that a software designer describes the
> behavior he wants. That behavioral description is turned into
> instructions to be executed by pre-defined hardware.
>
> A hardware designer takes the same problem and solves it by describing
> the hardware that he wants. He could describe that hardware with a
> schematic for ICs on a PCB, a schematic for a FPGA, HDL for a FPGA,
> or whatever. It doesn't matter, he's still describing the same
> hardware. The FPGA (or CPLD) just gives us a way to implement that
> hardware without using a solding iron to make changes :)
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55921Josh Model wrote: > I'd be interested if there are easy methods of creating nondeterministic > random binary numbers, either in an FPGA, or through a few pin connections. > Josh, thanks for the constructive tutorial information. I think ( nor being a real expert) that LFSRs are good enough for generating randomness in the physical world, but not good enough to fight an intelligent attacker (crypto). Still, one can use two relatively LFSRs of different length and XOR their outputs, to make it "more random". The LFSRs need not be long, but should be run fairly fast. Ideal application of an FPGA. See: http://www.xilinx.com/xapp/xapp052.pdf Peter Alfke, XilinxArticle: 55922
There is really no difference with your description and what happens with a FPGA. You write a behavior and this is turned into low level programming bits. These bits are then loaded into an electronic system in such a fashion that your behavior is implemented. Believe me the FPGA is just as much pre-defined hardware as is a processor. You can't change the transistors on the die. The fact that the jargon and methods of hardware design was first used to program them does not make FPGAs any less of a programmable device. It is all about the definition. Programming: Writing a behavior for a system. Are you programming when you write Verilog or VHDL? I think so. I could write a compiler that would take Verilog or VHDL and run it on a processor. Doesn't this make it software? I can take C code and run it on a FPGA. When did I stop writing software? What Verilog and VHDL don't have is, the ability to describe dynamic processes that allow for the creation of logic and interconnection. In the C/processor world I can use the resources (mainly memory) in the system any way I want any time I want. I can alloc memory or create a pipe to something or call on other precompiled units to be loaded. I can run subroutines and even create object code on the fly. You can do the same things with FPGAs it's just not easy. When FPGAs are designed that do things like fetch their own configurations, at a time other than boot time, then it will be easier to write C/C++ compilers for them. It's just a matter of time.... Steve "Brian" <usenet@carlsonclan.com> wrote in message news:bv8scv04vafonm72orb3aa92gqi29hg96u@4ax.com... > Describing hardware with text doesn't make it software.... > > To me, the big difference is that a software designer describes the > behavior he wants. That behavioral description is turned into > instructions to be executed by pre-defined hardware. >Article: 55923
Hi all, In addition, with Nios 3.0 (and higher) there is an on-chip debug module that supports stdout communication (sort of like a UART) through the JTAG pins. So, to implement a minimal Nios system (running GERMS) that the user can interact with, a UART *or* the OCI debug module is needed. I suggest checking out any designs labeled "minimal" in the Nios kit - these do not use any external memory, but do have the GERMS monitor as the program which boots. These designs are board independent - just re-assign pins such as clock, reset, and txd/rxd (for a UART) and you're ready to go. Jesse Kempa Altera Corp. jkempa at altera dot com fredrik_he_lang@hotmail.com (Fredrik) wrote in message news:<77a94d51.0305230248.6c889bba@posting.google.com>... > syevgen1@hotmail.com (Yevgeny K.) wrote in message news:<6c3628cf.0305222258.7e39a6c5@posting.google.com>... > > Hi Yevgeny, > You are right in your assumption I have all Altera Nios dev boards. > The only default device you need for GERMS (if I am not misstaken) is > a UART to send and revive commands over. > Cheers > FredrikArticle: 55924
hi There is only one problem because I'm totally beginers and i have no any ideas. In conditions i have to use C/A converter ZN-426 and EPROM 2764. Have you any example??? Kind regards U¿ytkownik "Klix" <embnet@tlen.pl> napisa³ w wiadomo¶ci news:bajao6$kil$1@korweta.task.gda.pl... > Hi > > I'm looking for project of nois generator in Xilinx. > > Kind regards. > >
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