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Messages from 58125

Article: 58125
Subject: Virtex-II Pro family is a hands-down winner for DSP
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Tue, 15 Jul 2003 07:49:18 -0700
Links: << >>  << T >>  << A >>
Michael,

No tricks.  V2 Pro parts are available NOW (for most devices and packages)
and they do have Xtreme DSP (tm) capabilites that are pretty awesome.

Your Xilinx FAE would be happy to provide you with a loaner demo board
that you could play with (or you could obtain one of your own through
distibution or order one on-line).

Depending on what you are doing, Virtex 2 Pro usually beats any other part
in terms of performance.  There are some DSP apps where Stratix is better,
but these are ones that can take advantage of the 9X9 multiplier mode.
There are some filter architectures that work better on STratix, than on
our parts, but in any digital filter, there is more than one possible
realization (IIR, FIR, folded, non-folded, etc.).  Our literature suggests
those architectures that are best fits for our parts, so apples to apples
comparison must be carefully done (do not use the wrong architecture with
the wrong part -- in either case, or else the comparison will be flawed).

The one issue (catch) that is raised is usually power:  all those
multipliers are not working for free.  But we use worst case patterns to
define our power estimate, as opposed to a typical pattern power estimate,
so again, Caveat Emptor (buyer beware), as the real power dissipation
between the two is actually almost identical (after all, similar 18X18
multipliers in the same technology draw the same power for the same speed
or performance).

Glad you have taken a serious look at our products,

Austin

Michael S wrote:

> I know that respective regulars of this newsgroup don't like to give
> decisive answers to A vs. X type of questions, but... This last visit
> of the Xilinx representative was a shocker !
>
> A bit of the background. We are as pure Altera shop as it goes. As
> such we don't follow Xilinx products very closely. When we
> occasionally did the check we typically found out that for our
> applications there are no big differences between offerings of Xilinx
> and Altera so there was no reason to step out of the comfort zone of
> established routine. We believed that this situation will last forever
> - it's what the competition is invented for, isn't it ?
>
> I have to mention that up until recently we never faced the project
> that was very multiplication-intensive on its FPGA side. The project
> we are  trying to achieve now is exactly like this- very multiply
> (MAC) intensive almost 100% FIR filtering. As usual, initially we
> figured out a possible Altera solution. It was a bit pricey and
> required two (or four smaller) chips but we thought that it is the
> state of the art and so be it. But here come a representatives from
> Xilinx and showed as their Virtex-II Pro parts... As I mentioned above
> it was a shock: about three time as many multipliers as in similar
> size/similar price Stratix chip. Two and a half times more multipliers
> than in significantly bigger Startix chip !
> XC2P30 - 136 18x18 Dedicated multipliers
> EP1S30 - 48  18x18 Embedded multipliers (the price of the parts is
> similar to XC2P30)
> EP1S40 - 56  18x18 Embedded multipliers
>
> I suppose that Startix parts are a bit faster, but it doesn't make a
> difference for our application. Doing the computational part of the
> design in the distinct (faster) clock domain doesn't make much sense
> when the main (data acquisition) clock already runs at 190MHz. And for
> 190MHz VirtexII-Pro is o.k. For us as far as Stratix unable to run
> calculation at 380MHz its speed advantage doesn't care.
>
> Since I have no experience with Xilinx in general and with Virtex-II
> Pro in particular I am afraid I missed something. It's almost too good
> to be true. IMHO if there is no catch (availability ?) here the XC2P
> parts draws Stratix into irrelevance for nearly all DSP-intensive
> applications.


Article: 58126
Subject: Re: programming a PLD/CPLD with a PIC?
From: fpgaguy@aedinc.net (Jason Daughenbaugh)
Date: 15 Jul 2003 07:58:06 -0700
Links: << >>  << T >>  << A >>
Javier,

We have done just exactly what you are describing with motorola MCUs
as well as with the Xilinx Picoblaze processor.  We have used the XSVF
file format provided by xilinx (basically a dense way to store an
SVF).  I am sure this isn't the most efficient way (SVFs are
play-and-check only), but it was very easy to put together due to the
info & code provided by Xilinx.

Check out xilinx app notes including XAPP058, XAPP503, and XAPP102.  I
think that there are more too.

For reference, the XSVF for an XC9572XL is ~29KB.  We have always used
either external memory or a comms link such as a serial port to
provide the XSVF file.

My favorite application for this is to use a Xilinx Picoblaze in an
FPGA to reprogram the configuration sprom and reboot.  The picoblaze
is tiny, and with no added hardware (except for the expensive
reprogrammable sprom) you can have a system that is reconfigurable. 
All you need is a way to send an XSVF to the FPGA.  Of course there is
the scary period during programming where if it is interrupted the
whole system is broken until an external JTAG programmer is used to
fix it, but this is acceptable for many of our products / clients.

Jason Daughenbaugh
http://www.aedbozeman.com


javodv@yahoo.es (javid) wrote in message news:<c10cd8da.0307140345.f0999e@posting.google.com>...
> Hello to All,
> 
> I was wondering if it is possible to program a PLD/CPLD via a PIC
> (without connecting external memory). The PIC I am using has a
> internal RAM of 768 bytes and 16k of flash. I have seen some app.notes
> from Altera/Xilinx/Lattice but I think that I need a more powerful
> micro for doing the CPLD reprograming with it. Is there any new small
> CPLD easy to reprogram?. I would appreciate any suggestion or link.
> 
> Thanks a lot and best regards,
> 
> Javier

Article: 58127
(removed)


Article: 58128
Subject: what are libraries for??
From: "Michael Nicklas" <michaeln@nospam.slayer.com>
Date: Tue, 15 Jul 2003 16:37:43 +0100
Links: << >>  << T >>  << A >>
Hi

no funnies about books please!!

What are libraries used for in HDL's?

Simulation or Synthesis or both?

Or is this a stupid question and shall I get my coat?

--
Cheers!

Mike



Article: 58129
Subject: Re: PROM size for spartan
From: Bruce Jorgens <bruce.jorgens@xilinx.com>
Date: Tue, 15 Jul 2003 09:11:21 -0700
Links: << >>  << T >>  << A >>
Gabriel,

The size of the bitstream required to configure the FPGA does not change as
you use more of the FPGA resources.  Based on the 89% full PROM, I assume you
are using the XC2S300E device.  As you exploit more of the FPGA your PROM will
stay 89% full so there is no need for you to use a larger PROM.

If you want the lowest cost, smallest boardspace solution, you should look at
our recently released Platform Flash family of configuration PROMs.  The
XCF02S is available now and will configure your XC2S300E.  You can find the
cross-reference to Spartan-IIE at:

http://www.xilinx.com/isp/compfpgatables/pfp_spartan.htm

Bruce Jorgens

"..:: Gabster ::.." wrote:

> The size of the PROM recommended for each Spartan model is shown here:
> http://www.xilinx.com/isp/compfpgatables/prom_spartan.htm
>
> Why can't I use a 4Mb PROM with my Spartan IIE FPGA. Right now, on a 2Mb
> (the recommended one), the PROM is 89% full but the FPGA is far from being
> completly exploited.
>
> thanks,
> Gabriel


Article: 58130
Subject: Re: JTAG standard connector
From: brad@tinyboot.com (Brad Eckert)
Date: 15 Jul 2003 09:17:55 -0700
Links: << >>  << T >>  << A >>
"..:: Gabster ::.." <gabsterblue@hotmail.com> wrote in message news:<8DMQa.38230$O55.885629@wagner.videotron.net>...
> Hi,
> 
>     I'm making a pcb with a xilinx FPGA. I will obviously put a JTAG header
> on my board. I simply want to know what is the standard pinout for the
> header. Looking a the specs for the Parallel IV cable from xilinx I found
> the following pinout:
> 
> 14 NC    13 GND
> 12 NC    11 GND
> 10 TDI    9 GND
> 8 TDO    7 GND
> 6 TCK    5 GND
> 4 TMS    3 GND
> 2 Vref     1 GND
> 
> However, my evaluation board from burchED doesn't feature the same pinout:
> 
> 1 TDI    2 TDO
> 3 TCK    4 TMS
> 5 NC    6 NC
> 7 GND    8 VCC
> 9 NC    10 NC
> 
>  Conclusion, I don't know what to use. The pinout from xilinx seems space
> wasteful. What would you put on your board?
> 
> thanks,
> Gabriel

If you're looking for some kind of defacto standard, Altera's
Byteblaster pinout is used by both Altera and Atmel. Look up
byteblaster on the web.

Article: 58131
Subject: Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 15 Jul 2003 12:33:25 -0400
Links: << >>  << T >>  << A >>
Michael S wrote:
> 
> I know that respective regulars of this newsgroup don't like to give
> decisive answers to A vs. X type of questions, but... This last visit
> of the Xilinx representative was a shocker !
> 
> A bit of the background. We are as pure Altera shop as it goes. As
> such we don't follow Xilinx products very closely. When we
> occasionally did the check we typically found out that for our
> applications there are no big differences between offerings of Xilinx
> and Altera so there was no reason to step out of the comfort zone of
> established routine. We believed that this situation will last forever
> - it's what the competition is invented for, isn't it ?
> 
> I have to mention that up until recently we never faced the project
> that was very multiplication-intensive on its FPGA side. The project
> we are  trying to achieve now is exactly like this- very multiply
> (MAC) intensive almost 100% FIR filtering. As usual, initially we
> figured out a possible Altera solution. It was a bit pricey and
> required two (or four smaller) chips but we thought that it is the
> state of the art and so be it. But here come a representatives from
> Xilinx and showed as their Virtex-II Pro parts... As I mentioned above
> it was a shock: about three time as many multipliers as in similar
> size/similar price Stratix chip. Two and a half times more multipliers
> than in significantly bigger Startix chip !
> XC2P30 - 136 18x18 Dedicated multipliers
> EP1S30 - 48  18x18 Embedded multipliers (the price of the parts is
> similar to XC2P30)
> EP1S40 - 56  18x18 Embedded multipliers
> 
> I suppose that Startix parts are a bit faster, but it doesn't make a
> difference for our application. Doing the computational part of the
> design in the distinct (faster) clock domain doesn't make much sense
> when the main (data acquisition) clock already runs at 190MHz. And for
> 190MHz VirtexII-Pro is o.k. For us as far as Stratix unable to run
> calculation at 380MHz its speed advantage doesn't care.
> 
> Since I have no experience with Xilinx in general and with Virtex-II
> Pro in particular I am afraid I missed something. It's almost too good
> to be true. IMHO if there is no catch (availability ?) here the XC2P
> parts draws Stratix into irrelevance for nearly all DSP-intensive
> applications.

As soon as you start comparing chips based on price (which is normally
the most useful measurement) you have to validate your prices.  For
example, I have been trying to get a reasonable 1Q04 price on a Spartan
3 part and they are just not giving out that info yet.  They will give
you a price, but it will be twice the price of a Spartan IIE part which
is obviously not what they will sell for when production is in full
swing.  

I have found from personal experience that if you make them compete for
the socket you can get the price significantly lower.  So you may be
getting a really, really good price from Xilinx who wants to "buy" your
socket.  But it is likely that Altera does not know you are shopping it
around and you can get a lower price on their parts.  

I only hope Lattice becomes a major player in this market.  I think
three is the magic number for mainstream FPGA vendors.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 58132
Subject: Virtex II Pro Exceptions
From: Jon Masters <jonathan@jonmasters.org>
Date: Tue, 15 Jul 2003 17:37:44 +0100
Links: << >>  << T >>  << A >>
Hi,

I am attempting to execute the following code:

	tlbwe    r4,r40,1

Which is correctly dissassembled as:

	7c 80 0f a4    tlbwelo r4,r0

However at run time an unexpected Program Interrupt (0x0700) occurs with 
the reason given in the ESR (0x8000000) of ``Illegal Instruction''.

This is on a development board containing a Xilinx Virtex II Pro which 
otherwise is running our code normally until this point.

Any suggestions are appreciated.

Jon.


Article: 58133
Subject: Re: mac & phy interface
From: "Stevenson" <stevensonDELTHIS@infinito.it>
Date: Tue, 15 Jul 2003 16:45:39 GMT
Links: << >>  << T >>  << A >>
Klemen <nec4b@email.si> wrote in message
bf105d$r9r$1@planja.arnes.si...
> Hi!
>
> Does anyone know what is the standard interface beatween
802.11a/b/g MAC and
> baseband? MAC would be implemented in fpga and baseband
should be in a
> seperate chip.

Hi!
For what I know there's not a standard interface!
It depends on what PHY (or baseband processor) are you
using...
Furthermore only few vendors offer a "MACless" baseband for
802.11a/g...
Most chips, like the Intersil Prism II (802.11b), have an
interface (called MDI) for data and another (MMI) for
management. These are quite simple to understand and work
with.
You can find more detailed informations in the Prism II
chipset datasheets.

Tony



P.S. It seems to be quite hard to get 802.11 parts and even
datasheets! :-)
Can anyone explain me why?!?





Article: 58134
Subject: Re: Wanted: Orcad Capture symbol for Xilinx Spartan IIE XC2S300E PQ208
From: "Steve Casselman" <sc_nospam@vcc.com>
Date: Tue, 15 Jul 2003 16:51:18 GMT
Links: << >>  << T >>  << A >>
From the FAQ
http://www.fpga-faq.com/FAQ_Pages/0027_Creating_PCB_symbols_for_FPGAs_using_ORCAD.htm
Last time I needed a Viewlogic symbol I asked my Insight-Electronics Gold
FAE and I got everything I needed.

Steve


"..:: Gabster ::.." <gabsterblue@hotmail.com> wrote in message
news:3I5Qa.39436$Pe2.1629953@wagner.videotron.net...
> Hi,
>
> If someone know where I could find the orcad capture symbol for the
XC2S300E
> in PQ208 package it would save me a lot of trouble and time.
>
> Thanks,
> Gabriel
>
>
>



Article: 58135
Subject: Re: PROM size for spartan
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 15 Jul 2003 10:17:46 -0700
Links: << >>  << T >>  << A >>
1. You can always use a bigger PROM. We usually recommend the tightest
fit because it is the most economical one. Bigger is ok.

2. Configuration code size is a constant for a given device, completely
independent of the logic utilization.

Peter Alfke, Xilinx Applications
========================
"..:: Gabster ::.." wrote:
> 
> The size of the PROM recommended for each Spartan model is shown here:
> http://www.xilinx.com/isp/compfpgatables/prom_spartan.htm
> 
> Why can't I use a 4Mb PROM with my Spartan IIE FPGA. Right now, on a 2Mb
> (the recommended one), the PROM is 89% full but the FPGA is far from being
> completly exploited.
> 
> thanks,
> Gabriel

Article: 58136
Subject: Re: PROM size for spartan
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Tue, 15 Jul 2003 17:37:17 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3F14373A.FBF54F53@xilinx.com>,
Peter Alfke  <peter@xilinx.com> wrote:
>2. Configuration code size is a constant for a given device, completely
>independent of the logic utilization.

If the Massive Patent Crossliscencing Settlement of Doom allows you to
use bitfile compression, that might be a worthwhile feature on future
devices.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 58137
Subject: Re: PROM size for spartan
From: "..:: Gabster ::.." <gabsterblue@hotmail.com>
Date: Tue, 15 Jul 2003 13:48:48 -0400
Links: << >>  << T >>  << A >>
I cannot seem to find a distributor for the new XCF02S. The only one listing
it is Avnet, but it's not in stock (and the minimum buy quantity is 74...I
would like to prototype first)

"Bruce Jorgens" <bruce.jorgens@xilinx.com> wrote in message
news:3F1427A9.DBA42BFD@xilinx.com...
> Gabriel,
>
> The size of the bitstream required to configure the FPGA does not change
as
> you use more of the FPGA resources.  Based on the 89% full PROM, I assume
you
> are using the XC2S300E device.  As you exploit more of the FPGA your PROM
will
> stay 89% full so there is no need for you to use a larger PROM.
>
> If you want the lowest cost, smallest boardspace solution, you should look
at
> our recently released Platform Flash family of configuration PROMs.  The
> XCF02S is available now and will configure your XC2S300E.  You can find
the
> cross-reference to Spartan-IIE at:
>
> http://www.xilinx.com/isp/compfpgatables/pfp_spartan.htm
>
> Bruce Jorgens
>
> "..:: Gabster ::.." wrote:
>
> > The size of the PROM recommended for each Spartan model is shown here:
> > http://www.xilinx.com/isp/compfpgatables/prom_spartan.htm
> >
> > Why can't I use a 4Mb PROM with my Spartan IIE FPGA. Right now, on a 2Mb
> > (the recommended one), the PROM is 89% full but the FPGA is far from
being
> > completly exploited.
> >
> > thanks,
> > Gabriel
>



Article: 58138
Subject: Re: PROM size for spartan
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Tue, 15 Jul 2003 11:01:05 -0700
Links: << >>  << T >>  << A >>
Compression of bit streams....

Is a tricky business.  Some bitstreams compress well, others do not compress
much at all.

Austin

"Nicholas C. Weaver" wrote:

> In article <3F14373A.FBF54F53@xilinx.com>,
> Peter Alfke  <peter@xilinx.com> wrote:
> >2. Configuration code size is a constant for a given device, completely
> >independent of the logic utilization.
>
> If the Massive Patent Crossliscencing Settlement of Doom allows you to
> use bitfile compression, that might be a worthwhile feature on future
> devices.
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu


Article: 58139
Subject: Re: what are libraries for??
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Tue, 15 Jul 2003 11:28:33 -0700
Links: << >>  << T >>  << A >>
Michael Nicklas wrote:

> What are libraries used for in HDL's?

For VHDL, libraries are compiled directory trees used to access packages
or other "Units" that you want to use, but don't want to edit,
and don't want to compile yourself in your default "work" directory/library.

The standard libraries require no setup by most tools.
I use ieee.std_logic_1164 for bit logic
and ieee.numeric_std for unsigned shifts, adds and compares.

If I have constants and functions to share between processes,
I use the default "work" library, as this is much less trouble
and more portable than naming and maintaining my own library.

> Simulation or Synthesis or both?

Both.


  -- Mike Treseler


Article: 58140
Subject: Re: free downloadable VLSI softwares
From: orgulhosamenteso@hotmail.com (Pedro Claro)
Date: 15 Jul 2003 11:49:36 -0700
Links: << >>  << T >>  << A >>
You could download, but you can also ask for the software on CD.
Well, I received Xilinx ISE 5.2 on CD with ModelSim. Check it out at:

http://www.xilinx.com/ise/ise_promo/ise5_eval.htm

I've also tried the Actel Libero 2.3 wich came in CDs, too:

http://interact.actel.com/gbnew/lr.cgi

Of course, these versions are limited in size and time.. 

Enjoy,

Pedro Claro

aji@noveldv.com (Ajeetha Kumari) wrote in message news:<8df95881.0307141836.7c343ae3@posting.google.com>...
> Hi,
>   Please check VHDL FAQ. Xilinix Webpack with Modelsim, SympanyEDA are few to name.
> 
> HTH,
> Ajeetha
> http://www.noveldv.com
> 
> a <a@a.com> wrote in message news:<beukeb$aql1@noticias.madritel.es>...
> > adarsh arora escribió:
> > > can u tell me from where i will get free downloadable softwares for
> > > VHDL/verilog simulation and synthesis , SPICE ,IC Station......  with
> > > free licences.
> > > waiting for ur help
> > http://ghdl.free.fr

Article: 58141
Subject: Re: An All Digital Phase Lock Loop
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Tue, 15 Jul 2003 13:58:50 -0500
Links: << >>  << T >>  << A >>
>
>
>Jason Berringer wrote:
>
>  
>
>>Hello guru's
>>
>>I was wondering if anyone has ever attempted a phase lock loop in digital
>>before (specifically VHDL). I'm looking for some examples or pointers on
>>trying to build one for a low frequency range of 200 Hz to 200 kHz. I would
>>appreciate any comments or suggestions. Google didn't get me very far, so if
>>you know of any app notes, etc. please let me know.
>>    
>>
You might have a look at TI's 74LS297 digital PLL chip.  It is a pretty 
complicated
device, but I have to say it worked far better than I expected in one of 
those
"can't be done" applications.  I had to get very tight control of a 
pixel clock
on a laser photoplotter, while multiplying the encoder pulses by 20.  A 
number
of engineers told me it was impossible, due to the fluctuation in the 
rotation
rate.  The LS297 has worked very well, however!

Jon


Article: 58142
Subject: Re: PROM size for spartan
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Tue, 15 Jul 2003 19:01:30 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3F144161.242FBBAB@xilinx.com>,
Austin Lesea  <Austin.Lesea@xilinx.com> wrote:
>Compression of bit streams....
>
>Is a tricky business.  Some bitstreams compress well, others do not compress
>much at all.

Right.  But compression, in the worst case, offers no savings, but in
the best case offers substantial savings.

And I'd expect that there is generally a fair amount of savings, just
from all the switchpoints which support a fairly large amount of
fanout when most switches only have a small amount of fanout most of
the time.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 58143
Subject: Re: programming a PLD/CPLD with a PIC?
From: Philip Freidin <philip@fliptronics.com>
Date: Tue, 15 Jul 2003 19:22:14 GMT
Links: << >>  << T >>  << A >>
On 14 Jul 2003 10:14:35 -0700, javodv@yahoo.es (javid) wrote:
>Hello to All,
>
>I was wondering if it is possible to program a PLD/CPLD via a PIC
>(without connecting external memory). The PIC I am using has a
>internal RAM of 768 bytes and 16k of flash. I have seen some app.notes
>from Altera/Xilinx/Lattice but I think that I need a more powerful
>micro for doing the CPLD reprograming with it. Is there any new small
>CPLD easy to reprogram?. I would appreciate any suggestion or link.
>
>Thanks a lot and best regards,
>
>Javier

You may find the following two links helpfull

   http://www.fpga-faq.com/FAQ_Pages/0036_Config_FPGA_with_PIC_and_Cheap_SEPROM.htm

   http://www.fpga-faq.com/FAQ_Pages/0038_Config_FPGA_from_a_processor.htm



Philip Freidin
Fliptronics

Article: 58144
Subject: Re: Virtex II Pro Exceptions
From: Robert McGee <robert.mcgee@xilinx.com>
Date: Tue, 15 Jul 2003 13:52:29 -0600
Links: << >>  << T >>  << A >>
tlbwe among other tlb instructions are treated as an illegal instructions
when the PPC405's TIEc405MmuEn signal is set to 0. I bet this is the case in
your design.

--Robert

Jon Masters wrote:

> Hi,
>
> I am attempting to execute the following code:
>
>         tlbwe    r4,r40,1
>
> Which is correctly dissassembled as:
>
>         7c 80 0f a4    tlbwelo r4,r0
>
> However at run time an unexpected Program Interrupt (0x0700) occurs with
> the reason given in the ESR (0x8000000) of ``Illegal Instruction''.
>
> This is on a development board containing a Xilinx Virtex II Pro which
> otherwise is running our code normally until this point.
>
> Any suggestions are appreciated.
>
> Jon.


Article: 58145
Subject: Re: PROM size for spartan
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Tue, 15 Jul 2003 13:23:07 -0700
Links: << >>  << T >>  << A >>
Nick,

It is really hard to sell a tool that only works sometimes (in fact, it does more
damage to do so, than to just not use that tool).

Thus, until we have a really robust method of compression that works across
thousands of bitstreams, we will stick to the easy method that we use now
(suppressing unused frames from being in the .bit file).

Austin

"Nicholas C. Weaver" wrote:

> In article <3F144161.242FBBAB@xilinx.com>,
> Austin Lesea  <Austin.Lesea@xilinx.com> wrote:
> >Compression of bit streams....
> >
> >Is a tricky business.  Some bitstreams compress well, others do not compress
> >much at all.
>
> Right.  But compression, in the worst case, offers no savings, but in
> the best case offers substantial savings.
>
> And I'd expect that there is generally a fair amount of savings, just
> from all the switchpoints which support a fairly large amount of
> fanout when most switches only have a small amount of fanout most of
> the time.
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu


Article: 58146
Subject: Re: how to remove this error
From: jon8spam@yahoo.com (Jon)
Date: 15 Jul 2003 13:52:09 -0700
Links: << >>  << T >>  << A >>
Hi Macei,
  It looks like that pin if it is an input or output nolonger exists
in the netlist.  Check the netlist to see if the net is renamed to
something else after synthesis.  I assume that you need that pin and
did not write logic that would get synthesized out.

Jon 

vhdl_uk@yahoo.co.uk (MACEI'S) wrote in message news:<fdfcada5.0307150152.76f887e3@posting.google.com>...
> Hi mates
> 
> I am getting following error while doing NGDBUILD using command line.
> I used -aul switch as suggested in error but this action simply
> doesn't assigned any pin to SR_IRD as seen in *.par file.
> 
> How tom remove this error . My UCF file entry is something like this 
> 
> NET "SR_IRD"			LOC = "P10" ;
> 
> Error :--------------------
> 
> /VIR3/VIR3_top/VIR3_top.ngo" ...
> Reading component libraries for design expansion...
> 
> Annotating constraints to design from file "VIR3.ucf" ...
> ERROR:NgdBuild:755 - Line 75 in 'VIR3.ucf': Could not find net(s)
> 'SR_IRD' in
>    the design.  To suppress this error use the -aul switch, specify
> the correct
>    net name or remove the constraint.
> ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
> ERROR:NgdBuild:19 - Errors found while parsing constraint file
> "VIR3.ucf".
> 
> 
> 
> Rgds
> MACEI'S

Article: 58147
Subject: mac & phy interface
From: "Klemen" <nec4b@email.si>
Date: Tue, 15 Jul 2003 23:36:54 +0200
Links: << >>  << T >>  << A >>
Hi!

Does anyone know what is the standard interface beatween 802.11a/b/g MAC and
baseband? MAC would be implemented in fpga and baseband should be in a
seperate chip.

regards
Klemen





Article: 58148
Subject: I/Os with Cypress chip
From: "Brad Smallridge" <bsmallridge@dslextreme.com>
Date: Tue, 15 Jul 2003 15:27:41 -0700
Links: << >>  << T >>  << A >>
Dear folks,

I am a Cypress user and have had the trouble of laying out a board using 134
of what I thought were 136 available I/O lines going into the device. Eight
of these lines were global control or global clocks.  I had thought that I
could use all of them but the Warp 6.2 only lets me use 128 I/Os. What
gives? Is there a special declaration I should be using for the global pins?
Do I only get 128 I/Os even though there are 136 I/O pins?

Thanks,

Brad

P.S Details of my discussion with Cypress below:

Created at:  06/20/03 03:45 PM

Part Number:  Delta 39K
Product:  Programmable Logic > Programmable Logic Devices
Subject:  Error with Max IO
Description:  I am running Warp6.2 for a 39k100 and get error EMP043
Resource Limit Maximum Number of IO Cells Exceeded (max=128, needed 134)
although I believe this chip should have enough IO.

Brad

Attachments:

 Interactions

 Cypress Response   07/15/03 08:03 AM | Web
Hi Brad,

I hope we have fully addressed your inquiry. I am closing this case for now,
if you require further assistance on this issue please re-open this case
(using the radio button for Status, Open, and clicking Submit) and we will
be glad to assist you. For all other inquiries please open a new case.


Thank you for using Cypress products,

Cypress Applications Support


 Cypress Response   | 07/10/03 02:51 PM | Web
Hi Brad,

The global clock and control signal pins are declared as inputs (for OE)
Warp will route these signals as in the 11c signal in your design.


Cypress Applications Support


 Customer Comment   Brad Smallridge | 07/10/03 11:33 AM | Web
Are there some sort of other pin type assignemnts similar to in, out, or
inout that should be used with the global clock and global control pins?

 Cypress Response   | 07/07/03 09:33 AM | Web
Hi Brad,

Sorry for all the confusion.

In reference to your response:

The data sheets state that I have 136 IOs available. Is there some sort of
internal architecture that limits me to 128 IOs? What pins may I or may I
not use?

Page 2 of the datasheet states that of the 208 packages. " Device Package
Offering and I/O Count Including Dedicated Clock and Control Inputs", is
136.

Pages 50 thru 56 of the datasheet explain the pins and their functions for
the CY39100V208-200NTC package. If you count the number of pins that can
function as I/O's there are 128. Depending how you configure the I/O's this
number decreases.

Please see application note: Delta39K and Quantum38K I/O Standards and
Configurations

I/O Standards and Configurations


Thank you for your patience


Cypress Applications Support




 Customer Comment   Brad Smallridge | 07/03/03 12:48 PM | Web
This reply seems non-responsive. The data sheets state that I have 136 IOs
available. Is there some sort of internal architecture that limits me to 128
IOs? What pins may I or may I not use? I think I need a better answer since
I have already committed to, and spent money on, a hardware design.


 Cypress Response   | 07/02/03 01:51 PM | Web
Hi Brad,

The pin attributes in your design are fine. Whether or not the design can be
fitted to the device depends on the rest of your design which you have
commented out. There are too many floating signals to determine if this
design as coded can be compiled to fit the device.

From what I have been able to determine, you will probably not have enough
I/O's to support your design.


Thank you for your patience


Cypress Applications Support


 Customer Comment   Brad Smallridge | 07/02/03 09:24 AM | Web
I am not using VCCIO for signals. Perhaps you can look at my VHD pin list
and tell me what pins I can not use?

 Cypress Response   | 06/30/03 09:09 AM | Web
Hi Brad,

I did try to contact you, I left a msg on your voice-mail.

I hope we have fully addressed your inquiry. I am closing this case for now,
if you require further assistance on this issue please re-open this case
(using the radio button for Status, Open, and clicking Submit) and we will
be glad to assist you. For all other inquiries please open a new case.


Thank you for using Cypress products,

Cypress Applications Support


 Cypress Response   | 06/27/03 03:20 PM | Web
Hi Brad,

Thank you for using the Cypress On-Line ConnectionCenterT. In reference to:


Error EMP043 Resource Limit Maximum Number of IO Cells Exceeded (max=128,
needed 134) although I believe this chip should have enough IO.

Ans: The available number of I/O's for this device is 128, the additional 8
I/O's (VCCIO) are for power to the I/O banks and not for signals.


Note:

If you limit your design to the use of 128 I/O's it will compile



Thank you for your patience

Cypress Applications Support


 Customer Comment   Brad Smallridge | 06/27/03 12:03 AM | Web
1) CY39100V208B-200NTC
2) no other errors

VHD file is attached
test08.vhd


 Cypress Response   | 06/23/03 10:27 AM | Web
Hi Brad,

We are presently looking into your case and will respond as soon as
possible. I want to clarify your issue, "Error with Max IO":

1) What is the entire part description of the device that you are targeting?

2) Are their any other errors being generated by the compiler?


Please include your design files that we may further investigate this issue.


Thank you for your patience

Cypress Applications Support




Article: 58149
Subject: Re: Xilinx FPGA module
From: "John Pham" <jpsc@hotmail.com>
Date: Wed, 16 Jul 2003 00:10:45 GMT
Links: << >>  << T >>  << A >>
Yes, go to http://snaplogix.tripod.com
for the FPGA DIMM module.  As of today, I'm out of blank PCB module and only
have
a few module with the bottom assembled - but I predict that will go away
pretty fast.
The next batch of blank PCB wont come for another 2 to 3 weeks.


"Amontec Team" <laurent.gauch@www.DELALLCAPSamontec.com> wrote in message
news:3F0ED6D1.2080701@www.DELALLCAPSamontec.com...
> John Pham wrote:
> > If anyone interest in a FPGA DIMM module using Xilinx Virtex (XCV600)
with
> > 512K SRAM, onboard 10/100 Ethernet + Flash + JTAG/ROM/CPLD and 16bit PCM
> > Codec please email me.  The board size is 5.25" x 3" 168 pins DIMM
module.
> > The next batch of production run is due in 3 weeks, bare board PCB and
semi
> > assemble board are available now
> >
>
> Interesting, did you have a reference page ?
>
> Laurent
> www.amontec.com
>





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