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Jasson, take a look at out free USB 1.1 PHY IP core. It includes a very simple DPLL. It is written in Verilog however. Best Regards, rudi -------------------------------------------------------- www.asics.ws --- Solutions for your ASIC/FPGA needs --- ----------------- FPGAs * Full Custom ICs * IP Cores --- FREE IP Cores --> http://www.asics.ws/ <-- FREE IP CoresArticle: 58251
1. In file test.v:
`include "header.vh"
`ifdef OP_MODE_0
mode0_proc mode_proc( // designed in mode0_proc.v
.O(sig_out), .I(sig_in));
`endif
`ifdef OP_MODE_1
mode1_proc mode_proc( // designed in mode1_proc.v
.O(sig_out), .I(sig_in));
`endif
2. In file header.vh:
`define OP_MODE_0 1
3. After I modified the OP_MODE_0 to OP_MODE_1 in header.vh, the ISE didn't
ask for the mode1_proc.v in the Module View window. Hence,
the Synplify failed during synthesis because the undefined mode1_proc.v
module. I had to "touch" the test.v to force ISE to re-scan the relationship
among test.v, mode0_proc.v, and mode1_proc.v. However, I have to "touch"
so many files in different directories if these files all contained such
"ifdef"... Is there any other way to solve it?
Article: 58252Hi all, Am new to fpga.I need help in selecting an external oscillator ( of 50MHz) for spartan IIE XC2S50E fpga. I would like to know the following details for this purpose. 1. What are the parameters to be considered in selecting external crystal oscillator? 2. Any standard crystal oscillator ckts avilable? 3. How many pins I have to leave in FPGA to connect the external crystal oscillator ckt? 4. Is there any specific documents that I can refer for this? Bijesh VMArticle: 58253
"bijesh v.m." <bijeshvm@hotmail.com> wrote in message news:416ef565.0307180020.95c61c9@posting.google.com... > Hi all, > > Am new to fpga.I need help in selecting an external oscillator ( of > 50MHz) for spartan IIE XC2S50E fpga. I would like to know the > following details for this purpose. > > 1. What are the parameters to be considered in selecting external > crystal oscillator? > 2. Any standard crystal oscillator ckts avilable? > 3. How many pins I have to leave in FPGA to connect the external > crystal oscillator ckt? > 4. Is there any specific documents that I can refer for this? You don't usually need to actually design and build a suitable oscillator, simply buy one of the many oscillator modules that are available. 50 MHz ones are easy to get hold of. They are available in 8 pin and 14 pin DIL packages. You can also get SMD ones. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 58254
> Am new to fpga.I need help in selecting an external oscillator ( of >50MHz) for spartan IIE XC2S50E fpga. I would like to know the >following details for this purpose. >1. What are the parameters to be considered in selecting external >crystal oscillator? Any constraints from your application? Accuracy? Temperature drift? ... >2. Any standard crystal oscillator ckts avilable? Most people use one of the standard oscillator packages. (rather that building their own circuit using a raw crystal) I'd expect almost any of the packages that run on 3.3 V would work. In most cases, it's not a big deal. >3. How many pins I have to leave in FPGA to connect the external >crystal oscillator ckt? One. Two for a differential input which might give you slightly less jitter. Maybe more if you are using a DLL and want to sync to an external pin. There are special clock-input pins. >4. Is there any specific documents that I can refer for this? How about the data sheet? I don't have the one for the -E handy, but the Spartan II has several pages on "Using Versatile I/O". The part on the clock inputs is on page 32 of section 2. Check the banking rules if you are doing something fancy. There is another section on clocking. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 58255
use the Jam STAPL ByteCode Player (sbi32.exe) from Altera. Simple to use from the command line like: jbi32 -dDO_PROGRAM=1 -aPROGRAM abc.jbc Martin -- -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/ "algous" <algous2002@yahoo.com.cn> schrieb im Newsbeitrag news:1e71fcd5.0307171824.6924e95b@posting.google.com... > you can find the jblaster project on the sourceforge.net > > Jim Flanagan <jflan@ieee.org> wrote in message news:<MPG.197fad6474e7fddb989682@netnews.worldnet.att.net>... > > [This followup was posted to comp.arch.fpga and a copy was sent to the > > cited author.] > > > > Hi.. > > I am searching for a 'standalone' command line utility that will > > allow me to program Altera CPLD parts using the ByteBlasterMV cable > > and WITHOUT using Max-Plus,etc. The MaxPlus sw comes bundled with a > > small executable (with 'C' source) that will allow you to program using > > .RBF (raw binary files) but not .POF files. Either I need to modify > > the source to accomodate POF files (don't have the specification, any > > help?) or get a utility that will convert POF to RBF format. > > > > In any event, I could use some direction. The reason for the standalone > > tool, is that I want to integrate the CPLD programming into a production > > environment and do not want an operator to have to run a program such > > as MaxPlus. > > > > Any help would be appreciate... Thanks. > > > > JimArticle: 58256
> > 3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF per > > power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). Is > > that accurate? Should I do more? What should I avoid? > > That's a reasoanable ballpark. Inductance is what you want to > avoid. Vias count, so do long traces from pads to vias. Why is everyone talking about 0.1uF caps? Isn't it time to adjust the cap values to the higher speed of the logic and to avoid EMI problems. A standard 0.1uF cap 0805 with X7R dielectric is at resonance at 10 MHz (see datasheet of Kemel caps)! Above 10 MHz the impedance becomes inductive. EMI is measured up to 1 GHz. Martin -- -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/Article: 58257
"Brad Smallridge" <bsmallridge@dslextreme.com> wrote in message news:<vhav5viql77dbc@corp.supernews.com>... > It would appear, however, that I can get the Global Signals to work as > inputs. But when I do, then I loose an I/O. That doesn't seem right. Like > buying a three input OR gate and only being able to use two of the inputs at > any one time. > > Brad Brad, I can't explain the loss of other I/O pins when the global signals are used. This could be a fitter problem. If it is, I wish you the best of luck trying to get Cypress to fix it. We are having a number of difficulties with the 39K device fitter. One of the scariest ones is this: We successfully fitted a design and then wished to make a change that involved adding a pin. Since the prototype board is already wired, we "fixed" the previously fitted pins prior to fitting the design with the added pin. The design does not fit. As a sanity check, we removed the new signal from the design and tried to fit it with the pins "fixed" as the fitter previously assigned them. The design will not fit. If we remove the compiler directive that keeps the pinout from changing, the design will fit and has the same pinout that we instructed it to keep. This does not bode well for future designs where one wants to make a change without changing the pin assignments previously made. I am sorry to report that Cypress seems unwilling to fix this and several other problems with the 39K fitter. Best regards, CharlesArticle: 58258
PCI on PCs runs off 5V. Yet most FPGA runs at 3V3. What is a suggested level translator to use? Does the use of level translators effect PCI compatibility?Article: 58259
hi, it depends of many things, What is the sample rate ? (150MHz) What are the data and coef size ? Is there decimation or interpolation ? How many TAPs ? Coefficients are constants ? XC2V300 doesn't exist, is it 2V3000-4 ? The first thing you must know is that a high sample rate is the less easy thing to achieve, but not impossible (in a -6 or V2Pro ! maybe it's possible with -5 or even -4) ludovic <Marloboro> a écrit dans le message de news:ee7eb4e.-1@WebX.sUN8CHnE... Hi guys, In my new project, input data to parallel FIR is as fast as 150 mhz which I think so fast for PDA (I have used coregen PDA at 50 mhz or slower, it run well) dont know how it perform? Xilinx data sheet on core FIR not saying about speed. I know speed depends on many factors as placement, routing,... Let say an 80% resource design with XC2V300 speed -4, how fast one can archive with the FIR???Article: 58260
Martin Schoeberl wrote: > > > > 3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF > per > > > power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). > Is > > > that accurate? Should I do more? What should I avoid? > > > > That's a reasoanable ballpark. Inductance is what you want to > > avoid. Vias count, so do long traces from pads to vias. > > Why is everyone talking about 0.1uF caps? Isn't it time to adjust the cap > values to the higher speed of the logic and to avoid EMI problems. A > standard 0.1uF cap 0805 with X7R dielectric is at resonance at 10 MHz (see > datasheet of Kemel caps)! Above 10 MHz the impedance becomes inductive. EMI > is measured up to 1 GHz. Two points I would make. 1) Whether a cap is inductive or capacitive at a given frequency is of no concern. The only thing that matters is the impedance. The purpose of a cap is to lower the impedance of the power to ground path at the frequencies of your noise. A low impedance inductive path is just as good a coupling the noise to ground as a low impedance capacitive path. 2) If you don't like the Kemel (sp? Kemet perhaps) caps, use someone else's caps that are rated with a higher resonance or a lower impedance. I know that the 0.1 uF caps I use have a resonance above 50 MHz. Perhaps you were looking at a larger package which adversely affects the impedance more than does the cap value? 0.1 uF caps come in 0603 packages which have very good high freq characteristics. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58261
Hi fellows, I am getting following error's My ucf file entry is given after this error. ERROR ____________________________________________________________________________ Checking timing specifications ... ERROR:TSDatabase:19 - Processing TIMESPEC definition "TS_CLK_2X=PERIOD "CLK_0_2XOUTDLL" 10000.000000 pS HIGH 5000.000000 pS" from UCF file: No TNM, TPSYNC or user group named "CLK_0_2XOUTDLL" is defined. ERROR:TSDatabase:19 - Processing TIMESPEC definition "TS_P2CLK2X=FROM "PADS" TO "CLK_0_2XOUTDLL" 8500.000000 pS" from UCF file: No TNM, TPSYNC or user group named "CLK_0_2XOUTDLL" is defined. ERROR:TSDatabase:19 - Processing TIMESPEC definition "TS_CLK2X2P=FROM "CLK_0_2XOUTDLL" TO "PADS" 9000.000000 pS" from UCF file: No TNM, TPSYNC or user group named "CLK_0_2XOUTDLL" is defined. Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 3 Number of warnings: 0 One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "vir3_top.bld"... _______________________________________________________________________________ UCF FILE ENTRY _____________________________________________________________________________ # # Timing Constraints # # NOTE: CLK_0_OUTDLL not used in this design # #TIMESPEC "TS_CLK_0" = PERIOD "CLK_0_OUTDLL" 16 HIGH 8; TIMESPEC "TS_CLK_2X" = PERIOD "CLK_0_2XOUTDLL" 10 HIGH 5; TIMESPEC "TS_P2P" = MAXDELAY FROM "PADS" TO "PADS" 20 nS; TIMESPEC "TS_P2CLK2X" = MAXDELAY FROM "PADS" TO "CLK_0_2XOUTDLL" 8.5 nS; #TIMESPEC "TS_P2CLK0" = MAXDELAY FROM "PADS" TO "CLK_0_OUTDLL" 8.5 nS; TIMESPEC "TS_CLK2X2P" = MAXDELAY FROM "CLK_0_2XOUTDLL" TO "PADS" 9 nS; # # Pin Location Constraints # Uncomment required pins ______________________________________________________________________________ Help would be appreciated Cheers ISAACArticle: 58262
rickman wrote: > 0.1 uF caps come > in 0603 packages which have very good high freq characteristics. Choose a low-inductance package and get as many pFs as economically available. Reverse geometry packages are worth looking at. And don't blow it by poor layout on the cap power and ground vias.Article: 58263
rickman wrote: > Two points I would make. > > 1) Whether a cap is inductive or capacitive at a given frequency is of > no concern. The only thing that matters is the impedance. The purpose > of a cap is to lower the impedance of the power to ground path at the > frequencies of your noise. A low impedance inductive path is just as > good a coupling the noise to ground as a low impedance capacitive path. I agree with you an this point, but to a degree.... The Kemet value and package mentioned with the SRF at 10MHz has an impedance of about 0.1 ohm at 10MHz. At 100MHz, the impedance is over 1 ohm. Assuming 12 .1uF caps scattered around an FPGA, if the chip uses a 100MHz clock there will be a ripple on the voltage plane of 83mV per amp of dynamic current. In today's lower foltage/higher current devices, can we accept those levels of voltage noise? It would take 1 or 2 caps with an SRF at 100MHz to provide the same filtering as 12 of those Kemet 0.1uF devices, again at 100MHz. > 2) If you don't like the Kemel (sp? Kemet perhaps) caps, use someone > else's caps that are rated with a higher resonance or a lower > impedance. I know that the 0.1 uF caps I use have a resonance above 50 > MHz. Perhaps you were looking at a larger package which adversely > affects the impedance more than does the cap value? 0.1 uF caps come in > 0603 packages which have very good high freq characteristics. Smaller packages do tend to perform better. It might be nasty working with 0402s, but the SRF can be better. As long as the PC layout isn't compromised (e.g., single vias distant from the mounting pads) better results are obtained. I have seen few designers actually do a comprohensive decoupling analysis. I've mentioned on this board before that the technique of using multiple capacitor values with differing SRFs can provide great benefit. As long as you keep the differences small (SRFs a decade apart for adjacent capacitors with have horrible impedance at one point between those SRFs - imagine what an inductor and capacitor in parallel provide at resonance) and the capacitors are nicely distributed, the total number of capacitors could be reduced to achieve the same impedance across a frequency range of interest. Just one capacitor value will work. EMI will suffer, there will be noise on the voltage planes. Poorly designed combinations of caps (e.g., two values laid out adjacent to each other in pairs aren't distributed enough to avoid the resonance mentioned above) will also provide ugly results but tend to "work." To "adjust the cap values to the higher speed of the logic" by reducing the capacitance alone (to increase the SRF) won't "avoid EMA problems" but will move them. Solid decoupling design will get us there.Article: 58264
Hi does anybody know if it is possible to get old libraries and if so, from where? I am using ISE 5.1i and am trying to redo a core which uses a LogiBlox DP_RAM module originally generated in 1999. When I try to synthesise the code it cant locate the library, do I have to redo a core to try and emulate this or can I simply get hold of the Logiblox library? Thanks in advance. -- Cheers! MikeArticle: 58265
Hi guys 1) Can I used *.bit file instead of *.rbt file to download using C++ program into PCI based FPGA device. 2) In xilinx ISE 5.2i or any other using GUI interface for compilation , mapping etc. When you rum generate programming file then it creates *.bit file not *.rbt file. Can anybody tell me how to convert *.bit into *.rbt file. Thanking you in advance. Cheers Rgds Macie'sArticle: 58266
Jim Flanagan <jflan@ieee.org> wrote in message news:<MPG.197fad6474e7fddb989682@netnews.worldnet.att.net>... > I am searching for a 'standalone' command line utility that will > allow me to program Altera CPLD parts using the ByteBlasterMV cable > and WITHOUT using Max-Plus,etc. Have you looked into JAM/STAPL? www.jamisp.com This is an Altera invented standard for programming CPLD's using external programmers and embedded systems. The kit includes source code so you can modify it to program a CPLD from an embedded system. But the last time I looked at it, the sample code worked with a ByteBlaster and ran from the command line. Alan Nishioka alann@accom.comArticle: 58267
In article <bf89is$59n@netnews.hinet.net>, louis lin wrote:
[ chop an example of `ifdef that would be trivial in the
traditional C programming world, but strains the capabilities
of Xilinx's Verilog tools]
> I had to "touch" the test.v to force ISE to re-scan the relationship
> among test.v, mode0_proc.v, and mode1_proc.v. However, I have to "touch"
> so many files in different directories if these files all contained such
> "ifdef"... Is there any other way to solve it?
I gave up on letting ISE itself deal with `ifdef. Now I run
all my Verilog through Icarus first (iverilog -E) using a Makefile,
and only then sic ISE on the preprocessed output. I agree the
real problem is in the dependency generator, the synthesizer
itself probably gets things right.
- Larry
Article: 58268"In xilinx ISE 5.2i or any other using GUI interface for compilation..." If you right click on the "Generate Programming File" and select the "Properties...", you have the option of generating .rbt (Create ASCII Configuration File) and/or .bin (Create Binary Configuration File) files. The .rbt (raw bit) files are ASCII ones and ASCII zeros. The .bin file is the binary equivalent of the .rbt at 1/8 the size. The .bit file may be very similar to the .bin file but there appears to be header information that needs to be stripped from the .bit file first according to a recent thread on this newsgroup. Personally, I like the .bin files. "MACEI'S" <vhdl_uk@yahoo.co.uk> wrote in message news:fdfcada5.0307180719.664abc97@posting.google.com... > Hi guys > > 1) Can I used *.bit file instead of *.rbt file to download using C++ > program into PCI based FPGA device. > 2) In xilinx ISE 5.2i or any other using GUI interface for compilation > , mapping etc. When you rum generate programming file then it creates > *.bit file not *.rbt file. Can anybody tell me how to convert *.bit > into *.rbt file. > Thanking you in advance. > > Cheers > > Rgds > > Macie'sArticle: 58269
Willem, Translators are strictly not allowed by the specification (but that doesn't mean that people don't use them). See the app note for PCI on our website for Virtex II Pro. http://www.xilinx.com/xapp/xapp653.pdf One can also use Spartan II, and Virtex directly with no translators, as these two parts are 5V tolerant, and also meet the 5V PCI spec. The circuits in the app note were built and tested on a number of PC PCI buses. Austin Willem Oosthuizen wrote: > PCI on PCs runs off 5V. Yet most FPGA runs at 3V3. What is a suggested > level translator to use? Does the use of level translators effect PCI > compatibility?Article: 58270
John_H wrote: > > rickman wrote: > > Two points I would make. > > > > 1) Whether a cap is inductive or capacitive at a given frequency is of > > no concern. The only thing that matters is the impedance. The purpose > > of a cap is to lower the impedance of the power to ground path at the > > frequencies of your noise. A low impedance inductive path is just as > > good a coupling the noise to ground as a low impedance capacitive path. > > I agree with you an this point, but to a degree.... The Kemet value and > package mentioned with the SRF at 10MHz has an impedance of about 0.1 > ohm at 10MHz. At 100MHz, the impedance is over 1 ohm. Assuming 12 .1uF > caps scattered around an FPGA, if the chip uses a 100MHz clock there > will be a ripple on the voltage plane of 83mV per amp of dynamic > current. In today's lower foltage/higher current devices, can we accept > those levels of voltage noise? It would take 1 or 2 caps with an SRF at > 100MHz to provide the same filtering as 12 of those Kemet 0.1uF devices, > again at 100MHz. The point is that you need to do the math based on the impedance at your frequency of interest, not based on the resonance freq. The width of the resonant fequency is far too narrow to be of any real use in noise decoupling. So you need to give consideration to the impedance over the frequency range of your noise and pay no attention to whether you are inductive, capacitive or at resonance. > > 2) If you don't like the Kemel (sp? Kemet perhaps) caps, use someone > > else's caps that are rated with a higher resonance or a lower > > impedance. I know that the 0.1 uF caps I use have a resonance above 50 > > MHz. Perhaps you were looking at a larger package which adversely > > affects the impedance more than does the cap value? 0.1 uF caps come in > > 0603 packages which have very good high freq characteristics. > > Smaller packages do tend to perform better. It might be nasty working > with 0402s, but the SRF can be better. As long as the PC layout isn't > compromised (e.g., single vias distant from the mounting pads) better > results are obtained. > > I have seen few designers actually do a comprohensive decoupling > analysis. I've mentioned on this board before that the technique of > using multiple capacitor values with differing SRFs can provide great > benefit. As long as you keep the differences small (SRFs a decade apart > for adjacent capacitors with have horrible impedance at one point > between those SRFs - imagine what an inductor and capacitor in parallel > provide at resonance) and the capacitors are nicely distributed, the > total number of capacitors could be reduced to achieve the same > impedance across a frequency range of interest. I have also heard of problems that can be produced from such an arrangement. I personally don't think any of this is a real issue. I use enough caps of a decent size to be effective without trying to design special effects based on a particular cap. That makes it a lot easier to buy components without having to specify a particular brand to get the "right" tuning. > Just one capacitor value will work. EMI will suffer, there will be > noise on the voltage planes. Poorly designed combinations of caps > (e.g., two values laid out adjacent to each other in pairs aren't > distributed enough to avoid the resonance mentioned above) will also > provide ugly results but tend to "work." > > To "adjust the cap values to the higher speed of the logic" by reducing > the capacitance alone (to increase the SRF) won't "avoid EMA problems" > but will move them. Solid decoupling design will get us there. The one fact that seems to be universally true about power decoupling design is that everyone has their own way of doing it and most of them seem to work. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58271
On 18 Jul 2003 08:19:17 -0700, vhdl_uk@yahoo.co.uk (MACEI'S) wrote:
>Hi guys
>
>1) Can I used *.bit file instead of *.rbt file to download using C++
>program into PCI based FPGA device.
>2) In xilinx ISE 5.2i or any other using GUI interface for compilation
>, mapping etc. When you rum generate programming file then it creates
>*.bit file not *.rbt file. Can anybody tell me how to convert *.bit
>into *.rbt file.
>Thanking you in advance.
>
>Cheers
>
>Rgds
>
>Macie's
This was covered last month:
http://www.fpga-faq.com/archives/56850.html#56857
http://www.fpga-faq.com/archives/56900.html#56908
So,
1) yes. If the PCI interface is in the FPGA though, it obviously
wont be available until after configuration.
2) wrong. (I'm using 5.2.03i). In the process window, select the
Process step "generate programming file". Bring up the process
properties (either right click and select properties, or menu
select process->properties). Select the "Create ASCII configuration
File". Re-run this process step.
The file formats are documented well enough in the FAQ that you could
write a converter, but for almost all applications this is not needed
since ISE can generate either format.
Philip Freidin
Philip Freidin
Fliptronics
Article: 58272hi aubel, the FIRs has 5 taps, fix and symetric coefs. Both data and coef are 10 bits. I think its possible but take more time for manual placement. thanks anyway.Article: 58273
MACEI'S wrote: > > Hi guys > > 1) Can I used *.bit file instead of *.rbt file to download using C++ > program into PCI based FPGA device. > 2) In xilinx ISE 5.2i or any other using GUI interface for compilation > , mapping etc. When you rum generate programming file then it creates > *.bit file not *.rbt file. Can anybody tell me how to convert *.bit > into *.rbt file. > Thanking you in advance. Generating an .rbt file is done with the same tool that makes the .bit file. There are a series of select check boxes in the "Generate Programming File" properties to indicate the type of output file. The BIT file must always be generated if you want either of the others, IIRC. The other options are to compress the bitstream, output a BIN file and/or a RBT file. I think you can only generate a BIT file for CPLDs though. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58274
Synplify generates slightly better code than XST resulting in a better utilization of the 2VP7 (in terms of IP that fits into the device). The V2PDK design has about 3 PLB masters, 2 PLB slaves, 12 OPB peripherals, 2 DCR interrupt controllers, brigdes, arbiters and some glue logic. To be able to synthesize with XST (verilog) edit flow.cfg, go to the end of the file, and remove some of the peripherals, e.g. parallel port, AC97, SPI or whatever else you don't need. If you want to work with EDK please contact your FAE and ask him to get you access to the EDK reference design for ML300. He will be able to get you access to the design. - Peter tk wrote: > Hi all, > > When I try to follow the steps to make a bitstream of ML300 Embbedded > reference system in > Virtex-II Pro Development Kit, I get the following error during Mapping: > > ERROR:Pack:18 - The design is too large for the given device and package. > Please check the Design Summary section to see which resource requirement > for > your design exceeds the resources available in the device. > > I'm using ISE 5.2i (SP3). The synthesis tool I use is XST. The following is > part of the synthesis report: > > Number of Slices: 3366 out of 5440 61% > Number of Slice Flip Flops: 3176 out of 10880 29% > Number of 4 input LUTs: 3920 out of 10880 36% > > The following is part of the Mapping report: > > Logic Utilization: > Number of Slice Flip Flops: 6,265 out of 9,856 63% > Number of 4 input LUTs: 7,420 out of 9,856 75% > Logic Distribution: > Number of occupied Slices: 4,957 out of 4,928 > 100% (OVERMAPPED) > Number of Slices containing only related logic: 3,346 out of 4,957 > 67% > > Number of Slices containing unrelated logic: 1,611 out of 4,957 > 32% > > *See NOTES below for an explanation of the effects of unrelated > logic > Total Number 4 input LUTs: 8,072 out of 9,856 81% > Number used as logic: 7,420 > Number used as a route-thru: 275 > Number used for Dual Port RAMs: 176 > (Two LUTs used per Dual Port RAM) > Number used as Shift registers: 201 > > I would like to ask how could I solve the *OVERMAPPED* problem? > There is pre-built bitstream file in the reference design. How come I > can't create one myself ?! > > Thanks in advance. > > tk
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