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I am trying to transfer some Verilog code from Cyclone FPGA devices to Spartan-3 FPGA. This module can initialize memory using the data in font.mif. The problem I met is that I cannot find a method to preload data to Block RAM. Any advice? Thanks. // coding under Quartus II 2.2 module Loadfont (dataout, addr, inclk); // port instantiation input [10:0] addr; input inclk; output [4:0] dataout; reg [4:0] datain; // instantiating lpm_ram_dq lpm_ram_dq ram (.data(datain), .address(addr), .we(0), .inclock(inclk), .outclock(inclk), .q(dataout)); // passing the parameter values defparam ram.lpm_width = 5; defparam ram.lpm_widthad = 11; defparam ram.lpm_indata = "REGISTERED"; defparam ram.lpm_outdata = "REGISTERED"; defparam ram.lpm_file = "font.mif"; endmodule (module RAMB4_S# (DO, ADDR, DI, EN, CLK, WE, RST); module RAMB4_S#_S# (DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); )Article: 58276
I am trying to transfer some Verilog code from Cyclone FPGA devices to Spartan-3 FPGA. This module written before can initialize memory using the data in font.mif. (support LPM megafunction at Quartus II) The problem I met is that I cannot find a method to preload data to Block RAM (IDE enviroment is Xilinx ISE 5). Any advice? Thanks. // coding under Quartus II 2.2 module Loadfont (dataout, addr, inclk); // port instantiation input [10:0] addr; input inclk; output [4:0] dataout; reg [4:0] datain; // instantiating lpm_ram_dq lpm_ram_dq ram (.data(datain), .address(addr), .we(0), .inclock(inclk), .outclock(inclk), .q(dataout)); // passing the parameter values defparam ram.lpm_width = 5; defparam ram.lpm_widthad = 11; defparam ram.lpm_indata = "REGISTERED"; defparam ram.lpm_outdata = "REGISTERED"; defparam ram.lpm_file = "font.mif"; endmodule (module RAMB4_S# (DO, ADDR, DI, EN, CLK, WE, RST); module RAMB4_S#_S# (DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); )Article: 58277
I find EDIF2NGD's error reporting near worthless. My errors have ranged from 100000 lines above the stated location to several hundred lines past the stated location. "Isaac" <fpga_uk@yahoo.co.uk> wrote in message news:889eb3fb.0307170306.40b10162@posting.google.com... > Hi Fellows, > > > I am having this error, I changed my edf file but it didn't work. > > still getting this error.. > > > ERROR:NgdBuild:180 - On or above line 1413 in file "VIR3_top.edf": > Bad > instanceRef "SR_DATA_IO_int_reg_7" in net "N_SR_DATA_IO_7". This > likely > means that the EDIF netlist was improperly written. Please contact > the > vendor of the program that produced this EDIF file. > > > > I check the file but I didn't find any thing unusal infact everything > for SR_DATA_IO_7 is same for the one's which are not mentioned in the > error. Like SR_DATA_IO_6 or lower. > > Waiting for your view on this > > Cheers > > > ISAACArticle: 58278
ISE 4.2 XST supported compile to EDIF but, unfortunately, they dropped that parameter with the newer versions. <email_address@message.end> wrote in message news:llq9hvs39mifu4uj2blapj4r93osk8qij1@4ax.com... > Hi, > > I'm using ISE 5.02.03 > > It looks like they (Xilinx) removed the EDIF option from XST. > > I found it in a google groups search (lots of people using it in > 4.2i), and I found it in the version 3 XST manuals: set the output > format to EDIF with -omft EDIF > > When I try that with 5.2i, I get an error:1361 (invalid omft option) > > So... How does one create and EDIF with XST? > > Please Help, > Gary > gwhelbig -at- yahoo -dot- com >Article: 58279
Hi, I have a problem with Multi device configuration circuit of Altera. My circuit have 2 EPC2 cascade mode and 2 EPF10K50 (Altera doc. AN 116.pdf page 11). The files .POF are 2. The first for the first device and the second for the second device. I try to programming with JTAG file .jcf. as follows: EPC2 -> File1.pof EPF10k50 -> -- EPC2 -> File2.pof EPF10k50 ->--. Before the programming my devices are not configure.WHY? Please Help me... Thanks Paolo --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.500 / Virus Database: 298 - Release Date: 10/07/2003Article: 58280
Hi all, the error message like this : FATAL_ERROR:Map:Portability/export/Port_Main.h:116:1.17 - This application has discovered an exceptional condition from which it cannot recover.Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com Xilinx answer to use "editbin" from msvc sdtudio-6.0.... but I dont have such thing..., down load map.exe from xilinx still give same error. How to get around it? please... I think when I have a multiplier it gives the error, remove the multiplier the error gone... what's the true story about this?Article: 58281
Martin Schoeberl wrote: > > > > 3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF > per > > > power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). > Is > > > that accurate? Should I do more? What should I avoid? > > > > That's a reasoanable ballpark. Inductance is what you want to > > avoid. Vias count, so do long traces from pads to vias. > > Why is everyone talking about 0.1uF caps? Isn't it time to adjust the cap > values to the higher speed of the logic and to avoid EMI problems. A > standard 0.1uF cap 0805 with X7R dielectric is at resonance at 10 MHz (see > datasheet of Kemel caps)! Above 10 MHz the impedance becomes inductive. EMI > is measured up to 1 GHz. They aren't - spread values are common to see, and there is a trend to smaller values. ( But I'll admit many just drop in 100nF ) I did see a good paper from Temic IIRC, on this. The key param, from a Vcc voltage noise perspective, is total system impedance, over the spectrum of the current spikes, at the pins. Another param, for RFI, is current loop area, and there local inductance makes a pi-filter, with any Cd. -jgArticle: 58282
How many bits in the coefficients? For 16 bit coef's I can
get that going well over 150 MHz with my IP, which has
embedded placement. Last time I looked at the Xilinx core,
they did things a little different so it would not achieve
the same speeds, but that was a while ago.
marlboro wrote:
> hi aubel,
>
> the FIRs has 5 taps, fix and symetric coefs. Both data and
> coef are 10 bits.
> I think its possible but take more time
> for manual placement.
>
> thanks anyway.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 58283
Hi,
I wonder if 'the panel' can help with this. Below find some VHDL
which invokes Synplify's syn_direct_enable directive. As the 'clock'
is going fast, I need the 'enable' signal to connect directly to the
clock enable pin of the CLBs' FFs in my Virtex II design. This gives
the design two cycles (enable is active every other cycle) set up time
before changing to the next state. So, syn_direct_enable would appear
to be the directive for me!
The problem is that when Synplify synthesizes this, FF data_int1
doesn't get the enable pin directly connected. Strangely enough,
data_int2 gets treated correctly.
Any ideas on why Synplify gets this wrong?
TIA, Syms.
p.s. Tried their support, the userid/password they emailed doesn't
work.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity direct_enable_test is
port (
signal res_n : in std_logic; -- General reset.
signal clock : in std_logic; -- clock 350MHz
signal toggle_in : in integer range 0 to 15; -- toggle
value
signal data : out std_logic -- data
);
end direct_enable_test;
architecture direct_enable_test_arch of direct_enable_test is
signal enable : std_logic;
signal data_int1 : std_logic;
signal data_int2 : std_logic;
signal toggle : integer range 0 to 15; -- toggle value
attribute syn_direct_enable: boolean;
attribute syn_direct_enable of enable : signal is true;
begin
data <= data_int1 or data_int2;
process (res_n, clock)
begin
if (res_n = '0') then
enable <= '0';
toggle <= 0;
elsif rising_edge (clock) then
enable <= not enable;
if enable = '1' then
toggle <= (toggle + 1) mod 16;
end if;
end if;
end process;
process (res_n, clock)
begin
if (res_n = '0') then
data_int1 <= '0';
elsif rising_edge (clock) then
if enable = '1' then
if toggle = 0 then
data_int1 <= not data_int1;
end if;
end if;
end if;
end process;
process (res_n, clock)
begin
if (res_n = '0') then
data_int2 <= '0';
elsif rising_edge (clock) then
if enable = '1' then
if toggle_in = 0 then
data_int2 <= not data_int2;
end if;
end if;
end if;
end process;
end direct_enable_test_arch;
Article: 58284You could try their newsgroup at news.synplicity.com "Symon" <symon_brewer@hotmail.com> wrote in message news:a28bc07f.0307181531.1ffe5cb@posting.google.com... > p.s. Tried their support, the userid/password they emailed doesn't > work.Article: 58285
No it was a fixed second order loop. The barrel shifts just increased the
gain.
Kevin Neilson wrote:
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3F134720.D19A8BCA@andraka.com...
> > Mine used a barrel shift in the feedback to get a gain that increased with
> the
> > size of the error. Had to do that to get a quick lock and still be able
> to
> > chase the reference. The reference was derived from a quad encoder on the
> > mechanical media path. The PLL had to adjust a process to keep a certain
> number
> > of events between encoder pulses. All in all, it was a pretty nasty
> problem
> > because of the dynamics and limited resolution of the encoder.
> >
> > Kevin Neilson wrote:
> >
>
> I like that idea. Actually, I recalled that mine had a time-varying gain,
> but it was much simpler. The gain was high before lock, and after locking,
> the gain switched to something lower. The gain was just implemented by
> left-shifting the output from the loop filter (which was just a comb or
> moving-average filter), so the gain could only be powers of two. Does the
> barrel shifter you describe increase the order of the loop? That probably
> makes it a lot harder to describe mathematically. I would have liked to do
> an analysis of mine, but of course I didn't have time, and for my
> application stability was much more important than lock time so I didn't
> really have to optimize it.
> -Kevin
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 58286I have a small VHDL project that I am attempting to get running under Quartus. Some of the errors I get are pretty obtuse like "Warning: No clock transition on bitportio:BitIOPorts|LEDReg[15] register". This is from the Analysis and Synthesis stage. To try to help isolate problems with the tool vs. my code, I am trying to compile the same code under Webpack 5.2i. But I can't get Webpack to understand my library package. The help file says to go to the "Sources" window and add the source file, then select "Move to Library" and choose the library from the dialog box. But I never get a dialog box. I can't find a way to *add* a new library and the Webpack help files are pretty obtuse. Is this a bug in Webpack? Is there no way to use a separate library file? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58287
"Henning Bahr" <Henning.Bahr@ncl.ac.uk> wrote in message news:8679149d.0307162201.49094c06@posting.google.com... > Hi there! > I hope this isn't too trivial: > I'm having a digital system with a finite state machine and a few > other modules which send a control signal to the FSM. Do you think it > is possible to use only clock and only posedge Flip Flops in such a > design? I can't manage it without the inverted clock so that the > control signals change at half the clock signal. But is there a way to > avoid this without violating setup and hold times? > > Cheers, > Henning Henning, I am assuming that the finite state machine and the "few other modules" are all in the FPGA. It is very possible to do what you ask about, and it is done day in and day out. As Peter Alfke said earlier, FPGAs are designed to have the clock to out time be longer than the hold time, assuming the signal propagated from Q to D input instantaneously. The only thing you have to worry about is the sum of clock to Q time, routing time, setup time and clock skew to be less than the clock period. That is what constraints are for -- to tell the place and route tool to meet that timing and to quantify it for you. Now let's assume that you do use the opposite edge, i.e., falling edge, of the clock. Also assume that you are not using a PLL or DLL. If the clock is not guaranteed to be perfectly symmetrical, then you must do additional analysis to determine what the high and low times are. You now need to factor this timing in, using additional constraints, to determine just how much time the tool should allow for the signal to make it to the opposite edge, i.e., the rising edge of the flip flop. This complicates timing and constraints, which detracts from the real task - to get a design working efficiently in a minimal amount of time. There are reasons to use opposite edges, but what you described above is not one of them. What you have described above is a synchronous design with one clock domain. Once you master a one clock design, you will be ready to move on to multiple clock designs where circuitry can be grouped into clock domains. Then you will have to learn how circuitry in one clock domain can talk reliably to circuitry in another clock domain. There are special rules to achieve this with great reliability, and it all comes under the heading of synchronous design. From my experience, only a small percentage of companies have taken the time and resources to document lessons learned (dating back to the 1970s) and generate design guides that cover this particular subject. These companies covet their design guides and expect their engineers to use it because they know it gives them a competitive edge. There are books, though, that cover this topic. From my experience, the companies that have not taken the time to document and generate design guides are also not reading these books, because I see a fair amount of asynchronous design usage, too. Good luck to you. Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL USAArticle: 58288
I am totally new in designing CPlD's (using Xilinx xcr3064), so what I going to ask may be totally rudimental to many but I would really appreciate any help in my problem. My problem is I am trying to design a unit with memory on board. What I would like to do is, try to feed and retrieve data from the unit to my computer but I am not sure how or what to do I need at both ends to interface the two, especially on the computer side. I am open to interface it any possible way, serial/parallel.Article: 58290
"James" <dinatouch@hotmail.com> wrote: > I cannot find a method to preload data to Block RAM (IDE enviroment is Xilinx ISE 5). Go to "Help"; "Online Documentation"; "Libraries Guide" Expand "Design Elements" Scroll down to "RAMB4_Sn" or "RAMB4_Sm_Sn" Double click on one of them. In the document window, scroll down to the instantiation examples. In the Verilog section you'll find something like: defparam user_instance_name.INIT_00 = 256_bit_hex_value; defparam user_instance_name.INIT_01 = 256_bit_hex_value; defparam user_instance_name.INIT_02 = 256_bit_hex_value; defparam user_instance_name.INIT_03 = 256_bit_hex_value; ... Is that what you were looking for? -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 58291
rickman wrote: > > I have a small VHDL project that I am attempting to get running under > Quartus. Some of the errors I get are pretty obtuse like "Warning: No > clock transition on bitportio:BitIOPorts|LEDReg[15] register". This is > from the Analysis and Synthesis stage. To try to help isolate problems > with the tool vs. my code, I am trying to compile the same code under > Webpack 5.2i. But I can't get Webpack to understand my library > package. > > The help file says to go to the "Sources" window and add the source > file, then select "Move to Library" and choose the library from the > dialog box. But I never get a dialog box. I can't find a way to *add* > a new library and the Webpack help files are pretty obtuse. Is this a > bug in Webpack? Is there no way to use a separate library file? I didn't get Webpack to handle my library, but I did find the problem with Quartus. Seems that Quartus has some issues with reporting problems as things totally unrelated. In this case I was generating a register enable by decoding an address. But I had an extra digit in the vector in the comparison. Rather than complain that it can't test equality on two different sized SLVs, it told me the clock on the register was stuck at GND or VCC depending on the particular register. Wow! This is two erroneous problem reports that have cost me several hours each. I wonder how many more I will find before I am done with this project. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58292
Hi all. I am attempting to design an All-Digital Phase Lock Loop for a motor control application. I know it's been done before, and I might even find an off the shelf part that does close to what I want, but some particular requirements force me to use a CPLD/FPGA. Anyway, I've seen several phase-detector/frequency-detector circuits and often see "Type I" or "Type IV". Is there any comprehensive list of phase/frequency detectors and/or advantages/disadvantages? I've Googled but I'm looking for some engineering insight from the people who've "been there, done that". Essentially, what I think I need from the phase/frequency detector are UP/DOWN signals to tell my system to get the counter-based NCO to run slower or faster. Are these typically called "bang-bang" type? Thanks for your help! Jay.Article: 58293
Hi, I have a problem with Multi device chain configuration circuit of Altera. My circuit have 2 EPC2 cascade mode and 2 EPF10K50 (Altera doc. AN 116.pdf page 11). The files .POF are 2. The first for the first device and the second for the second device. I try to programming with JTAG file .jcf. as follows: EPC2 -> File1.pof EPF10k50 -> -- EPC2 -> File2.pof EPF10k50 ->-- After the programming my devices are not configure.WHY? Please Help me... Thanks Paolo --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.500 / Virus Database: 298 - Release Date: 10/07/2003Article: 58294
Peter Ryser <ryserp@xilinx.com> wrote in message news:<3F1846C0.776CD1F5@xilinx.com>... > > If you want to work with EDK please contact your FAE and ask him to get > you access to the EDK reference design for ML300. He will be able to get you > access to the design. Hi Peter, when we received the EDK + DDR project, I also asked to be notified when a better EDK ref. design will be available, and so far have not got any more info, could you please enlight us what additional cores are available in the EDK ref. design you mentioned? ASFAIK TFT and Touchscreen are not implemented (or hopefully are now?) I have still having trouble to get EDK to work correctly using the obsoleted TFT ref. design - eg. display is looking in stripes 8 pixels missing after 8 ok pixels - if the problem is fixed and ref design availabl would be greate. anttiArticle: 58295
srisurya@yahoo.com (Srisurya Konduri) wrote in message news:<5e1276c1.0307182315.2b65b5c0@posting.google.com>... > I am totally new in designing CPlD's (using Xilinx xcr3064), so what I > going to ask may be totally rudimental to many but I would really > appreciate any help in my problem. > My problem is I am trying to design a unit with memory on board. What > I would like to do is, try to feed and retrieve data from the unit to > my computer but I am not sure how or what to do I need at both ends to > interface the two, especially on the computer side. I am open to > interface it any possible way, serial/parallel. 1 connect the memory pins to the pld 2 decide what interface to pc you use ie lpt, com, usb,.. lpt (printer port) is easiest just connect some pld pins to lpt port suggested minimum 4 like SPI interface and done, if the pld has more pins free then you can use 8 bit parallel interface as of hardware side its pretty trivial, software is what makes it work anttiArticle: 58296
Hi Folks, I am trying to get the Leonardo synthesis tool to use the available block ram within the FPGA. I have written a dual port RAM in VHDL and I am trying to synthesize on a Virtex II pro FPGA, which contains loads of available block RAM. My design synthesizes fine, but does not make use of the available block RAM. only LCs. Are current synthesis tools not intelligent enough to recognize RAM when they see it or is there a way to write a RAM file? I did not want the file to be limited to one family of FPGAs so that is the reason I wrote the dual port RAM file in VHDL. Are there any switches in Leonardo I can set, so do I have to write the RAM a different way ? Perhaps some synthesis tools can do this and others cannot. I would like to know which can, e.g. Synplify...as we can use both Leonardo and Synplify. Any replies greatly appreciated. BobArticle: 58297
stenasc@yahoo.com (Bob) wrote in message news:<20540d3a.0307190617.68af303d@posting.google.com>... > Hi Folks, > > I am trying to get the Leonardo synthesis tool to use the available > block ram within the FPGA. I have written a dual port RAM in VHDL and > I am trying to synthesize on a Virtex II pro FPGA, which contains > loads of available block RAM. > Perhaps some synthesis tools can do this and others cannot. I would > like to know which can, e.g. Synplify...as we can use both Leonardo > and Synplify. as your target is Virtex II Pro, you should use synplify as that is what was used for the V2PDK reference designs, that is if you like to use any of those then synplify is needed (XST fails). as of leonardo, I guess it can be used also for block ram but see my comment above, if you can use synplify as it is what Xilinx uses(used) for V2Pro developmemnt. :) anttiArticle: 58298
Symon Sorry if you had any problem accessing our web support. I forwarded your question to our technical support team. If you ever have any problem with the Web interface to technical support (at www.synplicity.com/support) You can always reach us through email at support@synplicity.com. Again, sorry for your inconvienience. One of our technical support engineers will be getting in touch with you next week. Andrew Dauman Synplicity, Inc. Symon wrote: > Hi, > I wonder if 'the panel' can help with this. Below find some VHDL > which invokes Synplify's syn_direct_enable directive. As the 'clock' > is going fast, I need the 'enable' signal to connect directly to the > clock enable pin of the CLBs' FFs in my Virtex II design. This gives > the design two cycles (enable is active every other cycle) set up time > before changing to the next state. So, syn_direct_enable would appear > to be the directive for me! > The problem is that when Synplify synthesizes this, FF data_int1 > doesn't get the enable pin directly connected. Strangely enough, > data_int2 gets treated correctly. > Any ideas on why Synplify gets this wrong? > TIA, Syms. > p.s. Tried their support, the userid/password they emailed doesn't > work. > > library IEEE; > use IEEE.STD_LOGIC_1164.all; > > entity direct_enable_test is > port ( > signal res_n : in std_logic; -- General reset. > signal clock : in std_logic; -- clock 350MHz > signal toggle_in : in integer range 0 to 15; -- toggle > value > signal data : out std_logic -- data > ); > end direct_enable_test; > > architecture direct_enable_test_arch of direct_enable_test is > > signal enable : std_logic; > signal data_int1 : std_logic; > signal data_int2 : std_logic; > signal toggle : integer range 0 to 15; -- toggle value > attribute syn_direct_enable: boolean; > attribute syn_direct_enable of enable : signal is true; > > begin > > data <= data_int1 or data_int2; > > process (res_n, clock) > begin > if (res_n = '0') then > enable <= '0'; > toggle <= 0; > elsif rising_edge (clock) then > enable <= not enable; > if enable = '1' then > toggle <= (toggle + 1) mod 16; > end if; > end if; > end process; > > process (res_n, clock) > begin > if (res_n = '0') then > data_int1 <= '0'; > elsif rising_edge (clock) then > if enable = '1' then > if toggle = 0 then > data_int1 <= not data_int1; > end if; > end if; > end if; > end process; > > process (res_n, clock) > begin > if (res_n = '0') then > data_int2 <= '0'; > elsif rising_edge (clock) then > if enable = '1' then > if toggle_in = 0 then > data_int2 <= not data_int2; > end if; > end if; > end if; > end process; > > end direct_enable_test_arch;Article: 58299
Thanks for the input, I understand what you are saying as in connect the pld to SPP, but what I dont understand is what software to use or code to start the communication and read the memory. I would real appreciate if you can forward me any examples/codes/links. antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0307190438.2fe7a38a@posting.google.com>... > srisurya@yahoo.com (Srisurya Konduri) wrote in message news:<5e1276c1.0307182315.2b65b5c0@posting.google.com>... > > I am totally new in designing CPlD's (using Xilinx xcr3064), so what I > > going to ask may be totally rudimental to many but I would really > > appreciate any help in my problem. > > My problem is I am trying to design a unit with memory on board. What > > I would like to do is, try to feed and retrieve data from the unit to > > my computer but I am not sure how or what to do I need at both ends to > > interface the two, especially on the computer side. I am open to > > interface it any possible way, serial/parallel. > > 1 connect the memory pins to the pld > 2 decide what interface to pc you use ie lpt, com, usb,.. > > lpt (printer port) is easiest just connect some pld pins to lpt > port suggested minimum 4 like SPI interface and done, > > if the pld has more pins free then you can use 8 bit parallel interface > > as of hardware side its pretty trivial, software is what makes it work > > antti
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