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Messages from 58375

Article: 58375
Subject: Re: Is QuickSwitch devices a good method to interface fpga 3.3v(spartan IIE) and 5v logic divices?
From: bijeshvm@hotmail.com (bijesh v.m.)
Date: 21 Jul 2003 22:41:41 -0700
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F1BEFFC.61ECA2DA@yahoo.com>...
> "bijesh v.m." wrote:
> > 
> > Hi all,
> > 
> >  Am new to fpga. I would like to know about QuickSwitch devices and
> > whether they are ideal to interface fpga (3.3v) with devices with
> > different (5v)logic levels.Please share your knowledge on the
> > following questions.
> > 
> > 1. Is it a good practice to use Quickswitch to interface (3.3v)
> > spartan IIE fpga and (5v) logic devices?
> 
> That is one way of dealing with 5 volt signals.  Or you can use a 5 volt
> tolerant FPGA in the first place.  I am finding that the Altera ACEX
> EP1K family is a good choice also and saves board space if you have a
> lot of 5 volt signals to interface.  
> 
> 
> > 2. Is it a commonly used approch to use Quickswitch devices  with
> > fpga? If not so what are its disadvantages?
> 
> The disadvantage is the extra board space.  
> 
> > 3. Is it a recent technology?
> 
> No, series pass switches have been used for voltage shifting for years.  
> 
> 
> > From what I read and understood is that,Quickswitches operation is in
> > effctive to connecting a small resistance in series between the two
> > logoc levels.
> 
> Not exactly.  They are a variable resistance where the resistance
> increases as the input voltage gets close to the Vdd voltage.  This is
> because a high input voltage reduces the drive voltage which turns off
> the series pass transistor.  So at lower voltage levels the switch is
> low resistance and has nearly no delay. 
> 
> > I read about Quickswitch devices from the site
> > http://www.idt.com/products/pages/Bus_Switches-QS316245.html.
> > 
> > 4. At frequencies (say 50MHZ) whether the quickswitch devices will
> > introduce significat delay?
> 
> The delay is less than a nanoSecond.  These switches are almost like a
> wire.  
> 
> 
> > 5.I think bidirectional data flow capability of the quickswitch device
> > is a very good feature( no need of additional data direction control
> > signals)compared to other Transceiver chips (like 74LVX4245).Whats
> > your thinking?
> 
> It all depends on your application.  For example, if you were adding a
> bunch of IO ports to control 5 volt signals from a 3 volt device then
> you could do better with a register since you can use a lot fewer pins
> on the FPGA.  Adding extra registers could share the data bus and would
> only require adding control signals. 
> 
> Also keep in mind that the quick switch will not let the 3 volt device
> *drive* to 5 volts if that is needed.  To get a signal to 5 volts you
> will need your low voltage driver to be open collector (drain) and a
> pullup to 5 volts on the output side of the switch.  This will be a bit
> slower than a 5 volt, direct drive, totem pole output.  
> 
> -- 
> 
> Rick "rickman" Collins
> 
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

Hi Rick,
 I was planning to use Quickswitch to interface a 5v TTL
microcontroller with Spartan IIE fpga in my design. From your replay
what I understood is that I shoud select a open drain o/p pin in my
fpga to tranfer a 5V I/P to the microcontroller.
  You wrote to point 5: 
 "To get a signal to 5 volts you will need your low voltage driver to
be open collector (drain) and a pullup to 5 volts on the output side
of the switch"

1. This I think brings a contraint to my design and I would like to
avoid this. Please suggest a good approch.

2. I would like to know ( our comments :) ) why this issue was not
mensioned in the Quickswitch site. I was misleaded or misunderstood by
the block diagrams in the document which shows interfacing 3.3V CPU
and 5V accessory devices ( application note
http://www.idt.com/docs/AN_11.pdf").

regards
Bijesh

Article: 58376
Subject: Re: asynchronous FIFO
From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Date: Tue, 22 Jul 2003 06:05:48 GMT
Links: << >>  << T >>  << A >>

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F1C845E.49CD7A06@xilinx.com...
> Here is a slight simplification offering a very compact layout.
> Start with two binary counters.
> For the write counter only: convert it to Grey and reclock the output
> with the read clock, then re-convert to binary (without registering),
> and do your subtraction.
>
> Binary counters are simpler than Grey counters, and the conversion is
> just a chain of concatenating XORs. I always do the bin-Grey conversion
> by XORing the D-inputs of the binary counter, which keeps the binary and
> Grey values in synchronism. The bin-Grey converter has a ripple delay,
> but that should not bother you at your benign frequencies.
> Obviously, you need to use the binary counters for addressing the
> dual-port RAM.

I was about to think it was obvious that you needed Grey counters, and then
I read this one.

It would seem if both read and write counters were Grey, then it should work
fine.

Do you mean convert the write count to Grey, latch that with the write clock
(so it would agree with a Grey write counter), then relatch with the read
clock?  Otherwise, it would seem that delays through the bin-Grey converter
would cause glitches in the reclocked output.

As usual for asynchronous circuits, the clocks may be slow, but with
arbitrary phase between them you have to watch the clocks carefully.

-- glen



Article: 58377
Subject: Re: Xilinx GCLK voltages
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Tue, 22 Jul 2003 17:05:15 +1000
Links: << >>  << T >>  << A >>
Avrum wrote:
> Not quite...

[snip clear concise description]

Thanks again for detailed reply - very helpful!  You should be writing 
doco for Xilinx! :)

John


Article: 58378
Subject: Re: Is QuickSwitch devices a good method to interface fpga 3.3v(spartan IIE) and 5v logic divices?
From: "Markus Sponsel" <msponsel@nospam.profichip.com>
Date: Tue, 22 Jul 2003 10:58:25 +0200
Links: << >>  << T >>  << A >>
bijesh v.m. wrote:
> rickman <spamgoeshere4@yahoo.com> wrote in message
> news:<3F1BEFFC.61ECA2DA@yahoo.com>...
>> "bijesh v.m." wrote:
>>>
>>> Hi all,
>>>
>>>  Am new to fpga. I would like to know about QuickSwitch devices and
>>> whether they are ideal to interface fpga (3.3v) with devices with
>>> different (5v)logic levels.Please share your knowledge on the
>>> following questions.
>>>
>>> 1. Is it a good practice to use Quickswitch to interface (3.3v)
>>> spartan IIE fpga and (5v) logic devices?
>>
>> That is one way of dealing with 5 volt signals.  Or you can use a 5
>> volt
>> tolerant FPGA in the first place.  I am finding that the Altera ACEX
>> EP1K family is a good choice also and saves board space if you have a
>> lot of 5 volt signals to interface.
>>
>>
>>> 2. Is it a commonly used approch to use Quickswitch devices  with
>>> fpga? If not so what are its disadvantages?
>>
>> The disadvantage is the extra board space.
>>
>>> 3. Is it a recent technology?
>>
>> No, series pass switches have been used for voltage shifting for
>> years.
>>
>>
>>> From what I read and understood is that,Quickswitches operation is
>>> in
>>> effctive to connecting a small resistance in series between the two
>>> logoc levels.
>>
>> Not exactly.  They are a variable resistance where the resistance
>> increases as the input voltage gets close to the Vdd voltage.  This
>> is
>> because a high input voltage reduces the drive voltage which turns
>> off
>> the series pass transistor.  So at lower voltage levels the switch is
>> low resistance and has nearly no delay.
>>
>>> I read about Quickswitch devices from the site
>>> http://www.idt.com/products/pages/Bus_Switches-QS316245.html.
>>>
>>> 4. At frequencies (say 50MHZ) whether the quickswitch devices will
>>> introduce significat delay?
>>
>> The delay is less than a nanoSecond.  These switches are almost like
>> a
>> wire.
>>
>>
>>> 5.I think bidirectional data flow capability of the quickswitch
>>> device
>>> is a very good feature( no need of additional data direction control
>>> signals)compared to other Transceiver chips (like 74LVX4245).Whats
>>> your thinking?
>>
>> It all depends on your application.  For example, if you were adding
>> a
>> bunch of IO ports to control 5 volt signals from a 3 volt device then
>> you could do better with a register since you can use a lot fewer
>> pins
>> on the FPGA.  Adding extra registers could share the data bus and
>> would
>> only require adding control signals.
>>
>> Also keep in mind that the quick switch will not let the 3 volt
>> device
>> *drive* to 5 volts if that is needed.  To get a signal to 5 volts you
>> will need your low voltage driver to be open collector (drain) and a
>> pullup to 5 volts on the output side of the switch.  This will be a
>> bit
>> slower than a 5 volt, direct drive, totem pole output.
>>
>> --
>>
>> Rick "rickman" Collins
>>
>> rick.collins@XYarius.com
>> Ignore the reply address. To email me use the above address with the
>> XY
>> removed.
>>
>> Arius - A Signal Processing Solutions Company
>> Specializing in DSP and FPGA design      URL http://www.arius.com
>> 4 King Ave                               301-682-7772 Voice
>> Frederick, MD 21701-3110                 301-682-7666 FAX
>
> Hi Rick,
>  I was planning to use Quickswitch to interface a 5v TTL
> microcontroller with Spartan IIE fpga in my design. From your replay
> what I understood is that I shoud select a open drain o/p pin in my
> fpga to tranfer a 5V I/P to the microcontroller.
>   You wrote to point 5:
>  "To get a signal to 5 volts you will need your low voltage driver to
> be open collector (drain) and a pullup to 5 volts on the output side
> of the switch"
>
> 1. This I think brings a contraint to my design and I would like to
> avoid this. Please suggest a good approch.
>
> 2. I would like to know ( our comments :) ) why this issue was not
> mensioned in the Quickswitch site. I was misleaded or misunderstood by
> the block diagrams in the document which shows interfacing 3.3V CPU
> and 5V accessory devices ( application note
> http://www.idt.com/docs/AN_11.pdf").
>
> regards
> Bijesh

Hi Bijesh,

I am not Rick, but we have used the quickswitches exactly for the case
you are dealing with. We connected a C165 microcontroller to an Xilinx
Virtex-E device and it works superb. The QS cannot drive 5 Volts, that
is correct, but if you are using a device with TTL inputs (as you do)
there will be no problem. Application Note AN11 is absolutely correct
and we did the design as mentioned there (Diode + parallel Resistor).
Works now for half a year without problems.

Hope this helps a bit,

          Markus Sponsel

#################################################
profichip GmbH
Einsteinstraße 6
91074 Herzogenaurach
Germany
#################################################

To reply me directly remove "XYZ".



Article: 58379
Subject: Re: asynchronous FIFO
From: rjd@transtech-dsp.com (rob d)
Date: 22 Jul 2003 02:28:03 -0700
Links: << >>  << T >>  << A >>
I am very, very curious that Peter did not suggest the async fifo in
coregen. We have been using it since version 3. I think that it's at 5
now but there is nothing documented to say whether later versions are
just adding support for new devices.

We had teething troubles with simulation early on, and our test code
still has legacy functionality that clocks the read side at many times
less than the write frequency through to about twice, in about 15
steps (how to confuse a fitter, have multiple DCM's and counters and
then mux them onto a clock). I don't remeber the core ever failing in
use, just in simulation.

Rob

Article: 58380
Subject: (repost) What are the maximum filter specs you've seen?
From: "Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk>
Date: Tue, 22 Jul 2003 10:48:35 +0100
Links: << >>  << T >>  << A >>

Hello folks,

Just a few quick questions regarding filters and actual designs on FPGAs:

What are the largest interpolation/decimation factors you have used/seen
used?

What is the largest number of independant data channels you have used
through one filter or N instances of the same filter? (no. of
channels = N)

What is the largest bit-width input data samples you have used/seen used?

Thanks for your time,

Ken


--
To reply by email, please remove the _MENOWANTSPAM from my email address.



Article: 58381
Subject: Re: help needed..... ERROR:MapLib:30 - Bad format for LOC constraint AB12 on rx.
From: Martin Kellermann <martin.kellermann@nospam.xilinx.com>
Date: Tue, 22 Jul 2003 13:16:59 +0200
Links: << >>  << T >>  << A >>
That would be an environment variable to set.
But I'd check my pin-locks again. Normally that comes up when you try to 
use a pin that's not available (e.g. NC)

Martin


paraag wrote:

> hi
> 
> The solution for this is to 
> set XIL_MAP_LOCWARN=1 
> but where do I do this , can someone help me??
> Thanx
> Paraag
> 


Article: 58382
Subject: Re: device selection for game system
From: russelmann@hotmail.com (Rudolf Usselmann)
Date: 22 Jul 2003 06:57:07 -0700
Links: << >>  << T >>  << A >>
antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0307170322.4bfe9f92@posting.google.com>...
> david.tucker@goliathindustries.com (David Tucker) wrote in message news:<e67c452f.0307010747.390938fc@posting.google.com>...
> > I'm working on implementing a custom game boy advance cartrige with
> > the following features:
> > 
> > - 4-16MByte flash rom (bank switched to a 24 pin buss)
> > - 32kbyte save ram (game state save, can be stored in flash rom if needed)
> > - usb-to-pc link
> > - in system reprogramability via usb
> > - hardware assist for MP3/OGG decoding or similar lossy compression
> >(target compression is 8bit, 2-8Kbit/sec, for 30min of audio in 2mbyte of rom)
> > 
> > Space is a huge concern, my target board size is 1x2 inches.  Plus my
> > target cost in quantitys of 1,000 or more is $10-$15 total for the
> 
> space is not your concern directly, 1x2 inches (if fully avaiable for
> components and both sides allowed) is today pretty much enough real-estate.
> 
> price is your concerne, and real one.
> 
> flash+ram+logic for bank switching == fits the target price
> 
> if you need USB then it comes real problem (at your target price)


I agree, the biggest problem is cost.

If you add a Spartan FPGA, you can use my free USB 1.1
IP core, all you need is a $0.50 USB transceiver from
Phillips and a USB connector.
However, the FPGA and the config eeprom will cost you
around $30 alone, without the flash. You can however
add some hw support for MP3, or even include a 8051
compatible micro in the FPGA.

Regards,
rudi               
--------------------------------------------------------
www.asics.ws  --- Solutions for your ASIC/FPGA needs ---
----------------- FPGAs * Full Custom ICs * IP Cores ---
FREE IP Cores --> http://www.asics.ws/ <-- FREE IP Cores

Article: 58383
Subject: FPGA Editor
From: fpga_uk@yahoo.co.uk (Isaac)
Date: 22 Jul 2003 07:29:35 -0700
Links: << >>  << T >>  << A >>
Hi Guys,

In Xilinx FPGA editor when you have finished your design and you can
see the routed desing using Xilinx FPGA Editor.
In that area used by the wire is more than the area used by IOB. How
can I place the wire the way I wanted to. Is FPGA editor can be used
to accomplish this task.

Secondly, how can I concerntrate the desing in one part of the chip
rather than to use automatically generated design.

Cheers 

Isaac

Article: 58384
Subject: Xilinx WebPack support "dual edge clock" ??
From: Erik Spaenig <erik.spaenigREMOVE@seitzinger-popp.de>
Date: Tue, 22 Jul 2003 17:41:21 +0200
Links: << >>  << T >>  << A >>
Hello NG,

I have a problem with the new WebPack 5.2i (SP2)
wenn i compile an old VHDL-source (from Weback 4.x)
I get the error message "Xst:797 : unsupported Clock statement" for this
>>>>>
process (I_CLK_100)
begin
   if (I_CLK_100'event) then  --I_CLK_100 dual edge
     V_FRAME_OLD1 <= I_FRAME_I;     --1 bis  5 ns Verzögerung
     V_FRAME_OLD  <= V_FRAME_OLD1;  --6 bis 10 ns Verzögerung
   end if;
end process;
<<<<<
I found in the "Language templates/VHDL" only D-Latches with rising edge
>>>>> if (CLK'event AND CLK='1') then <<<<<
I can remember that I have my code copyed from the templates of the old WebPack.

any suggestion ??
Thanks for help,

Erik

Article: 58385
Subject: Re: Xilinx WebPack support "dual edge clock" ??
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Tue, 22 Jul 2003 15:43:28 +0000 (UTC)
Links: << >>  << T >>  << A >>
Erik Spaenig <erik.spaenigREMOVE@seitzinger-popp.de> wrote:
: Hello NG,

: I have a problem with the new WebPack 5.2i (SP2)
: wenn i compile an old VHDL-source (from Weback 4.x)
: I get the error message "Xst:797 : unsupported Clock statement" for this
:>>>>>
: process (I_CLK_100)
: begin
:    if (I_CLK_100'event) then  --I_CLK_100 dual edge
:      V_FRAME_OLD1 <= I_FRAME_I;     --1 bis  5 ns Verzögerung
:      V_FRAME_OLD  <= V_FRAME_OLD1;  --6 bis 10 ns Verzögerung
:    end if;
: end process;
: <<<<<
: I found in the "Language templates/VHDL" only D-Latches with rising edge
:>>>>> if (CLK'event AND CLK='1') then <<<<<
: I can remember that I have my code copyed from the templates of the old WebPack.

: any suggestion ??

Only coolrunner II has dual edge triggerd flipflops. So your statement above
can't be synthezised. Either double your clock with a DLL or use two code
pathes, with one set of flipflop clocked on one edge and the rest on the
other.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 58386
Subject: Re: How to choose FPGA device?
From: Andrew Paule <lsboogy@qwest.net>
Date: Tue, 22 Jul 2003 10:49:29 -0500
Links: << >>  << T >>  << A >>
what do you want to do - there are many good manufacturers out there.

Andrew

yxl wrote:

>I found there are many FPGA devices, how to choose a good one for myself?
>  
>


Article: 58387
Subject: Re: Xilinx WebPack support "dual edge clock" ??
From: Erik Spaenig <erik.spaenigREMOVE@seitzinger-popp.de>
Date: Tue, 22 Jul 2003 17:57:31 +0200
Links: << >>  << T >>  << A >>
Uwe Bonnes wrote:

> Only coolrunner II has dual edge triggerd flipflops. So your statement above
> can't be synthezised. Either double your clock with a DLL or use two code
> pathes, with one set of flipflop clocked on one edge and the rest on the
> other.

I am realy sure that my old design work fine in a SpartanII with the WebPack 4.x

Erik

Article: 58388
Subject: Re: Xilinx WebPack support "dual edge clock" ??
From: "John_H" <johnhandwork@mail.com>
Date: Tue, 22 Jul 2003 16:06:12 GMT
Links: << >>  << T >>  << A >>
But since the Spartan-II silicon doesn't have dual-edged register, how would
you expect the WebPack to translate your statement into single edged
registers?


"Erik Spaenig" <erik.spaenigREMOVE@seitzinger-popp.de> wrote in message
news:bfjmk8$qof$00$2@news.t-online.com...
> Uwe Bonnes wrote:
>
> > Only coolrunner II has dual edge triggerd flipflops. So your statement
above
> > can't be synthezised. Either double your clock with a DLL or use two
code
> > pathes, with one set of flipflop clocked on one edge and the rest on the
> > other.
>
> I am realy sure that my old design work fine in a SpartanII with the
WebPack 4.x
>
> Erik



Article: 58389
Subject: Re: asynchronous FIFO
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 22 Jul 2003 09:21:34 -0700
Links: << >>  << T >>  << A >>


Glen Herrmannsfeldt wrote:"
> I was about to think it was obvious that you needed Grey counters, and then
> I read this one.
In a FIFO you can have any type of counter, as long as read and write
count the same way. Grey coding is needed only for control functions
that have to cross the clock boundary.
> 
> Do you mean convert the write count to Grey, latch that with the write clock
> (so it would agree with a Grey write counter), then relatch with the read
> clock? 
Yes

> As usual for asynchronous circuits, the clocks may be slow, but with
> arbitrary phase between them you have to watch the clocks carefully.
Yes, you have to be paranoid. But there is no problem with crossing the
clock domain boundary using a Grey signal.

So, once more, and to indicate the efficiency I count the flip-flops per
address bit, the remaining logic is free in the associated LUTs.

Binary read counter: first FF (read clock)
Binary write counter: second FF (write clock)
Grey copy of write counter: third FF (write clock)
transferred to read clock, without ANY logic in-between: fourth FF (read clock)
converted to binary, subtracted from binary read counter. Really needs
no flip-flop, since everything is synchronous with the read clock, but
it might be nice to register the count output to eliminate the potential
synchronous glitches right after the read clock ( at the cost of latency).

Sum total four flip-flops, two clocked by write, two by read.
That is half a CLB in Virtex-II or Spartan3.
So you can address and control a 1024-deep FIFO with five CLBs.

In case anybody is interested, here are the equations for binary-to-Grey:

Gn = Bn XOR B(n+1)  

and for Grey to binary:

Bn = Gn XOR B(n+1)         note the speed-limiting ripple structure

With both conversions: for the MSB:  G=B

Peter Alfke

Article: 58390
Subject: Re: Xilinx WebPack support "dual edge clock" ??
From: Erik Spaenig <erik.spaenigREMOVE@seitzinger-popp.de>
Date: Tue, 22 Jul 2003 18:29:37 +0200
Links: << >>  << T >>  << A >>
Hello,

> But since the Spartan-II silicon doesn't have dual-edged register, how would
> you expect the WebPack to translate your statement into single edged
> registers?
without any warning or error ??

Erik

Article: 58391
Subject: Re: Distributed RAM
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 22 Jul 2003 09:30:18 -0700
Links: << >>  << T >>  << A >>
Kuan,
BlockSelect RAM is just another word for the Xilinx BlockRAM, which is a
dual-port RAM of 18 kilobits size. See the data sheet for Virtex-II or Spartan3.

The difference between 400 and 500 MHz is mainly Marketing, different
degrees of aggressiveness in describing super-optimized design structures.

Greetings
Peter
===================
Kuan Zhou wrote:
> 
> Hi,
>    Thank you for your reply. How about Block SelectRAM?
> Is it a unique feature of Xilinx too?
>    I checked the website recently.It says the fastest FPGA in
> Xilinx has a system clock of 400 MHz while the fastest one in
> Altera is 500 MHz. What's the main difference which leads to
> the difference of speed? The speed difference is not big though.
> 
>    Thank you very much!
> 
> sincerely
> -------------
> Kuan Zhou
> ECSE department
> 
> On Mon, 21 Jul 2003, Peter Alfke wrote:
> 
> > In Xilinx devices, the 4-input LUTs can also be used as 16-bit RAM. That
> > means each LUT can be a RAM with 4 address inputs and one Din and one Dout.
> > There are also ways to combine two LUTs to form a 16-bit dual-port RAM.
> > Compared to BlockRAMs, these distributed RAMs are more flexible and
> > faster, but they require more external logic when they are expanded to
> > greater depth.
> > The LUT can also be configured to be a 16-bit shift register (LSR16).
> > Distributed RAM (LUT-RAM) is only available in Xilinx FPGA families...
> > Peter Alfke, Xilinx.
> > ==========
> > Kuan Zhou wrote:
> > >
> > > Hi,
> > >    Can anybody tell me the advantage of distributed RAM and the resources
> > > descriping it?
> > >
> > > sincerely
> > > -------------
> > > Kuan Zhou
> > > ECSE department
> >
> >

Article: 58392
Subject: Re: Phase / frequency detector types
From: symon_brewer@hotmail.com (Symon)
Date: 22 Jul 2003 09:42:41 -0700
Links: << >>  << T >>  << A >>
Hi Jerry,
       I agree! The circuit in 'Dean's Book' I referred to doesn't use
tri-states, it uses a diff amp integrator driven by the signals that
would've driven the tri-states. This also prevents "galloping ghost",
if I understand your terminology right!? As I learned from the 'book'
this fixes (or can fix) problems with charge leakage from the
tri-state, power supply noise on the tri-state drivers. It also means
the spurs resulting because, typically, the integrated voltage isn't
midway between the rails of the tri-state driver, are lower and more
predictable.
             Syms.


Jerry Avins <jya@ieee.org> wrote in message news:<3F1C7F5F.F94678C2@ieee.org>...
> Symon wrote:
> > 
> > Hi,
> >    Try https://www.national.com/appinfo/wireless/files/DeansBook_4_01.pdf
> > for a good read on PLLs. I'm thinking of using the design in chapter
> > 12 with the XAPP0028 circuit minus the tri-states.
>   ...
> 
> In most hardware designs, tri state is a way to lock a steady charge on
> the integrating cap, instead of always ramping it up or down, "galloping
> ghost" style. Applied that way, it reduces phase jitter.
> 
> Jerry

Article: 58393
Subject: Re: asynchronous FIFO
From: "Kevin Neilson" <kevin_neilson@removethistextcomcast.net>
Date: Tue, 22 Jul 2003 17:32:02 GMT
Links: << >>  << T >>  << A >>

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F1C845E.49CD7A06@xilinx.com...

> Obviously, you need to use the binary counters for addressing the
> dual-port RAM.
>
> Peter Alfke, Xilinx
> =================

Why couldn't one address the RAM with Gray pointers?
-Kevin



Article: 58394
Subject: Re: FPGA Editor
From: Philip Freidin <philip@fliptronics.com>
Date: Tue, 22 Jul 2003 17:42:16 GMT
Links: << >>  << T >>  << A >>
On 22 Jul 2003 07:29:35 -0700, fpga_uk@yahoo.co.uk (Isaac) wrote:
>Hi Guys,
>
>In Xilinx FPGA editor when you have finished your design and you can
>see the routed desing using Xilinx FPGA Editor.
>In that area used by the wire is more than the area used by IOB.

I don't know what you mean.

>How
>can I place the wire the way I wanted to. Is FPGA editor can be used
>to accomplish this task.

Yes. It is an editor. You need to change the operating mode from
read-only to "read-write".

File->Main Properties->Edit Mode. This is also available in the
File->Open pop-up

Doing manual routing is not easy. You will need to carefully read
the documentation. Sometimes it is best to start by practicing on
an empty design (vreated new in the FPGA editor), until you are
competent at doing the manual routing commands. Then do it on
your real design.

>Secondly, how can I concerntrate the desing in one part of the chip
>rather than to use automatically generated design.

Yes. You need to constrain your design BEFORE you run place-and-route.
You should probably use an Area Constraint.

>Cheers 
>Isaac

Philip Freidin


Philip Freidin
Fliptronics

Article: 58395
Subject: Re: Phase / frequency detector types
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 22 Jul 2003 10:44:02 -0700
Links: << >>  << T >>  << A >>
If you worry about undefined 3-state levels, you can drive the pin with
either a 50% voltage divider or even from an external source with the
appropriate voltage. Since the active outputs have an impedance far
below 100 Ohm (often around 10 Ohm), there is ample room for creativity.

Peter Alfke
================
Symon wrote:
> 
> Hi Jerry,
>        I agree! The circuit in 'Dean's Book' I referred to doesn't use
> tri-states, it uses a diff amp integrator driven by the signals that
> would've driven the tri-states. This also prevents "galloping ghost",
> if I understand your terminology right!? As I learned from the 'book'
> this fixes (or can fix) problems with charge leakage from the
> tri-state, power supply noise on the tri-state drivers. It also means
> the spurs resulting because, typically, the integrated voltage isn't
> midway between the rails of the tri-state driver, are lower and more
> predictable.
>              Syms.
> 
> Jerry Avins <jya@ieee.org> wrote in message news:<3F1C7F5F.F94678C2@ieee.org>...
> > Symon wrote:
> > >
> > > Hi,
> > >    Try https://www.national.com/appinfo/wireless/files/DeansBook_4_01.pdf
> > > for a good read on PLLs. I'm thinking of using the design in chapter
> > > 12 with the XAPP0028 circuit minus the tri-states.
> >   ...
> >
> > In most hardware designs, tri state is a way to lock a steady charge on
> > the integrating cap, instead of always ramping it up or down, "galloping
> > ghost" style. Applied that way, it reduces phase jitter.
> >
> > Jerry

Article: 58396
Subject: Re: asynchronous FIFO
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 22 Jul 2003 11:04:18 -0700
Links: << >>  << T >>  << A >>
You can use any type counter you can imagine, as long as read and write
counter sequences are identical.
In my suggestion, there is no Grey counter in the read domain, but there
are binary counters in both domains. That's why you "obviously"have to
use these. I have tried to simplify this design as much as possible.
As Albert Einstein once said: 
Everything should be made as simple as possible, but not any simpler...

Peter Alfke
====================
Kevin Neilson wrote:
> 
> "Peter Alfke" <peter@xilinx.com> wrote in message
> news:3F1C845E.49CD7A06@xilinx.com...
> 
> > Obviously, you need to use the binary counters for addressing the
> > dual-port RAM.
> >
> > Peter Alfke, Xilinx
> > =================
> 
> Why couldn't one address the RAM with Gray pointers?
> -Kevin

Article: 58397
Subject: Internal Error again in Quartus II 3.0
From: spring <spring555555@yahoo.com>
Date: Tue, 22 Jul 2003 15:58:01 -0400
Links: << >>  << T >>  << A >>
Hi, all,
Does anyone know how to deal with the annoying "Internal Error" with 
whatever Quartus II 3.0 or Max+plus II? I migrated a design from 
Max+plus II to Quartus II, imported the assignment from .acf file, then 
run compilation. The Quartus showed the "Interanl Error" with following 
message:
“Internal Error: Sub-system: ASMDB, File: asmdb_mux.cpp, Line: 445
ASMDB_MUX error: RAM_MUX::select : index out of range (index = 2048, 
size = 2048) : last archgroup encountered: type = RAM_CONTENT_FLEX10KE
Quartus II Version 3.0 Build 199 06/26/2003 SJ Full Version”
And compilation was cancelled!
I was hoping that the new Quartus II 3.0 would probably be better than 
Max+plus II. I am wrong. I would guess that the Quartus was designed by 
the same people. Besides, every time I am looking for the mySupport on 
the Altera website, the only thing they could do is asking my design and 
all my project files, although I gave them all the detailed information, 
steps, their software messages.
Any input would be appreciated.
spring


Article: 58398
(removed)


Article: 58399
Subject: Re: FPGA Editor
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 22 Jul 2003 16:23:29 -0400
Links: << >>  << T >>  << A >>
Philip Freidin wrote:
> 
> On 22 Jul 2003 07:29:35 -0700, fpga_uk@yahoo.co.uk (Isaac) wrote:
> >Hi Guys,
> >
> >In Xilinx FPGA editor when you have finished your design and you can
> >see the routed desing using Xilinx FPGA Editor.
> >In that area used by the wire is more than the area used by IOB.
> 
> I don't know what you mean.
> 
> >How
> >can I place the wire the way I wanted to. Is FPGA editor can be used
> >to accomplish this task.
> 
> Yes. It is an editor. You need to change the operating mode from
> read-only to "read-write".
> 
> File->Main Properties->Edit Mode. This is also available in the
> File->Open pop-up
> 
> Doing manual routing is not easy. You will need to carefully read
> the documentation. Sometimes it is best to start by practicing on
> an empty design (vreated new in the FPGA editor), until you are
> competent at doing the manual routing commands. Then do it on
> your real design.
> 
> >Secondly, how can I concerntrate the desing in one part of the chip
> >rather than to use automatically generated design.
> 
> Yes. You need to constrain your design BEFORE you run place-and-route.
> You should probably use an Area Constraint.

The real problem with manual editing a design is maintenance.  I have
worked on two designs which required manual edits to the routing.  One
was a very simple routing change to optimize a very short path where the
chip was muxing a clock.  But every time a new P&R was done, it had to
be edited to get this small improvement in routing time.  So we had to
document this change step by step so the next person to work on the
design could repeat the process.  

The other was a similar change for a clock multiplexor, but was more
extensive.  This was done by someone else and a couple of years later
when we were reworking the design, we could not find any documentation
on the change.  This led to a process of trying to trace the ownership
of the design back to the original designer who happened to be my second
level manager.  Lets just say that this process was not conducive to my
career advancement at that point since I have been sprinkling my
exploration with some amount of criticism about the lack of
documentation.  

The odd thing was that no one ever produced any real documentation of
that hand routing.  The second level manager gave a few of us a demo of
what needed to be changed and how to do it.  It seems clear that some
companies make do with oral tradition rather than written
documentation.  

So be aware of how important documentation of hand editing can be.  The
process may seem simple, but it can be difficult to convey exactly how
to do it. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX



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