Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 59125

Article: 59125
Subject: Re: Upgrading OS or WebPack
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 08 Aug 2003 18:15:57 -0400
Links: << >>  << T >>  << A >>
Aart van Beuzekom wrote:
> 
> Hei,
> 
> I will start developing FPGA applications with WebPack. My problem is
> that my OS is WinNT, which is not supported by WebPack 5.2i. I've got a
> CD laying round here with WebPack version 4.2WP0.0.
> 
> Can anybody tell me if the advantages of v. 5.2i are so much that
> upgrading to Win2000 really is necessary?
> 
> My application will run on a Spartan-II device. Clock speed wil not be
> an issue, but efficient use of logic cells might be.

There are other reasons to upgrade to Win2000 and it can be fairly
painless.  If you are interested, email me. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 59126
Subject: Re: speeding up quartus
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Fri, 08 Aug 2003 16:39:06 -0700
Links: << >>  << T >>  << A >>
Don S wrote:
> I'm a sysadmin looking at a problem that a designer is having with
> slow turn around times in Altera Quartus. The turn around time on a 
> compile is about 1 hr on a AMD 1700+ with 1 gig of memory. Quartus 
> version is 2.1 running on Win2K SP2.

Gosh. I wish I had a sysadmin. Any openings? :)

One hour is not bad for synthesis and place+route
on a medium sized FPGA.

> There is apparently a way to lock down the layout of certain blocks
> and/or do an incremental compile so that everything would not have to 
> be re-synthesised but the designer says that it doesn't seem to work 
> correctly. 

I haven't even tried the "logic-lock" place+route locker because
things change too much and I don't do that many place+routes.

You should turn on "smart-compile" to save the cache.
Hard drives are cheap.

> Any pointers would be greatly appreciated.

A simulation recompile and rerun only takes a few minutes.
You might suggest the designer spend more time on the
testbench and less in synthesis/place+route.

  -- Mike Treseler


Article: 59127
Subject: Re: Virtex-II RocketIO: Serial ATA?
From: Andrew Paule <lsboogy@qwest.net>
Date: Fri, 08 Aug 2003 19:28:53 -0500
Links: << >>  << T >>  << A >>
This might be a place to go to an ON NBSG16VS part, and do the power 
rails to get the vcm into spec, unless you want to AC couple.  They can 
be set from 100mV to 800 mV (you want about 500 if I remember 
correctly), but don't get the BGA - they are dropping BGA's like crazy 
(too much lead inductance, you'll make rise time spec, but not by much 
unless you're very careful) - the QFN's can go to 35ps.

Andrew

Paul Gentieu wrote:

> The Xilinx web page describing the RocketIO serdes mentions in passing 
> that it can support Serial ATA. But I don't see any support for 
> out-of-band signaling, and the serdes voltage swing and common-mode 
> levels don't seem compatible either.
>
> So, it seems that significant external circuitry would be required, 
> and it would be kludgy. Is there an appnote for doing this? Dedicated 
> SATA Phy chips seem pretty hard to find.
>
> Of course, a real SATA-compatible transceiver in the next generation 
> of the FPGA would be preferable...
>
> -Paul
>


Article: 59128
Subject: Re: I am new and I want to help
From: alw@al-williams.com (Al Williams)
Date: 8 Aug 2003 17:33:04 -0700
Links: << >>  << T >>  << A >>
usrdr@yahoo.co.uk (serdar) wrote in message news:<d983e0c.0308080239.68f20297@posting.google.com>...
> Hi,
> I am new CPLD and FPGA. Should I start Xilinx devices or ALTERA
> 
You might find it interesting to look at the tutorials at
http://tutor.al-williams.com. These cover the basics of Xilinx and
Altera using CPLDs. It is overwhelming getting started, but working
through the tutorial will help you get a feel for things. Keep in 
mind that you can do software simulation and get your feet wet 
without actually investing in any hardware at first.

Regards,

Al Williams
AWC
http://www.al-williams.com/awce

Article: 59129
Subject: Re: speeding up quartus
From: "Paul Leventis" <paul.leventis@utoronto.ca>
Date: Sat, 09 Aug 2003 01:21:15 GMT
Links: << >>  << T >>  << A >>
Hi Don,

I have a few questions:

(a) Why is the user iterating through full P&R so much?  Is it for timing
closure?  Or are they doing post-P&R simulation when they could be using
pre-P&R simulation for the purposes of debugging their HDL?
(b) What device is being used, and how full is it?  1 hr is not unreasonable
for a medium-sized design, and your observation that Quartus is CPU bound
confirms that the user is not running out of memory for some reason.

There is an option in Quartus known as "Fast Fit" which will make the fitter
run faster at the expense of a small amount of performance.  I'd also
suggest upgrading to the latest version of Quartus II (version 3.0) as I
*think* there has been a bit of a speed up for newer families over the past
few releases, though I don't have the data handy to confirm this.  If the
user is iterating to achieve timing closure, a newer version of Quartus
could do the trick as we are constantly improve the quality of push-button
place and route.

I'm not terribly familiar with the CPU time implications of using logic lock
or incremental compile and will ask a colleague about this on Monday.

Regards,

Paul Leventis
Altera Corp.



"Don S" <dshesnicky@yahoo.com> wrote in message
news:b9ff9982.0308081117.164f3b3a@posting.google.com...
> I'm a sysadmin looking at a problem that a designer is having with
> slow turn around times in Altera Quartus. The turn around time on a
> compile is about 1 hr on a AMD 1700+ with 1 gig of memory. Quartus
> version is 2.1 running on Win2K SP2.
>
> The bulk of the time is spent in Logic Synthesis and the Fitter.
> If we just bring up the task manager it shows that we have not tapped
> the memory but the cpu is pegged.
>
> There is apparently a way to lock down the layout of certain blocks
> and/or do an incremental compile so that everything would not have to
> be re-synthesised but the designer says that it doesn't seem to work
> correctly.
>
> Any pointers would be greatly appreciated.
>
> Don



Article: 59130
Subject: Xilinx Webpack ISE and Verilog-2001?
From: "dont_reply" <anon@anon.com>
Date: Sat, 09 Aug 2003 02:35:39 GMT
Links: << >>  << T >>  << A >>
Does Xilinx Webpack ISE support RTL-synthesis of Verilog-2001?  If so, what
was the first version to support it?  I'm mainly looking at support for
'signed' number support.
(Signed regs, wires, inputs/outputs, and '>>>')



Article: 59131
Subject: Re: Xilinx Webpack ISE and Verilog-2001?
From: "Paul Leventis" <paul.leventis@utoronto.ca>
Date: Sat, 09 Aug 2003 02:55:20 GMT
Links: << >>  << T >>  << A >>
> Does Xilinx Webpack ISE support RTL-synthesis of Verilog-2001?  If so,
what
> was the first version to support it?  I'm mainly looking at support for
> 'signed' number support.
> (Signed regs, wires, inputs/outputs, and '>>>')

Can't answer you on ISE support -- but if you are looking for a freely
available Verilog-2001 compiler, the Quartus II 3.0 Web Edition should do
the trick.  You can select Verilog-1995 or Verilog-2001 support via the
Settings dialog box in the Assignments menu.  Almost all language features
are supported, including signed declarations and the >>> operator.  Please
see http://www.altera.com/support/kdb/rd05132003_6968.html or application
note AN238 for more information.

Regards,

Paul Leventis
Altera Corp.



Article: 59132
Subject: from Altera to Xilinx
From: "Ronny Hengst" <ballu_baer@gmx.de>
Date: Sat, 9 Aug 2003 10:16:34 +0200
Links: << >>  << T >>  << A >>
Hello.

I have to implement a Design from an Altera Max7000S (EPM7128SL84-15) to any
Xilinx-Board. Which board you can recommend for this task and why? Are there
any problems I have to watch out?

Regards, Ronny



Article: 59133
Subject: DDR-ram interface (xapp200)
From: "Michael Chan" <s354025@student.uq.edu.au>
Date: Sat, 9 Aug 2003 23:24:09 +1000
Links: << >>  << T >>  << A >>
Hi,

I'm working on a University project that requires ddr-ram interfaced to a
Vertex-EM device.  I am basing my design off xapp200 from xilinx.  The
design uses DLLs to deskew the system clock and ddr-ram clock.  The signal
fed back to the DLLs (sys_clk_fb) is apparently the ddr clk.  What I don't
understand is where I take this signal from.  Should I have tracks on my PCB
comming back from the ddr-ram chips to inputs on the fpga?  Or can the
feedback signal come from inside the fpga?

I am a little lost as to how the DLLs manage to sychronise the two clocks.
Any help would be appreciated.

Thanks.

Michael.



Article: 59134
Subject: Re: DDR-ram interface (xapp200)
From: "Bob" <nimby1_not_spmmm@earthlink.net>
Date: Sat, 09 Aug 2003 16:21:49 GMT
Links: << >>  << T >>  << A >>
Michael,

There are two basic ways that DLL's are used to de-skew clocks. For lack of
any other names, they are:

1) internal de-skew
2) external de-skew

Internal de-skew means that the global clock net, within the FPGA,
transitions at the same time (phase) that the FPGA's input clock
transitions.

External de-skew means that a clock at an FPGA output pin transitions at the
same time (phase) that the FPGA's input clock transitions.

Here are some terms you should know:

IBUF/OBUF -- an FPGA input/output pin (what most of the FPGA pins are).
IBUFG -- really just a standard I/O pin, but physically close to the DLL --
such that the DLL knows what its routing delay is to it. These are where
clock inputs (and external clock feedback signals) are supposed to connect
to.
DLL -- the phase detector, etc...
BUFG -- a global clock buffer. The output of the BUFG's are the global clock
nets.

With internal de-skew, the output of the BUFG (global clock net) is fed
directly back to the DLL's clock feedback input -- with the FPGA itself.
With external de-skew, the output of the BUFG feeds an OBUF (output pin).
Then, a trace on your circuit board connects that OBUF to an IBUFG.

With a synchronous RAM design (like your DDR project), the idea is to first
get a clock to the RAM that has the same phase as one of the FPGA's internal
global clock nets. This is so that the timing of the RAM read data, at the
FPGA IBUF's, has a known time relationship. One of the DLL's in the design
is used to do this -- via external de-skew.

The other DLL is used (via internal de-skew) to create the "read RAM data"
clock.

I haven't looked at XAPP200 carefully, but here's how we do our DDR
controllers:

1) Use external de-skew to create the RAM's CLK/CLKB, and DQS clocks. Note
that the DQS clocks (strobes) are tristated during RAM reads, and are not
used during RAM reads. Additionally, this DLL's 90deg output is used to feed
the OBUF's that create the RAM DQ lines -- but only for RAM writes.

2) Use internal de-skew to create a separate clock net for RAM reads (and
other FPGA functions).

Having said all this, I must say that it's amazing to me that a Virtex-E
device can be used for this type of application. I say this because the data
from the RAM is valid during the time "between" the RAM's DQS clock (strobe)
edges. So, when the RAM read data gets back to the FPGA pins, its valid data
position is not ideal (i.e., suitable setup and hold time). It is much
easier to use a Virtex-II device, wherein a third internal de-skew clock net
can be generated (which has phase shift via the DCM) in order to properly
capture the RAM read data.

Either way, you'll learn a lot with this project.

Regards,
Bob


"Michael Chan" <s354025@student.uq.edu.au> wrote in message
news:bh2scl$kop$1@bunyip.cc.uq.edu.au...
> Hi,
>
> I'm working on a University project that requires ddr-ram interfaced to a
> Vertex-EM device.  I am basing my design off xapp200 from xilinx.  The
> design uses DLLs to deskew the system clock and ddr-ram clock.  The signal
> fed back to the DLLs (sys_clk_fb) is apparently the ddr clk.  What I don't
> understand is where I take this signal from.  Should I have tracks on my
PCB
> comming back from the ddr-ram chips to inputs on the fpga?  Or can the
> feedback signal come from inside the fpga?
>
> I am a little lost as to how the DLLs manage to sychronise the two clocks.
> Any help would be appreciated.
>
> Thanks.
>
> Michael.
>
>



Article: 59135
Subject: Re: Virtex-II RocketIO: Serial ATA?
From: David Rogoff <david@therogoffs.com>
Date: Sat, 09 Aug 2003 11:08:40 -0700
Links: << >>  << T >>  << A >>
Andrew Paule <lsboogy@qwest.net> writes:

> Paul Gentieu wrote:
>
>> The Xilinx web page describing the RocketIO serdes mentions in
>> passing that it can support Serial ATA. But I don't see any support
>> for out-of-band signaling, and the serdes voltage swing and
>> common-mode levels don't seem compatible either.
>>
>> So, it seems that significant external circuitry would be required,
>> and it would be kludgy. Is there an appnote for doing this?
>> Dedicated SATA Phy chips seem pretty hard to find.
>>
>> Of course, a real SATA-compatible transceiver in the next generation
>> of the FPGA would be preferable...
>>
>> -Paul
>>
> This might be a place to go to an ON NBSG16VS part, and do the power
> rails to get the vcm into spec, unless you want to AC couple.  They
> can be set from 100mV to 800 mV (you want about 500 if I remember
> correctly), but don't get the BGA - they are dropping BGA's like crazy
> (too much lead inductance, you'll make rise time spec, but not by much
> unless you're very careful) - the QFN's can go to 35ps.
>
> Andrew
>

Andrew,

I just looked at the data sheet on Onsemi's web site.  How does this
part help with OOB?  It's just a Differential Receiver/Driver: there's
no enable or CM detection.  It would only help with levels, which
isn't as much of an issue.  I don't think you understood the question,
or maybe you meant a different Onsemi part.

Anyway, Paul, please beat up your Xilinx rep!  I'm annoyed about this
too.  They prominently say that the RocketIO can be used for SATA
applications, but it doesn't support OOB, which is absolutely
required.  Maybe if enough people bug them they will do something about it!

 David

Article: 59136
Subject: Re: Offshore engineering
From: "an" <dont_reply@nowhere.net>
Date: Sat, 09 Aug 2003 18:44:06 GMT
Links: << >>  << T >>  << A >>
> I've been debating for several days whether or not to post this message.
> Well...here it goes, we'll see what develops.
>
> I read a disturbing article this last week in Time magazine.  It seems to
be
> available online at
> http://www.time.com/time/magazine/article/0,9171,1101030804-471198,00.html
.
> This article describes the alarming rate at which many types of jobs are
> being exported to countries such as India, where the work gets done for
darn
> near 1/10th. the cost, or less.
>
> Now, before anybody beats me over the head with a digital club, please
know
> that my intention here is to understand the trend and what it might mean
in
> general.  As a small business owner facing the need to hire engineers
> (FPGA/embedded) within the next six to twelve months I have to ask myself
if
> my competitors have exported these jobs?  If that were to be the case,
> competitive forces alone would almost dictate that I (and others in my
> position) look for offshore solutions.

From people I've spoken to down here in Southern California, most
of the 'famous' high-tech companies (Broadcom, Connexant, etc.) have
already begun investigating outsourcing engineering/design work.  My
contact at Connexant says some departments there already outsource some
portion of back-end (place/route) designwork to Indian firms.  Broadcom
is likely to follow soon (if they haven't started already.)

At this point, the engineering-design capabilities of these outsourcing
companies are 'fairly basic.'  As the practice is in its infancy, the
work-quality is decidedly mixed, varying from company to company and project
to project.  Projects which require ongoing input from the (US-based)
spec-writers often run into complications, due to communication errors or
other logistic problems.  (Sitting down face to face still beats out
email/video-conferencing any day!)  I suspect that as time goes on,
project managers will become more familiar with the process of outsourcing,
and adapt to the logistic issues.

Likewise, as the outsourcing companies compete against one another, the
better performers will garner repeat work, increase their design capacity
and sophistication.



Article: 59137
Subject: Re: Virtex-II RocketIO: Serial ATA?
From: Andrew Paule <lsboogy@qwest.net>
Date: Sat, 09 Aug 2003 13:49:32 -0500
Links: << >>  << T >>  << A >>
The on semi part just gets you into the voltage swing - the oob and 
cmdet functions are going to have to be handled externally also - I used 
to work for a company that did these things (Wavecrest) and notice that 
now mindspeed is dumping their parts (last time buys).  The serial ATA 
functions are not going to be well supported by Xilinx - I think that 
they are trying to get these things tested right now, and being a 
digital company, I think that they have some marketing people who assume 
that they can handle this stuff.   Obviously, any mention of SATA with 
these chips has not been well thought out (1.0 ATA spec requires OOB).  
Mindspeed is dumping this stuff, and I think I'd be looking LSI ways for 
a while for anything custom.  The jitter spec along is going to force 
these things away from compliance - me thinks you get about a third of a 
UI at 1.2G for TJ - and the DCM in the part already gives about 100ps - 
great for CMOS, but until you get a good CDR module, and proper I/O 
buffers, we're playing with external components anyway. 

I'd see if Peter Alfke (he is Xilinx, but I've found him to be 
knowledgable and honest) knows of any hints, but I think that serial ATA 
is still best done SiGe with externals.  Mindspeed is having some sort 
of real fun - the telecom market is not giving them the business that 
they need to keep some parts alive (they are the cores that Xilinx is 
using), and should be a good source - they make GREAT stuff, but they 
are dumping this stuff

Side note for Peter - how can you BERT two of these if your clock is 
only at 100ps RJ? Tektronix and wavecrest are both capable of doing 
this, but their clocks are under 1ps jitter.   You need a thermally 
stabilized source to do this in my goofy opinion.

Andrew

David Rogoff wrote:

>Andrew Paule <lsboogy@qwest.net> writes:
>
>  
>
>>Paul Gentieu wrote:
>>
>>    
>>
>>>The Xilinx web page describing the RocketIO serdes mentions in
>>>passing that it can support Serial ATA. But I don't see any support
>>>for out-of-band signaling, and the serdes voltage swing and
>>>common-mode levels don't seem compatible either.
>>>
>>>So, it seems that significant external circuitry would be required,
>>>and it would be kludgy. Is there an appnote for doing this?
>>>Dedicated SATA Phy chips seem pretty hard to find.
>>>
>>>Of course, a real SATA-compatible transceiver in the next generation
>>>of the FPGA would be preferable...
>>>
>>>-Paul
>>>
>>>      
>>>
>>This might be a place to go to an ON NBSG16VS part, and do the power
>>rails to get the vcm into spec, unless you want to AC couple.  They
>>can be set from 100mV to 800 mV (you want about 500 if I remember
>>correctly), but don't get the BGA - they are dropping BGA's like crazy
>>(too much lead inductance, you'll make rise time spec, but not by much
>>unless you're very careful) - the QFN's can go to 35ps.
>>
>>Andrew
>>
>>    
>>
>
>Andrew,
>
>I just looked at the data sheet on Onsemi's web site.  How does this
>part help with OOB?  It's just a Differential Receiver/Driver: there's
>no enable or CM detection.  It would only help with levels, which
>isn't as much of an issue.  I don't think you understood the question,
>or maybe you meant a different Onsemi part.
>
>Anyway, Paul, please beat up your Xilinx rep!  I'm annoyed about this
>too.  They prominently say that the RocketIO can be used for SATA
>applications, but it doesn't support OOB, which is absolutely
>required.  Maybe if enough people bug them they will do something about it!
>
> David
>  
>


Article: 59138
Subject: Re: I am new and I want to help
From: "Jean Nicolle" <j.nicolle@sbcglobal.net>
Date: Sat, 09 Aug 2003 23:02:25 GMT
Links: << >>  << T >>  << A >>
you can also check http://www.fpga4fun.com/

"serdar" <usrdr@yahoo.co.uk> wrote in message
news:d983e0c.0308080239.68f20297@posting.google.com...
> Hi,
> I am new CPLD and FPGA. Should I start Xilinx devices or ALTERA
> devices? and verilog or VHDL?
> I think buy a CPLD starter board.(CoolRunner II Design Kit or MAX 7000
> Quick Start Development Kit) Can you recommended any board for
> starting?



Article: 59139
Subject: Re: from Altera to Xilinx
From: "Simon Peacock" <nowhere@to.be.found>
Date: Sun, 10 Aug 2003 13:53:07 +1200
Links: << >>  << T >>  << A >>
check the coolrunner family, you might find a pin compatible version.  :-)
I actually found a pin for pin (but it had 2 less IO) version which is
cheaper.. the max is cheaper than the coolrunner that is by a factor of
about 3.
Failing that there's the 9500 series which I bet is cheaper than the
coolrunner.


Simon

"Ronny Hengst" <ballu_baer@gmx.de> wrote in message
news:bh2afi$tgbr9$1@ID-163925.news.uni-berlin.de...
> Hello.
>
> I have to implement a Design from an Altera Max7000S (EPM7128SL84-15) to
any
> Xilinx-Board. Which board you can recommend for this task and why? Are
there
> any problems I have to watch out?
>
> Regards, Ronny
>
>



Article: 59140
Subject: Xilinx virtex II DCM CLKFX output not working
From: "Charles Stuart" <cstuart@cfl.rr.com>
Date: Sun, 10 Aug 2003 02:18:23 GMT
Links: << >>  << T >>  << A >>
I've looked through the Xilinx site and found some reference to the problem
I'm having and tried the suggestions, but to no avail. I am using the DFS
function on a DCM, but I get no output from the CLKFX output....... yes I
have also defined the CLKIN_PERIOD. Has anyone seen this  problem ?

Thanks in advance
 Charlie



Article: 59141
Subject: Re: Xilinx virtex II DCM CLKFX output not working
From: "Bob" <nimby1_not_spmmm@earthlink.net>
Date: Sun, 10 Aug 2003 03:55:54 GMT
Links: << >>  << T >>  << A >>
Is the DCM locked?

Bob


"Charles Stuart" <cstuart@cfl.rr.com> wrote in message
news:PXhZa.26947$K4.1430387@twister.tampabay.rr.com...
> I've looked through the Xilinx site and found some reference to the
problem
> I'm having and tried the suggestions, but to no avail. I am using the DFS
> function on a DCM, but I get no output from the CLKFX output....... yes I
> have also defined the CLKIN_PERIOD. Has anyone seen this  problem ?
>
> Thanks in advance
>  Charlie
>
>



Article: 59142
Subject: Re: Virtex-II RocketIO: Serial ATA?
From: Andrew Paule <lsboogy@qwest.net>
Date: Sun, 10 Aug 2003 00:06:37 -0500
Links: << >>  << T >>  << A >>
I spent a little (emphasis on little) bit of time, and Xilinx does not 
say in any of the lit that I can find that they actually support serial 
ATA.  I think that this is one standard that you will have to get 
elsewhere.  Ever look at XAUI/XIBI stuff, much better alternative.

Andrew

Paul Gentieu wrote:

> The Xilinx web page describing the RocketIO serdes mentions in passing 
> that it can support Serial ATA. But I don't see any support for 
> out-of-band signaling, and the serdes voltage swing and common-mode 
> levels don't seem compatible either.
>
> So, it seems that significant external circuitry would be required, 
> and it would be kludgy. Is there an appnote for doing this? Dedicated 
> SATA Phy chips seem pretty hard to find.
>
> Of course, a real SATA-compatible transceiver in the next generation 
> of the FPGA would be preferable...
>
> -Paul
>


Article: 59143
Subject: Re: Xilinx virtex II DCM CLKFX output not working
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Sun, 10 Aug 2003 06:54:47 GMT
Links: << >>  << T >>  << A >>
You have to monitor the "LOCKED" output and reset the DCM if lock is not
achieved.  My reset sequencing module takes this into account and holds the
rest of the FPGA in reset until all DCM's are up and running.  It resets the
DCM's, waits for a period of time and then samples for a lock condition.  If
no lock was achieved the sequence repeats (reset, look for lock).


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"





"Charles Stuart" <cstuart@cfl.rr.com> wrote in message
news:PXhZa.26947$K4.1430387@twister.tampabay.rr.com...
> I've looked through the Xilinx site and found some reference to the
problem
> I'm having and tried the suggestions, but to no avail. I am using the DFS
> function on a DCM, but I get no output from the CLKFX output....... yes I
> have also defined the CLKIN_PERIOD. Has anyone seen this  problem ?
>
> Thanks in advance
>  Charlie
>
>



Article: 59144
Subject: FPGA for a Newcomer
From: "John Bowen" <johnboy@cafes.net>
Date: Sun, 10 Aug 2003 08:11:21 -0500
Links: << >>  << T >>  << A >>
 I've had several courses on Digital Logic, ......but that was in the early
1980s !!  I was very familiar with the 7400 series of integrated circuits,
and could name the gates and truth tables off the top of my head. A lot of
years have passed since I worked with these chips, and I've fallen way
behind in technology. But now I'd like to do some experimenting on my own.
  I wanted to build something like a simple Annunciator Panel type project,
so I dug out my old logic books to brush up. What I found out was that I
needed about 50-75 Logic Gates for my particular design, though I'm sure I
could pare that down some, but  the thought of mounting and wiring (I used
to wire-wrap a lot) about 25 or more Integrated Circuits just kind of
discouraged me. I was asking a fellow Technician about maybe using some sort
of EEProm, and he told me about Field Programmable Gate Arrays...according
to what I've since learned, it looks like I should be able to program a FPGA
with my logic design(or reprogram it if I make a mistake)....my logic would
be a series of And, Nor, etc. gates, Flip Flops, etc, and use contact
closures for inputs and LEDs for outputs. Am I correct in my interpretation
of what a FPGA is, and how it operates?
   I was looking at 10 inputs (contact closures) and 10 simple LEDs for the
outputs on this first project. Since I'm not familiar with the pin
assignments for the I/Os, and what's needed to program these FPGAs, would
any of you have a recommendation on what family and size of FPGA I should
start with? Or is an FPGA really what I need? What about a programmer (or
programming method) and software? I'd be most comfortable using a software
that graphically displays my gates and their connections if there is such a
thing, but since this is just going to be a playtoy for now, I guess cost
needs to be a consideration, so inexpensive developmental would be best. Is
there a Complete Experimenter's Kit available for someone with my interests?
Or would I be better off buying individual components to suit my needs?
  I've read some of the posts, and it sounds like you guys are WAAAY up on
the curve....can you help me get started?
Thanks, John.



Article: 59145
Subject: Re: I am new and I want to help
From: Rob Judd <judd@ob-wan.com>
Date: Sun, 10 Aug 2003 23:15:34 +1000
Links: << >>  << T >>  << A >>
Al Williams wrote:
> 
> usrdr@yahoo.co.uk (serdar) wrote in message news:<d983e0c.0308080239.68f20297@posting.google.com>...
> > Hi,
> > I am new CPLD and FPGA. Should I start Xilinx devices or ALTERA
> >
> You might find it interesting to look at the tutorials at
> http://tutor.al-williams.com. These cover the basics of Xilinx and
> Altera using CPLDs. It is overwhelming getting started, but working
> through the tutorial will help you get a feel for things. Keep in
> mind that you can do software simulation and get your feet wet
> without actually investing in any hardware at first.

Al,

That looks like a valuable resource. Thanks for the effort of writing it
all up.

Rob

Article: 59146
Subject: Re: Offshore engineering
From: "Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it>
Date: Sun, 10 Aug 2003 13:28:54 GMT
Links: << >>  << T >>  << A >>
"Martin Euredjian" <0_0_0_0_@pacbell.net> ha scritto nel messaggio
news:ChpYa.49$6x2.6678595@newssvr14.news.prodigy.com...

> Where is this going?  I'm all for globalization and
> economic prosperity at
> every point on the globe

If you really are for economic prosperity everywhere, you must accept
the fact that when the cake needs to be split in more parts, the slices
are smaller. So those who ate almost all of the cake in the past, now
will have less to eat.

-- 
Lorenzo



Article: 59147
Subject: Re: speeding up quartus
From: "Paul Baxter" <pauljnospambaxter@hotnospammail.com>
Date: Sun, 10 Aug 2003 15:14:17 +0100
Links: << >>  << T >>  << A >>
Off the subject but I have been really glad to see Altera's presence in this
forum for the last few months.

For years it seemed that only Xilinx cared about their user community on
here so its nice to see the support. Kudos to Paul, Subroto et al. (and
continuing thanks to Austin, Peter et al from Xilinx)

Mike hit the nail on the head, most work should be done pre-synthesis. Of
course the Altera product (or Xilinx) doesn't really lend itself to doing
this by itself. I'd recommend Active HDL (www.aldec.com) though others swear
by ModelSim

You 'really' need a decent simulator to speed the overall design process.

Paul

"Paul Leventis" <paul.leventis@utoronto.ca> wrote in message
news:f0YYa.127991$hOa.39807@news02.bloor.is.net.cable.rogers.com...
> Hi Don,
>
> I have a few questions:
>
> (a) Why is the user iterating through full P&R so much?  Is it for timing
> closure?  Or are they doing post-P&R simulation when they could be using
> pre-P&R simulation for the purposes of debugging their HDL?
> (b) What device is being used, and how full is it?  1 hr is not
unreasonable
> for a medium-sized design, and your observation that Quartus is CPU bound
> confirms that the user is not running out of memory for some reason.
>
> There is an option in Quartus known as "Fast Fit" which will make the
fitter
> run faster at the expense of a small amount of performance.  I'd also
> suggest upgrading to the latest version of Quartus II (version 3.0) as I
> *think* there has been a bit of a speed up for newer families over the
past
> few releases, though I don't have the data handy to confirm this.  If the
> user is iterating to achieve timing closure, a newer version of Quartus
> could do the trick as we are constantly improve the quality of push-button
> place and route.
>
> I'm not terribly familiar with the CPU time implications of using logic
lock
> or incremental compile and will ask a colleague about this on Monday.
>
> Regards,
>
> Paul Leventis
> Altera Corp.
>
>
>
> "Don S" <dshesnicky@yahoo.com> wrote in message
> news:b9ff9982.0308081117.164f3b3a@posting.google.com...
> > I'm a sysadmin looking at a problem that a designer is having with
> > slow turn around times in Altera Quartus. The turn around time on a
> > compile is about 1 hr on a AMD 1700+ with 1 gig of memory. Quartus
> > version is 2.1 running on Win2K SP2.
> >
> > The bulk of the time is spent in Logic Synthesis and the Fitter.
> > If we just bring up the task manager it shows that we have not tapped
> > the memory but the cpu is pegged.
> >
> > There is apparently a way to lock down the layout of certain blocks
> > and/or do an incremental compile so that everything would not have to
> > be re-synthesised but the designer says that it doesn't seem to work
> > correctly.
> >
> > Any pointers would be greatly appreciated.
> >
> > Don
>
>



Article: 59148
Subject: Re: FPGA for a Newcomer
From: Phil Hays <SpamPostmaster@attbi.com>
Date: Sun, 10 Aug 2003 14:34:55 GMT
Links: << >>  << T >>  << A >>
John Bowen wrote:

> ... Am I correct in my interpretation of what a FPGA is, and 
> how it operates?

Yes.

> ... a recommendation on what family and size of FPGA I should
> start with? Or is an FPGA really what I need?

A very similar product called a CPLD is probably closer to your needs. 
CPLDs are smaller, simpler and cheaper.  As you don't need the number of
gates even the smallest FPGA has (~10,000) you probably want to look at
CPLDs first.


> What about a programmer (or programming method) and software? 

Programmer is a cable between a parallel port on a PC and software can
be various free packages from the CPLD vendor.  I'd suggest looking at
Altera's MAX and Xilinx's Coolrunner and 9500 stuff.  Software is at:

http://www.altera.com/products/software/free/fre-emax_baseline.html
http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack

Yes, these are just the biggest two vendors.  See the vendor list at:

http://www.optimagic.com/


> I'd be most comfortable using a software
> that graphically displays my gates and their connections if there is such a
> thing, but since this is just going to be a playtoy for now, I guess cost
> needs to be a consideration, so inexpensive developmental would be best.

Schematic entry packages are included with free software packages from
Altera and Xilinx.


> Is
> there a Complete Experimenter's Kit available for someone with my interests?

Two choices:

http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=design_kit
http://www.altera.com/products/devkits/kit-dev_platforms.jsp


> Or would I be better off buying individual components to suit my needs?

Perhaps.  Planning on making more than one?  Then perhaps making a
circuit board and buying the parts would be a good idea.


-- 
Phil Hays

Article: 59149
Subject: a quick searching problem
From: zhenxu2000@hotmail.com (Zhen)
Date: 10 Aug 2003 08:14:14 -0700
Links: << >>  << T >>  << A >>
There are two vectors, named V1 and V2, the sizes of which are 1*M and
1*N, respectively. We have known that there is at most one common
element in both vectors. I am looking for the quick algorithm to
search this common element.

The general algorithm is to compare every element in V1 with each
element in V2. the comparison complexity will be O(M*N). Is there any
efficient method to complete it?
I hope it can be done in FPGA. If M=N=60, and each element is 20 bit
long,there isn't enough pins for the general search algorithms at one
time. It need some loops to do it. So I am looking for an efficient
algorithm and expect that the common element can be found in around
10ns~50ns. Is it possible?
Thanks,



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search