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Messages from 59300

Article: 59300
Subject: Re: Old Xilinx FPGAs
From: antti@case2000.com (Antti Lukats)
Date: 14 Aug 2003 03:35:24 -0700
Links: << >>  << T >>  << A >>
Jeff Sampson <jsampson@pobox.com> wrote in message news:<3F3AEA81.6020104@pobox.com>...
> [Please pardon an intrusion from a really casual FPGA/CPLD user]
> 
> I have a collection of old Xilinx parts. XC2018, XC3020, XC3030, XC3064, 
> XC4004A. I gave up years ago trying to find software for the XC2018 parts. 
[]
>Or should I just throw these old parts away and get some Spartan/Virtex parts?

second that: I also have some XC2018 (50+) XC3020,XC3090, etc... parts
but I am just about throwing them away.
I had XACT 3.20 on 5 Inch floppy disks, but not sure if it survived the
process of upgrades :)
paper cards -> 
paper tape -> 
consumer tape recorder -> 
8inch floppy ->
5inch floppy ->   [old XACT was here! ]
floppy (as we know) + my first HD (10MB, double height)
...

as of what to use - if you are not in a real hurry - wait up for Spartan III,
and forget drop trash all below it.

antti

Article: 59301
Subject: Problem with Modelsim Lisence server...
From: deb_astro@yahoo.co.in (Debashish)
Date: 14 Aug 2003 06:41:39 -0700
Links: << >>  << T >>  << A >>
Hi guys,
Here i have a problem with my Modelsim lisence server.I have 2
lisences for modelsim in my office. But many a times if someone dont
close the modelsim properly or dont release the lisence (by command
quit -sim), lisence stays active even if he is not working.So most of
the time i am not able to use 2 linces. So being a Windows 2000 server
we had to restart it again and agian atleast once everyday, two kill
those process and regain the 2 lisences.

 Is there any way or any script that can help me to do this without
restarting the lisence server. I know its easier to handle in Linux or
Unix severs, by just killing the process. But how will i do the same
without restarting the windows 2000 server. Is there any java or any
other script for that.

Regards..
Debashish Hota

Article: 59302
Subject: Modelsim : Error code 3601
From: Abhinav <ag01@ieee.org>
Date: Thu, 14 Aug 2003 06:58:07 -0700
Links: << >>  << T >>  << A >>
Hello all, 

Whenver I try to simulate my design. I get this error: 
Error: (vsim-3601) Iteration limit reached at time 390 ns. I did a 
verror 3601 on it. All it says it to increase the IterationLimit. 
But that doesn't help either.  

Bascially my design has a queue 
size which is being used to calculate an average and that average 
is then compared to a constant value. The design works fine as 
long as the queue size is small. But as that size increases 
from 20 onwards. I get that 3601 error. 

Any help will be highly appreciated.

Article: 59303
Subject: Re: Modelsim : Error code 3601
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Thu, 14 Aug 2003 15:46:17 +0100
Links: << >>  << T >>  << A >>
"Abhinav" <ag01@ieee.org> wrote in message
news:ee7f377.-1@WebX.sUN8CHnE...
> Hello all,
> Whenver I try to simulate my design. I get this error:
>  Error: (vsim-3601) Iteration limit reached at time 390 ns.
> I did a verror 3601 on it. All it says it to increase the
> IterationLimit. But that doesn't help either.
> Bascially my design has a queue size which is being used to
> calculate an average and that average is then compared to a
> constant value. The design works fine as long as the queue
> size is small. But as that size increases from 20 onwards.
> I get that 3601 error. Any help will be highly appreciated.

Abhinav,

please post in plain-text rather than RTF!

This problem arises when you have many signals updating
and then causing other processes to run, all with no time delay.
It almost always represents a major error in your conversion
of the problem into VHDL or Verilog (Note: a poster called
"Isaac" recently posted two messages about the same problem
on comp.lang.vhdl).

There are many ways to write code that suffers this problem,
but the most common way is probably to write large amounts
of logic using many concurrent assignments.  If you do this,
it's easy to design logic that has combinational feedback
loops.  If such a zero-delay feedback loop converges to
a steady state, you will appear to get sensible results.
But if the loop starts to oscillate, you get a zero-period
oscillator which will quickly consume the maximum number
of simulation cycles without allowing time to progress.

In a rather large simulation, it is possible that the iteration
limit needs to be increased.  But it is still most likely that
it's a coding problem.  Without seeing your code it is
impossible to give any specific advice.
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 59304
Subject: Re: Skew on a clock tree on a virtex II : what is the good figure ?
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Thu, 14 Aug 2003 08:12:29 -0700
Links: << >>  << T >>  << A >>
JF,

Skew can always be a problem, if you do not take it into account.  Since the software does take
internal skew into account automatically, with the timing constraints properly set, internal paths
of the design should have no problems with setup, or hold timing.

External wide IO busses need to be thought out, as the software doesn't understand constraining a
wide IO buss to less than X skew (nice feature, though).

As the die gets larger, there isn't much you can do, as the speed of light in silicon (propagation
of signals in the wires), combined with the RC delays, combine to make the longest lines have the
delays mentioned.

The speed of the chip has almost nothing to do with this (ie the fastest clock rate the global
clock tree will toggle at).  But it is true that the faster the speed grade, the smaller the skew
will be.  But the skew is dominated more by the silicon light speed (speed of the signal in
silicon) and by the metal line RC, which is a small component of the speed grade.

Austin

jean-francois hasson wrote:

> Hi,
>
> Considering your answer does it imply that the chip (xc2v6000-5) is
> not fast enough for a 450 ps skew on the clock to be a problem ?
>
> J.F. Hasson
>
> Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F3AAE78.AF5F5717@xilinx.com>...
> > J.F.,
> >
> > The report by the tools is correct.
> >
> > Different sized parts will have different skews (delays) in the their clock
> > trees due to size.
> >
> > Additionally, skew is a function of position on the tree, so from the top left
> > corner down to the middle of a part all the way to the bottom left corner, the
> > skew will be less than 130 ps for a 2V6000, wheras from the top left corner over
> > towards the top middle over to the right corner, it will be about 450 ps for a
> > 2V6000.
> >
> > Top to bottom: 130 ps.  Right to left: 450 ps.  Smallest in the middles, largest
> > at the corners.
> >
> > For a 2V1000, these are all less than 100 ps.
> >
> > Thus if you wanted to make the highest speed wide parallel interface, I would
> > use the left or right sides (least skew), rather than the top or bottom edges
> > (for least skew between bits).
> >
> > If I had to use the top or bottom edges, I would try to group the IOs near the
> > center, or near the left and right extremes.
> >
> > Again the timing reports and FPGA_Editor report the right (worst case) numbers.
> >
> > Hope this helps,
> >
> > Austin
> >
> > jean-francois hasson wrote:
> >
> > > Hi,
> > >
> > > I am working on a design involving a virtex II -5. I read in a previous post
> > > that the skew one could expect from a clock tree is less than 100 ps.
> > > However when, on the design I am developping, I run the timing analyzer I
> > > get a skew for some clock on a clock tree of about 450 ps or 500 ps (using
> > > the 5.1i F23). How should I interpret this difference ? Any clue ? Which
> > > figure is the right one ?
> > >
> > > J.F. Hasson


Article: 59305
Subject: Re: Old Xilinx FPGAs
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Thu, 14 Aug 2003 08:25:59 -0700
Links: << >>  << T >>  << A >>
Jeff,

For these ancient devices (see Peter's threads regarding the aging rate of FPGAs),
there are archived versions of software, but it also takes a computer system that is
compatible (ie DOS, Windows 3.0, etc).

By submitting a hotline case online, you will be able to get a response for what
devices are upward (or downward) bitstream compatible (not all are).

The early software also used the early hardware keys (dongles), so that is also
something that is needed....(if anyone offers you some old software -- get the old key
too!).

Not something that would interest me in spending time on, as you could probably pick up
surplus grey market models of much more recent devices that are supported by the free
Webpack software.

But, if you are nostalgic.....I hear that folks have FPGA versions of PDP-8
computers....and cross compilers for IBM 1130's that run on PC's.....strange
hobbies....but some folks collect stamps, so I suppose I can't really understand any of
it.

Austin

Jeff Sampson wrote:

> [Please pardon an intrusion from a really casual FPGA/CPLD user]
>
> I have a collection of old Xilinx parts. XC2018, XC3020, XC3030, XC3064,
> XC4004A. I gave up years ago trying to find software for the XC2018 parts. But I
> assumed my software would do the XC30xx and XC40xx when I got around to using
> them. Now I notice that the Xilinx web page doesn't have spec sheets for the
> base XC30xx and XC40xx or XC40xxA parts. I also notice that me oldest software,
> Foundation Base 1.4 is too new to include these parts. (after casual browsing
> through Foundation Base 1.4, WebPack 4.2, WebPack 5.1i, Student 2.1i)
>
> So, my question is, am I missing someting? Or do I just need older software?
>
> Can I use XC3030A to create code for a XC3030? I'm guessing that I can't.
>
> What about the XC4004A? Can I use XC4003E or XC4003XL to create code for the
> XC4004A? I'm guessing not.
>
> If I need older software, does anyone have any old software they want to part with?
>
> I'm guessing old software falls into 3 catagories:
>
>    1. Better keep it in case we have to update this old stuff.
>    2. It is still here on the shelf because I couldn't bear to throw it away.
>    3. Threw it away years ago.
>
> Or should I just throw these old parts away and get some Spartan ot Virtex parts?
>
> --
> Jeff Sampson
> http://tcrobots.org/members/jsamp.htm


Article: 59306
Subject: Virtex II Output Impedance
From: "Jeremy Whatley" <jeremyw@erlangtech.com>
Date: Thu, 14 Aug 2003 11:08:04 -0500
Links: << >>  << T >>  << A >>
Can anyone tell me what kind of output impedance I should expect to see from
a Xilinx Virtex II XC2V1000-FF896 FPGA?  The Digitally Controlled Impedance
feature was not used for this design.  The signals in question are LVTTL
12mA fast slew rate (I think that's default).

Thanks!

Jeremy Whatley
jeremyw@erlangtech.com



Article: 59307
Subject: Re: Old Xilinx FPGAs
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 14 Aug 2003 09:16:58 -0700
Links: << >>  << T >>  << A >>
Jeff, if you want to maintain or upgrade an existing board or box, your
question makes sense, and Austin gave you some advice.

If you plan a new design, throw these devices and their software away.
New devices, be they Spartan or Virtex-II, are so much cheaper, and so
much more powerful and feature-rich, and the software is so much better...

If you found a '286-based computer, would you start using it??

Using my formula of one FPGA-year = 15 human years, these devices are
>180 years old Civil War veterans. Give them a degnified burial...
Peter Alfke
=========
Jeff Sampson wrote:
> 
> [Please pardon an intrusion from a really casual FPGA/CPLD user]
> 
> I have a collection of old Xilinx parts. XC2018, XC3020, XC3030, XC3064,
> XC4004A. I gave up years ago trying to find software for the XC2018 parts. But I
> assumed my software would do the XC30xx and XC40xx when I got around to using
> them. Now I notice that the Xilinx web page doesn't have spec sheets for the
> base XC30xx and XC40xx or XC40xxA parts. I also notice that me oldest software,
> Foundation Base 1.4 is too new to include these parts. (after casual browsing
> through Foundation Base 1.4, WebPack 4.2, WebPack 5.1i, Student 2.1i)
> 
> So, my question is, am I missing someting? Or do I just need older software?
> 
> Can I use XC3030A to create code for a XC3030? I'm guessing that I can't.
> 
> What about the XC4004A? Can I use XC4003E or XC4003XL to create code for the
> XC4004A? I'm guessing not.
> 
> If I need older software, does anyone have any old software they want to part with?
> 
> I'm guessing old software falls into 3 catagories:
> 
>    1. Better keep it in case we have to update this old stuff.
>    2. It is still here on the shelf because I couldn't bear to throw it away.
>    3. Threw it away years ago.
> 
> Or should I just throw these old parts away and get some Spartan ot Virtex parts?
> 
> --
> Jeff Sampson
> http://tcrobots.org/members/jsamp.htm

Article: 59308
Subject: Re: Actel: Libero/Synplify "Run" button disabled
From: Ken McElvain <ken@synplicity.com>
Date: Thu, 14 Aug 2003 16:47:16 GMT
Links: << >>  << T >>  << A >>
This usually happens when a virus has modified the executable.
I would do a good check and if you find something, then
re-install.

Antti Lukats wrote:

> Hi
> 
> I do answer mostly, but maybe I get some answer when I need some too
> 
> problem
> 
> Actel Libero (latest version) all installed, synplify/actel installed
> 
> but when I launch synplify the "Run" button is disabled (also menu)
> menu "Compile only" is enabled but doesnt do anything :(
> licensing seems to be OK. and I have tried RTFM, but it all tells you
> what todo [when Run is enabled]
> 
> its probably some real silly problem, but nowhere to look :(
> 
> tnx
> antti
> 


Article: 59309
Subject: Re: Virtex II Output Impedance
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Thu, 14 Aug 2003 09:53:45 -0700
Links: << >>  << T >>  << A >>
22.6 ohms, typical corners of PVT

This can be found by using the "terminator Wizard" in Hyperlynx, or by taking
the V/I in the IV tables directly from the ASCII IBIS model.

Austin



Jeremy Whatley wrote:

> Can anyone tell me what kind of output impedance I should expect to see from
> a Xilinx Virtex II XC2V1000-FF896 FPGA?  The Digitally Controlled Impedance
> feature was not used for this design.  The signals in question are LVTTL
> 12mA fast slew rate (I think that's default).
>
> Thanks!
>
> Jeremy Whatley
> jeremyw@erlangtech.com


Article: 59310
Subject: Re: Skew on a clock tree on a virtex II : what is the good figure ?
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Thu, 14 Aug 2003 09:56:44 -0700
Links: << >>  << T >>  << A >>
I am reminded by one of my good friends here in ICDES,

That the skew (delay) of the logic signals is by design larger than the clock network, so the software
doesn't even have to think about skew (much).

In other words, the FPGA interconnect is "correct by design."

That is why it is not a good idea to use local interconnect for clocks and data.

Austin

Austin Lesea wrote:

> JF,
>
> Skew can always be a problem, if you do not take it into account.  Since the software does take
> internal skew into account automatically, with the timing constraints properly set, internal paths
> of the design should have no problems with setup, or hold timing.
>
> External wide IO busses need to be thought out, as the software doesn't understand constraining a
> wide IO buss to less than X skew (nice feature, though).
>
> As the die gets larger, there isn't much you can do, as the speed of light in silicon (propagation
> of signals in the wires), combined with the RC delays, combine to make the longest lines have the
> delays mentioned.
>
> The speed of the chip has almost nothing to do with this (ie the fastest clock rate the global
> clock tree will toggle at).  But it is true that the faster the speed grade, the smaller the skew
> will be.  But the skew is dominated more by the silicon light speed (speed of the signal in
> silicon) and by the metal line RC, which is a small component of the speed grade.
>
> Austin
>
> jean-francois hasson wrote:
>
> > Hi,
> >
> > Considering your answer does it imply that the chip (xc2v6000-5) is
> > not fast enough for a 450 ps skew on the clock to be a problem ?
> >
> > J.F. Hasson
> >
> > Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F3AAE78.AF5F5717@xilinx.com>...
> > > J.F.,
> > >
> > > The report by the tools is correct.
> > >
> > > Different sized parts will have different skews (delays) in the their clock
> > > trees due to size.
> > >
> > > Additionally, skew is a function of position on the tree, so from the top left
> > > corner down to the middle of a part all the way to the bottom left corner, the
> > > skew will be less than 130 ps for a 2V6000, wheras from the top left corner over
> > > towards the top middle over to the right corner, it will be about 450 ps for a
> > > 2V6000.
> > >
> > > Top to bottom: 130 ps.  Right to left: 450 ps.  Smallest in the middles, largest
> > > at the corners.
> > >
> > > For a 2V1000, these are all less than 100 ps.
> > >
> > > Thus if you wanted to make the highest speed wide parallel interface, I would
> > > use the left or right sides (least skew), rather than the top or bottom edges
> > > (for least skew between bits).
> > >
> > > If I had to use the top or bottom edges, I would try to group the IOs near the
> > > center, or near the left and right extremes.
> > >
> > > Again the timing reports and FPGA_Editor report the right (worst case) numbers.
> > >
> > > Hope this helps,
> > >
> > > Austin
> > >
> > > jean-francois hasson wrote:
> > >
> > > > Hi,
> > > >
> > > > I am working on a design involving a virtex II -5. I read in a previous post
> > > > that the skew one could expect from a clock tree is less than 100 ps.
> > > > However when, on the design I am developping, I run the timing analyzer I
> > > > get a skew for some clock on a clock tree of about 450 ps or 500 ps (using
> > > > the 5.1i F23). How should I interpret this difference ? Any clue ? Which
> > > > figure is the right one ?
> > > >
> > > > J.F. Hasson


Article: 59311
Subject: Re: Actel: Libero/Synplify "Run" button disabled
From: "ns" <ns@gmx.at>
Date: Thu, 14 Aug 2003 20:00:21 +0200
Links: << >>  << T >>  << A >>
I think this is a License problem, check if license is ok for new version
and that all path to the licfile are set correct. I had this with Synplify
standalone and an older license.




"Ken McElvain" <ken@synplicity.com> schrieb im Newsbeitrag
news:3F3BBCD5.5010805@synplicity.com...
> This usually happens when a virus has modified the executable.
> I would do a good check and if you find something, then
> re-install.
>
> Antti Lukats wrote:
>
> > Hi
> >
> > I do answer mostly, but maybe I get some answer when I need some too
> >
> > problem
> >
> > Actel Libero (latest version) all installed, synplify/actel installed
> >
> > but when I launch synplify the "Run" button is disabled (also menu)
> > menu "Compile only" is enabled but doesnt do anything :(
> > licensing seems to be OK. and I have tried RTFM, but it all tells you
> > what todo [when Run is enabled]
> >
> > its probably some real silly problem, but nowhere to look :(
> >
> > tnx
> > antti
> >
>



Article: 59312
Subject: Re: Virtex II Output Impedance
From: Andrew Paule <lsboogy@qwest.net>
Date: Thu, 14 Aug 2003 13:26:46 -0500
Links: << >>  << T >>  << A >>
Is the PECL 7 Ohms?

Andrew

Austin Lesea wrote:

>22.6 ohms, typical corners of PVT
>
>This can be found by using the "terminator Wizard" in Hyperlynx, or by taking
>the V/I in the IV tables directly from the ASCII IBIS model.
>
>Austin
>
>
>
>Jeremy Whatley wrote:
>
>  
>
>>Can anyone tell me what kind of output impedance I should expect to see from
>>a Xilinx Virtex II XC2V1000-FF896 FPGA?  The Digitally Controlled Impedance
>>feature was not used for this design.  The signals in question are LVTTL
>>12mA fast slew rate (I think that's default).
>>
>>Thanks!
>>
>>Jeremy Whatley
>>jeremyw@erlangtech.com
>>    
>>
>
>  
>


Article: 59313
Subject: Re: Virtex II Output Impedance
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Thu, 14 Aug 2003 11:56:49 -0700
Links: << >>  << T >>  << A >>
5.6 ohms....

Again from the terminator wizard.  Where did you get 7 ohms?  From the midpoint of
the IV curve (which is pretty close to the estimate from hyperlynx which looks at
the transistion region and averages the R).

Austin

Andrew Paule wrote:

> Is the PECL 7 Ohms?
>
> Andrew
>
> Austin Lesea wrote:
>
> >22.6 ohms, typical corners of PVT
> >
> >This can be found by using the "terminator Wizard" in Hyperlynx, or by taking
> >the V/I in the IV tables directly from the ASCII IBIS model.
> >
> >Austin
> >
> >
> >
> >Jeremy Whatley wrote:
> >
> >
> >
> >>Can anyone tell me what kind of output impedance I should expect to see from
> >>a Xilinx Virtex II XC2V1000-FF896 FPGA?  The Digitally Controlled Impedance
> >>feature was not used for this design.  The signals in question are LVTTL
> >>12mA fast slew rate (I think that's default).
> >>
> >>Thanks!
> >>
> >>Jeremy Whatley
> >>jeremyw@erlangtech.com
> >>
> >>
> >
> >
> >


Article: 59314
Subject: Re: Quartus II and fixing hold timing
From: vbetz@altera.com (Vaughn Betz)
Date: 14 Aug 2003 12:33:24 -0700
Links: << >>  << T >>  << A >>
I made a minor mistake in my previous post.  If you're using Cyclone,
the variable to turn off register packing on any problematic registers
is AUTO_PACKED_REGISTERS_CYCLONE = OFF (not
AUTO_PACKED_REGISTERS_STRATIX = OFF as I said in my previous post. 
So, you can try:

 AUTO_PACKED_REGISTERS_CYCLONE = OFF on low_ad_or_fb[] and
high_ad_or_fb[]

if you find my suggestion #2 in the previous post is indeed the
problem.

Or you can set this through the assignment editor in the GUI, in which
case you don't have to remember the precise variable name (just look
for the AUTO PACKED REGISTERS option).

Regards,

Vaughn
Altera

Article: 59315
Subject: Re: FPGA/DSP Expert - business partner for innovative FFT
From: "Jon Harris" <jon_harrisTIGER@hotmail.com>
Date: Thu, 14 Aug 2003 12:34:22 -0700
Links: << >>  << T >>  << A >>
You can find the patent here:
http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1
&u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1=5528736.WKU.&OS=PN/5528736&RS=PN/55
28736
(Watch the word wrap--I wish I knew how to get shorter URLs out of the USPTO
site.)

Clay, I interpreted his statement about "100% HW utilization" to mean that
it packed well into current FPGA architectures, allowing (near) 100%
utilization of the FPGA, not that it required 100% of any particular HW
device.

-Jon

"Clay S. Turner" <physicsNOOOOSPPPPAMMMM@bellsouth.net> wrote in message
news:sVw_a.7804$_3.5732@fe02.atl2.webusenet.com...
> Hello Seung,
>
> If you have 100% hardware utilization, doesn't this present a problem if
you
> make a change to the design??
>
> Curious what is the # for your patent??
>
> Clay
>
>
> "Seung" <kim.seung@sbcglobal.net> wrote in message
> news:fdf92243.0308131136.74aff961@posting.google.com...
> > Hello
> >
> > I have a patent and recently added one more on innovative FFT
> > algorithm and architecture.
> > If you're a business minded expert on FPGA with interests in DSP, this
> > is a great opportunity. Our FFT is 'the' optimal HW solution as
> > follows:
> >
> > 1. Minimum HW complexity: 100% HW utilization
> > 2. Suitable for super fast pipelined FFT: only local data flow - not
> > based on butterfly algorithm
> > 3. Minimum clock cycles: baseline architecture needs N clock for
> > N-point FFT
> > 4. Scalable to arbitrary large FFT size
> > 5. Multi-dimension extension: world's first 'intrinsic'
> > multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs)
> > : great for 2-D/3-D real-time medical imaging, SAR, etc.
> >
> > If you're interested in building a business together based on this
> > innovation,
> > please contact me with your resume. It'll be ideal if you have
> > contacts for potential customers.
> >
> > Any help on this matter from FPGA/DSP group members will be
> > appreciated.
> >
> >
> > Thanks.
> >
> > Seung P. Kim, Ph.D
> > Silicon Computing, Inc.
> > Mountain View, CA
>
>
>



Article: 59316
Subject: Re: Proto-Board with VirtexII and multiple DDR SDRAM banks?
From: Philip Freidin <philip@fliptronics.com>
Date: Thu, 14 Aug 2003 19:35:53 GMT
Links: << >>  << T >>  << A >>
On 13 Aug 2003 18:09:47 -0700, parin_dalal@yahoo.com (PD) wrote:
>Hi, I could use some help finding an eval/proto-board.  I'm having
>trouble finding a board with multiple DDR SDRAM banks (3+) connected
>to a VirtexII with 1M+ system gates.
>
>The closest board I can find is the Sundance Multiprocessor Technology
>SMT351, which has 4 banks but no DDR (an inadequate data rate).
>
>Any leads?  Thanks for any help you can lend.

You can find lots of links to FPGA boards here:

    http://www.fpga-faq.com/FPGA_Boards.shtml

Philip


Philip Freidin
Fliptronics

Article: 59317
Subject: Off topic - Re: FPGA/DSP Expert - business partner for innovative FFT
From: "Bhaskar Thiagarajan" <bhaskart@deja.com>
Date: Thu, 14 Aug 2003 13:34:04 -0700
Links: << >>  << T >>  << A >>
Jon

This will be your friend for long URLs.
http://tinyurl.com/
You can create a toolbar button and click that after a long link web page
and it voila, out pops the smaller one.
For example...
http://tinyurl.com/k1x6

Cheers
Bhaskar

"Jon Harris" <jon_harrisTIGER@hotmail.com> wrote in message
news:3f3a9180$1_1@newsfeed...
> You can find the patent here:
>
http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1
>
&u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1=5528736.WKU.&OS=PN/5528736&RS=PN/55
> 28736
> (Watch the word wrap--I wish I knew how to get shorter URLs out of the
USPTO
> site.)
>
> Clay, I interpreted his statement about "100% HW utilization" to mean that
> it packed well into current FPGA architectures, allowing (near) 100%
> utilization of the FPGA, not that it required 100% of any particular HW
> device.
>
> -Jon
>
> "Clay S. Turner" <physicsNOOOOSPPPPAMMMM@bellsouth.net> wrote in message
> news:sVw_a.7804$_3.5732@fe02.atl2.webusenet.com...
> > Hello Seung,
> >
> > If you have 100% hardware utilization, doesn't this present a problem if
> you
> > make a change to the design??
> >
> > Curious what is the # for your patent??
> >
> > Clay
> >
> >
> > "Seung" <kim.seung@sbcglobal.net> wrote in message
> > news:fdf92243.0308131136.74aff961@posting.google.com...
> > > Hello
> > >
> > > I have a patent and recently added one more on innovative FFT
> > > algorithm and architecture.
> > > If you're a business minded expert on FPGA with interests in DSP, this
> > > is a great opportunity. Our FFT is 'the' optimal HW solution as
> > > follows:
> > >
> > > 1. Minimum HW complexity: 100% HW utilization
> > > 2. Suitable for super fast pipelined FFT: only local data flow - not
> > > based on butterfly algorithm
> > > 3. Minimum clock cycles: baseline architecture needs N clock for
> > > N-point FFT
> > > 4. Scalable to arbitrary large FFT size
> > > 5. Multi-dimension extension: world's first 'intrinsic'
> > > multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs)
> > > : great for 2-D/3-D real-time medical imaging, SAR, etc.
> > >
> > > If you're interested in building a business together based on this
> > > innovation,
> > > please contact me with your resume. It'll be ideal if you have
> > > contacts for potential customers.
> > >
> > > Any help on this matter from FPGA/DSP group members will be
> > > appreciated.
> > >
> > >
> > > Thanks.
> > >
> > > Seung P. Kim, Ph.D
> > > Silicon Computing, Inc.
> > > Mountain View, CA
> >
> >
> >
>
>



Article: 59318
Subject: Re: Old Xilinx FPGAs
From: symon_brewer@hotmail.com (Symon)
Date: 14 Aug 2003 14:35:05 -0700
Links: << >>  << T >>  << A >>
If you're that nostalgic, I wonder if you could use a modern FPGA to
emulate an old one? You see old arcade games emulated, I guess there's
no reason you couldn't code an XC2018 in HDL and implement it in a
Stratix if you're mad/sad enough! Sort of a Meta-FPGA.
I just searched, someone's already done something similar!
http://ce.et.tudelft.nl/~reinoud/mpga/README.html
        cheers, Syms.

Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F3BAA07.462EBCB3@xilinx.com>...
> Jeff,
> 
> For these ancient devices (see Peter's threads regarding the aging rate of FPGAs),
> there are archived versions of software, but it also takes a computer system that is
> compatible (ie DOS, Windows 3.0, etc).
> 
> By submitting a hotline case online, you will be able to get a response for what
> devices are upward (or downward) bitstream compatible (not all are).
> 
> The early software also used the early hardware keys (dongles), so that is also
> something that is needed....(if anyone offers you some old software -- get the old key
> too!).
> 
> Not something that would interest me in spending time on, as you could probably pick up
> surplus grey market models of much more recent devices that are supported by the free
> Webpack software.
> 
> But, if you are nostalgic.....I hear that folks have FPGA versions of PDP-8
> computers....and cross compilers for IBM 1130's that run on PC's.....strange
> hobbies....but some folks collect stamps, so I suppose I can't really understand any of
> it.
> 
> Austin
> 
> Jeff Sampson wrote:
> 
> > [Please pardon an intrusion from a really casual FPGA/CPLD user]
> >
> > I have a collection of old Xilinx parts. XC2018, XC3020, XC3030, XC3064,
> > XC4004A. I gave up years ago trying to find software for the XC2018 parts. But I
> > assumed my software would do the XC30xx and XC40xx when I got around to using
> > them. Now I notice that the Xilinx web page doesn't have spec sheets for the
> > base XC30xx and XC40xx or XC40xxA parts. I also notice that me oldest software,
> > Foundation Base 1.4 is too new to include these parts. (after casual browsing
> > through Foundation Base 1.4, WebPack 4.2, WebPack 5.1i, Student 2.1i)
> >
> > So, my question is, am I missing someting? Or do I just need older software?
> >
> > Can I use XC3030A to create code for a XC3030? I'm guessing that I can't.
> >
> > What about the XC4004A? Can I use XC4003E or XC4003XL to create code for the
> > XC4004A? I'm guessing not.
> >
> > If I need older software, does anyone have any old software they want to part with?
> >
> > I'm guessing old software falls into 3 catagories:
> >
> >    1. Better keep it in case we have to update this old stuff.
> >    2. It is still here on the shelf because I couldn't bear to throw it away.
> >    3. Threw it away years ago.
> >
> > Or should I just throw these old parts away and get some Spartan ot Virtex parts?
> >
> > --
> > Jeff Sampson
> > http://tcrobots.org/members/jsamp.htm

Article: 59319
Subject: Re: Old Xilinx FPGAs
From: Jeff Sampson <jsampson@pobox.com>
Date: Thu, 14 Aug 2003 17:28:34 -0500
Links: << >>  << T >>  << A >>
After some digging I decided to dump my old parts. I wanted to go with Spartan 
5V parts. But I see they are ancient also. I can only get them through Digikey 
as special order. So somebody doesn't want me to use them...

So unless I find some in 1 or 2 quantity at a reasonable price (this is for a 
prototyping system so I would prefer 5V parts) I guess I'll go with Spartan II 
and use level translators on the outputs.

It also occured to me that I should download all the WebPacks and Spartan data 
sheets from the Xilink web site. Because they might not be there tomorrow. :-)

(PS. I didn't want to be nostalgic. I just wanted to use parts that are still 
being sold on Digikey. :-)

Symon wrote:
> If you're that nostalgic, I wonder if you could use a modern FPGA to
> emulate an old one? You see old arcade games emulated, I guess there's
> no reason you couldn't code an XC2018 in HDL and implement it in a
> Stratix if you're mad/sad enough! Sort of a Meta-FPGA.
> I just searched, someone's already done something similar!
> http://ce.et.tudelft.nl/~reinoud/mpga/README.html
>         cheers, Syms.
> 
> Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F3BAA07.462EBCB3@xilinx.com>...
> 
>>Jeff,
>>
>>For these ancient devices (see Peter's threads regarding the aging rate of FPGAs),
>>there are archived versions of software, but it also takes a computer system that is
>>compatible (ie DOS, Windows 3.0, etc).
>>
>>By submitting a hotline case online, you will be able to get a response for what
>>devices are upward (or downward) bitstream compatible (not all are).
>>
>>The early software also used the early hardware keys (dongles), so that is also
>>something that is needed....(if anyone offers you some old software -- get the old key
>>too!).
>>
>>Not something that would interest me in spending time on, as you could probably pick up
>>surplus grey market models of much more recent devices that are supported by the free
>>Webpack software.
>>
>>But, if you are nostalgic.....I hear that folks have FPGA versions of PDP-8
>>computers....and cross compilers for IBM 1130's that run on PC's.....strange
>>hobbies....but some folks collect stamps, so I suppose I can't really understand any of
>>it.
>>
>>Austin
>>
>>Jeff Sampson wrote:
>>
>>
>>>[Please pardon an intrusion from a really casual FPGA/CPLD user]
>>>
>>>I have a collection of old Xilinx parts. XC2018, XC3020, XC3030, XC3064,
>>>XC4004A. I gave up years ago trying to find software for the XC2018 parts. But I
>>>assumed my software would do the XC30xx and XC40xx when I got around to using
>>>them. Now I notice that the Xilinx web page doesn't have spec sheets for the
>>>base XC30xx and XC40xx or XC40xxA parts. I also notice that me oldest software,
>>>Foundation Base 1.4 is too new to include these parts. (after casual browsing
>>>through Foundation Base 1.4, WebPack 4.2, WebPack 5.1i, Student 2.1i)
>>>
>>>So, my question is, am I missing someting? Or do I just need older software?
>>>
>>>Can I use XC3030A to create code for a XC3030? I'm guessing that I can't.
>>>
>>>What about the XC4004A? Can I use XC4003E or XC4003XL to create code for the
>>>XC4004A? I'm guessing not.
>>>
>>>If I need older software, does anyone have any old software they want to part with?
>>>
>>>I'm guessing old software falls into 3 catagories:
>>>
>>>   1. Better keep it in case we have to update this old stuff.
>>>   2. It is still here on the shelf because I couldn't bear to throw it away.
>>>   3. Threw it away years ago.
>>>
>>>Or should I just throw these old parts away and get some Spartan ot Virtex parts?
>>>
>>>--
>>>Jeff Sampson
>>>http://tcrobots.org/members/jsamp.htm


Article: 59320
Subject: Re: Old Xilinx FPGAs
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 14 Aug 2003 15:36:08 -0700
Links: << >>  << T >>  << A >>
In Xilinx we have been pretty careful to always make the next generation
a functional superset of the previous one.
There are only a few exceptions: 
XC5200 and XC6200 are orphans.
The Xtal oscillator-inverter was discontinued after XC3000.
There were some "wide-edge decoders" in early XC4000.
And of course the pin-outs and the packages and supply voltages changed.
Other than that there should be no problem for "Project Nostalgia".
Staying with Xilinx might be less troublesome than switching to Stratix.
 :-)

Peter Alfke, Xilinx Applications
=================================

Symon wrote:
> 
> If you're that nostalgic, I wonder if you could use a modern FPGA to
> emulate an old one? You see old arcade games emulated, I guess there's
> no reason you couldn't code an XC2018 in HDL and implement it in a
> Stratix if you're mad/sad enough! Sort of a Meta-FPGA.
> I just searched, someone's already done something similar!
> http://ce.et.tudelft.nl/~reinoud/mpga/README.html
>         cheers, Syms.
> 
> Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F3BAA07.462EBCB3@xilinx.com>...
> > Jeff,
> >
> > For these ancient devices (see Peter's threads regarding the aging rate of FPGAs),
> > there are archived versions of software, but it also takes a computer system that is
> > compatible (ie DOS, Windows 3.0, etc).
> >
> > By submitting a hotline case online, you will be able to get a response for what
> > devices are upward (or downward) bitstream compatible (not all are).
> >
> > The early software also used the early hardware keys (dongles), so that is also
> > something that is needed....(if anyone offers you some old software -- get the old key
> > too!).
> >
> > Not something that would interest me in spending time on, as you could probably pick up
> > surplus grey market models of much more recent devices that are supported by the free
> > Webpack software.
> >
> > But, if you are nostalgic.....I hear that folks have FPGA versions of PDP-8
> > computers....and cross compilers for IBM 1130's that run on PC's.....strange
> > hobbies....but some folks collect stamps, so I suppose I can't really understand any of
> > it.
> >
> > Austin
> >
> > Jeff Sampson wrote:
> >
> > > [Please pardon an intrusion from a really casual FPGA/CPLD user]
> > >
> > > I have a collection of old Xilinx parts. XC2018, XC3020, XC3030, XC3064,
> > > XC4004A. I gave up years ago trying to find software for the XC2018 parts. But I
> > > assumed my software would do the XC30xx and XC40xx when I got around to using
> > > them. Now I notice that the Xilinx web page doesn't have spec sheets for the
> > > base XC30xx and XC40xx or XC40xxA parts. I also notice that me oldest software,
> > > Foundation Base 1.4 is too new to include these parts. (after casual browsing
> > > through Foundation Base 1.4, WebPack 4.2, WebPack 5.1i, Student 2.1i)
> > >
> > > So, my question is, am I missing someting? Or do I just need older software?
> > >
> > > Can I use XC3030A to create code for a XC3030? I'm guessing that I can't.
> > >
> > > What about the XC4004A? Can I use XC4003E or XC4003XL to create code for the
> > > XC4004A? I'm guessing not.
> > >
> > > If I need older software, does anyone have any old software they want to part with?
> > >
> > > I'm guessing old software falls into 3 catagories:
> > >
> > >    1. Better keep it in case we have to update this old stuff.
> > >    2. It is still here on the shelf because I couldn't bear to throw it away.
> > >    3. Threw it away years ago.
> > >
> > > Or should I just throw these old parts away and get some Spartan ot Virtex parts?
> > >
> > > --
> > > Jeff Sampson
> > > http://tcrobots.org/members/jsamp.htm

Article: 59321
Subject: Problems with ModelSim (Atmel's System Designer)
From: piran125@interia.pl (Slawek)
Date: 14 Aug 2003 15:43:32 -0700
Links: << >>  << T >>  << A >>
I am trying to simulate small VHDL project (which I syntheze before
with Exemplar logic) and recive errors like below:

# Loading project 
vcom -reportprogress 300 -work work
{C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD}
# Model Technology ModelSim ATMEL vcom 5.5a Compiler 2001.04 Apr  5
2001
# -- Loading package standard
# -- Loading package std_logic_1164
# ERROR: Could not find exemplar.exemplar
# ERROR: C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(8):
cannot find expanded name: exemplar.exemplar
# ERROR: C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(8):
Unknown field: exemplar.
# ERROR: Could not find exemplar.exemplar_1164
# ERROR: C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(9):
cannot find expanded name: exemplar.exemplar_1164
# ERROR: C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(9):
Unknown field: exemplar_1164.
# ERROR: C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(11):
VHDL Compiler exiting


Can You please advise how to show Modelsim the missing packages?
Where to take them from?
I am using these tools as parts of Atmel's System Designer for FPSLIC

Thx for any ideas,
Slawek

Article: 59322
Subject: Re: Old Xilinx FPGAs
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Thu, 14 Aug 2003 22:52:30 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3F3C0D12.9070509@pobox.com>, Jeff Sampson wrote:
> (PS. I didn't want to be nostalgic. I just wanted to use parts that are still 
> being sold on Digikey. :-)

Digikey has Spartan-II chips.

     - Larry

Article: 59323
Subject: Re: Old Xilinx FPGAs
From: Jeff Sampson <jsampson@pobox.com>
Date: Thu, 14 Aug 2003 18:24:52 -0500
Links: << >>  << T >>  << A >>
Larry Doolittle wrote:
> In article <3F3C0D12.9070509@pobox.com>, Jeff Sampson wrote:
> 
>>(PS. I didn't want to be nostalgic. I just wanted to use parts that are still 
>>being sold on Digikey. :-)
> 
> Digikey has Spartan-II chips.
> 
>      - Larry

Oh, what I meant was "I wanted to use the XC30xx and XC40xx parts that I already 
have. After all, they are still being sold by Digikey."

The Spartan II is my current choice because it is sold by Digikey and at least 
one of my software packages will support it. But I have to lay out some cash for it.

I did go to the trouble to change the pin pattern of the flat pack PCB pattern 
for Eagle CAD so I can get the 8mil minimum claerance that Olimex.com wants. So 
I know ahead of time that I can make a board to put the part on.

-- 
Jeff Sampson
http://tcrobots.org/members/jsamp.htm


Article: 59324
Subject: Re: Off topic - Re: FPGA/DSP Expert - business partner for innovative FFT
From: "Jon Harris" <jon_harrisTIGER@hotmail.com>
Date: Thu, 14 Aug 2003 17:13:00 -0700
Links: << >>  << T >>  << A >>
That toolbar method is pretty neat!  The only thing I wonder about is how
long the URL redirection will work.  And of course it assumes that the
tinyURL server is always up.

"Bhaskar Thiagarajan" <bhaskart@deja.com> wrote in message
news:bhgrnu$lln6$1@ID-82263.news.uni-berlin.de...
> Jon
>
> This will be your friend for long URLs.
> http://tinyurl.com/
> You can create a toolbar button and click that after a long link web page
> and it voila, out pops the smaller one.
> For example...
> http://tinyurl.com/k1x6
>
> Cheers
> Bhaskar
>
> "Jon Harris" <jon_harrisTIGER@hotmail.com> wrote in message
> news:3f3a9180$1_1@newsfeed...
> > You can find the patent here:
> >
>
http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1
> >
>
&u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1=5528736.WKU.&OS=PN/5528736&RS=PN/55
> > 28736
> > (Watch the word wrap--I wish I knew how to get shorter URLs out of the
> USPTO
> > site.)
> >
> > Clay, I interpreted his statement about "100% HW utilization" to mean
that
> > it packed well into current FPGA architectures, allowing (near) 100%
> > utilization of the FPGA, not that it required 100% of any particular HW
> > device.
> >
> > -Jon
> >
> > "Clay S. Turner" <physicsNOOOOSPPPPAMMMM@bellsouth.net> wrote in message
> > news:sVw_a.7804$_3.5732@fe02.atl2.webusenet.com...
> > > Hello Seung,
> > >
> > > If you have 100% hardware utilization, doesn't this present a problem
if
> > you
> > > make a change to the design??
> > >
> > > Curious what is the # for your patent??
> > >
> > > Clay
> > >
> > >
> > > "Seung" <kim.seung@sbcglobal.net> wrote in message
> > > news:fdf92243.0308131136.74aff961@posting.google.com...
> > > > Hello
> > > >
> > > > I have a patent and recently added one more on innovative FFT
> > > > algorithm and architecture.
> > > > If you're a business minded expert on FPGA with interests in DSP,
this
> > > > is a great opportunity. Our FFT is 'the' optimal HW solution as
> > > > follows:
> > > >
> > > > 1. Minimum HW complexity: 100% HW utilization
> > > > 2. Suitable for super fast pipelined FFT: only local data flow - not
> > > > based on butterfly algorithm
> > > > 3. Minimum clock cycles: baseline architecture needs N clock for
> > > > N-point FFT
> > > > 4. Scalable to arbitrary large FFT size
> > > > 5. Multi-dimension extension: world's first 'intrinsic'
> > > > multi-dimensional FFT algorithm & architecture (not relay on 1-D
FFTs)
> > > > : great for 2-D/3-D real-time medical imaging, SAR, etc.
> > > >
> > > > If you're interested in building a business together based on this
> > > > innovation,
> > > > please contact me with your resume. It'll be ideal if you have
> > > > contacts for potential customers.
> > > >
> > > > Any help on this matter from FPGA/DSP group members will be
> > > > appreciated.
> > > >
> > > >
> > > > Thanks.
> > > >
> > > > Seung P. Kim, Ph.D
> > > > Silicon Computing, Inc.
> > > > Mountain View, CA
> > >
> > >
> > >
> >
> >
>
>





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