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Messages from 59325

Article: 59325
Subject: Re: Multiple device configuration using local update over ethernet
From: gregs@altera.com (Greg Steinke)
Date: 14 Aug 2003 18:39:44 -0700
Links: << >>  << T >>  << A >>
Mr. Klink,

Altera has tested the remote and local update modes only for single
Stratix devices, so this is what is officially supported. However, we
have put some thought into how these modes could be used in a
multi-device Stratix chain, and here is what we have come up with.
Please keep in mind that these approaches have not been tested, so
there could be an issue that we have not thought of when coming up
with these.


==============================================================================
For Local Update Mode:
======================
Remote System Configuration of a multi-device Stratix chain in local
update mode can be implemented using the following setup. One of the
Stratix devices in the chain should have local update mode enabled
(MSEL[2] set to logic high level) and is designated the master device.
All remaining Stratix devices are setup in normal configuration mode
(MSEL[2] is low) and are chained to the end of this master device. The
nCEO of the master (or previous) Stratix device drives the nCE of the
slave (or subsequent) device. The open-drain nSTATUS and CONF_DONE
signals of the FPGAs are connected in parallel and pulled-up
externally.

The difference between a normal multi-device configuration and local
update multi-device configuration is the nCONFIG connection. In local
update mode, the user can trigger a reconfiguration from core logic
using the RU_nCONFIG signal. While assertion of this signal pulses
nSTATUS low (to reset external host or configuration device) and puts
the master Stratix device in configuration mode, it does not reset the
slave devices since they ignore nSTATUS in user mode. Slave devices
need to be reset by pulsing their nCONFIG inputs low. Slave nCONFIG
pins should be connected in parallel and pulled up externally. A
regular I/O pin on the master device can be setup as an open-drain
output pin and connected to the slave nCONFIG inputs. This I/O pin
should be driven low prior to the RU_nCONFIG signal assertion. This
setup resets and reconfigures all FPGAs in the chain. The nCONFIG
input on the master device is individually pulled-up and isolated from
the slave nCONFIG inputs.

If an external host, such as a MAX CPLD or a processor, is used to
manage configuration, the host should monitor nSTATUS and reconfigure
the chain when it pulses low. When the external host triggers a
reconfiguration, all FPGAs in the chain must be reset.



For Remote Update Mode:
=======================
Remote Configuration of multiple Stratix devices is not supported when
using the Enhanced Configuration devices, but can be implemented when
using an external intelligent host such as a MAX device or a
processor.

In a multi-device setup, the first Stratix device in the chain is the
only device with the Remote/Local Update circuitry enabled (MSEL2 =
1). All remaining devices in the chain, are setup for normal
configuration (MSEL2 = 0). The devices in the chain can be configured
in any of the three supported schemes - Fast Passive Parallel, Passive
Serial, or Passive Parallel Asynchronous. The nCEO of the master (or
first) Stratix device drives the nCE of the slave (or subsequent)
device. The nCONFIG input signal, and open-drain nSTATUS & CONF_DONE
signals are connected in parallel and pulled-up externally.

During initial power-up, the master Stratix device will select the
configuration page (i.e. drive the PGM[] pins) based on its
local/remote update setting on the RUnLU pin. The external host should
sample the PGM[] pins and load the selected configuration files to all
the FPGAs in the chain. If any of the devices detect a configuration
error, the nSTATUS signal will be pulsed low and the external host
must reconfigure the chain based on the new PGM[] pin setting. If the
CONF_DONE signal does not go high after all configuration data has
been sent, the host must pulse nCONFIG and trigger a reconfiguration.

After a remote update is received, the master Stratix device can
trigger a reconfiguration cycle by asserting its internal RU_nCONFIG
signal. This internal RU_nCONFIG assertion will trigger a low pulse on
nSTATUS. The external host must detect this low pulse on nSTATUS. Upon
detection, the host must pulse the nCONFIG signal low to reset all
FPGAs in the chain, sample the PGM[] pins and start a reconfiguration
cycle with the selected configuration page.

A user watchdog timer error on the master Stratix device should be
handled similar to an internal RU_nCONFIG assertion. When the host
detects a low pulse on nSTATUS, it should pulse nCONFIG low, sample
the PGM[] pins and reconfigure the chain with the selected
configuration data set.

Note that the nSTATUS pin is ignored by the slave devices when they
are in user mode. Hence, an external nCONFIG pulse is required before
the reconfiguration cycle. This is also the reason why the Enhanced
Configuration devices do not support multi-device chains.

----------------------------

Sincerely,
Greg Steinke
gregs@altera.com


kommandantklink@hotmail.com (Wilhelm Klink) wrote in message news:<6011e208.0308051712.6cfe0a61@posting.google.com>...
> Yes, you can do it, but can you do it for "local/remote update mode" (ie MSEL2 = 1).
> 
> "Valeria Dal Monte" <prova@microsoft.com> wrote in message news:<seHXa.226441$lK4.6759497@twister1.libero.it>...
> > Wilhelm Klink <kommandantklink@hotmail.com> wrote in message
> > 6011e208.0308042011.5bdae5e1@posting.google.com...
> > > Altera have told me it is not possible to perform a multiple device
> > > configuration (typically done by hooking up the nCE/nCEO pins of the
> > > individual FPGAs) when using local update mode (update over ethernet).
> > >  Does anyone know why it isn't possible?  It is not reasonable for a
> > > board with 10 FPGAs to have 10 separate ethernet connections, and
> > > having to update a set of these boards in the field using a
> > > programming cable would be most tedious.
> > 
> > Regardless of ethernet, at least for the passive serial configuration mode
> > in SRAM devices, it is possible. I did it.

Article: 59326
Subject: Replacement for Cypress Delta 39K part
From: "Brad Smallridge" <bsmallridge@dslextreme.com>
Date: Thu, 14 Aug 2003 20:49:02 -0700
Links: << >>  << T >>  << A >>
Hello fpga group,

I am thinking about replacing a Cypress 39K CPLD (CY39100V208B-200NTC) with
another technology.  Not to sure how to size the task but the volume is low
enough, and the development cycle is early enough that I can spend money to
get a fairly good size fpga, but would rather stay away from the bleeding
edge of technology. If you know what I mean.

The size of the Cypress chip seemed to be OK, so far, that is, the Warp
synthesis tool handled anything I was doing.  However I did intend to use
the dedicated FIFO's that were part of the Cypress architecure, part of the
channel memory or something, they call it.  The XILINX Spartan parts seem to
have dedicated multipliers, that I am not interested in, so perhaps these
are not a good match for me?  What part is best for me?

Thanks for any advise.

Brad



Article: 59327
Subject: Re: Old Xilinx FPGAs
From: Rob Judd <judd@ob-wan.com>
Date: Fri, 15 Aug 2003 13:54:02 +1000
Links: << >>  << T >>  << A >>
Sacrilege! Post 'em to me, I'll use them.

Rob


Antti Lukats wrote:
> 
> Jeff Sampson <jsampson@pobox.com> wrote in message news:<3F3AEA81.6020104@pobox.com>...
> > [Please pardon an intrusion from a really casual FPGA/CPLD user]
> >
> > I have a collection of old Xilinx parts. XC2018, XC3020, XC3030, XC3064,
> > XC4004A. I gave up years ago trying to find software for the XC2018 parts.
> []
> >Or should I just throw these old parts away and get some Spartan/Virtex parts?
> 
> second that: I also have some XC2018 (50+) XC3020,XC3090, etc... parts
> but I am just about throwing them away.
> I had XACT 3.20 on 5 Inch floppy disks, but not sure if it survived the
> process of upgrades :)
> paper cards ->
> paper tape ->
> consumer tape recorder ->
> 8inch floppy ->
> 5inch floppy ->   [old XACT was here! ]
> floppy (as we know) + my first HD (10MB, double height)
> ...
> 
> as of what to use - if you are not in a real hurry - wait up for Spartan III,
> and forget drop trash all below it.
> 
> antti

Article: 59328
Subject: Re: FPGA/DSP Expert - business partner for innovative FFT
From: kim.seung@sbcglobal.net (Seung)
Date: 14 Aug 2003 23:50:36 -0700
Links: << >>  << T >>  << A >>
Hi Jon and Clay,

I used the phrase '100% HW utilization' as an indicator of how well 
the HW matches with the algorithm (as old systolic architecture guys
would
use the term) -  it means no hardware is wasted sitting idle. So it is
not meant for FPGA utilization percentage, but rather usage
indicator of synthesized logic.

Regards,

Seung




"Jon Harris" <jon_harrisTIGER@hotmail.com> wrote in message news:<3f3a9180$1_1@newsfeed>...
> You can find the patent here:
> http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1
> &u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1=5528736.WKU.&OS=PN/5528736&RS=PN/55
> 28736
> (Watch the word wrap--I wish I knew how to get shorter URLs out of the USPTO
> site.)
> 
> Clay, I interpreted his statement about "100% HW utilization" to mean that
> it packed well into current FPGA architectures, allowing (near) 100%
> utilization of the FPGA, not that it required 100% of any particular HW
> device.
> 
> -Jon
> 
> "Clay S. Turner" <physicsNOOOOSPPPPAMMMM@bellsouth.net> wrote in message
> news:sVw_a.7804$_3.5732@fe02.atl2.webusenet.com...
> > Hello Seung,
> >
> > If you have 100% hardware utilization, doesn't this present a problem if
>  you
> > make a change to the design??
> >
> > Curious what is the # for your patent??
> >
> > Clay
> >
> >
> > "Seung" <kim.seung@sbcglobal.net> wrote in message
> > news:fdf92243.0308131136.74aff961@posting.google.com...
> > > Hello
> > >
> > > I have a patent and recently added one more on innovative FFT
> > > algorithm and architecture.
> > > If you're a business minded expert on FPGA with interests in DSP, this
> > > is a great opportunity. Our FFT is 'the' optimal HW solution as
> > > follows:
> > >
> > > 1. Minimum HW complexity: 100% HW utilization
> > > 2. Suitable for super fast pipelined FFT: only local data flow - not
> > > based on butterfly algorithm
> > > 3. Minimum clock cycles: baseline architecture needs N clock for
> > > N-point FFT
> > > 4. Scalable to arbitrary large FFT size
> > > 5. Multi-dimension extension: world's first 'intrinsic'
> > > multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs)
> > > : great for 2-D/3-D real-time medical imaging, SAR, etc.
> > >
> > > If you're interested in building a business together based on this
> > > innovation,
> > > please contact me with your resume. It'll be ideal if you have
> > > contacts for potential customers.
> > >
> > > Any help on this matter from FPGA/DSP group members will be
> > > appreciated.
> > >
> > >
> > > Thanks.
> > >
> > > Seung P. Kim, Ph.D
> > > Silicon Computing, Inc.
> > > Mountain View, CA
> >
> >
> >

Article: 59329
Subject: Re: Problems with ModelSim (Atmel's System Designer)
From: "Alan Fitch" <alan.fitch@doulos.com>
Date: Fri, 15 Aug 2003 09:38:35 +0100
Links: << >>  << T >>  << A >>

"Slawek" <piran125@interia.pl> wrote in message
news:dd729dc8.0308141443.3e517b07@posting.google.com...
> I am trying to simulate small VHDL project (which I syntheze before
> with Exemplar logic) and recive errors like below:
>
> # Loading project
> vcom -reportprogress 300 -work work
> {C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD}
> # Model Technology ModelSim ATMEL vcom 5.5a Compiler 2001.04 Apr  5
> 2001
> # -- Loading package standard
> # -- Loading package std_logic_1164
> # ERROR: Could not find exemplar.exemplar
> # ERROR:
C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(8):
> cannot find expanded name: exemplar.exemplar
> # ERROR:
C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(8):
> Unknown field: exemplar.
> # ERROR: Could not find exemplar.exemplar_1164
> # ERROR:
C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(9):
> cannot find expanded name: exemplar.exemplar_1164
> # ERROR:
C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(9):
> Unknown field: exemplar_1164.
> # ERROR:
C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(11):
> VHDL Compiler exiting
>
>
> Can You please advise how to show Modelsim the missing packages?
> Where to take them from?
> I am using these tools as parts of Atmel's System Designer for
FPSLIC
>
> Thx for any ideas,
> Slawek


You should find the source code (VHDL) for the missing packages
in the Leonardo installation. It's in the file

<path to leonardo>\data\exemplar.vhd

In modelsim, you need to compile that file into a library called
exemplar. From the modelsim command prompt

vlib exemplar
vmap work exemplar
vcom <path to leonardo>\data\exemplar.vhd

vmap work <your normal library>


That should work. However if you use Modelsim Projects, they have
a stupid "feature" of creating a "work" library in a folder called
"work",
which will probably cause my instructions above to fail :-(

So you might find it easier to do this
vlib exemplar

Click the modelsim "Compile" icon.
From the drop-down list of libraries select "exemplar"
Browser to exemplar.vhd
click OK

Then when you compile your normal code, select "work" from
the drop-down list.

When you start simulation, you should be able to see to libraries,
your normal work library, and the library called "exemplar". If you
click on "exemplar" you should see a letter P (for Package) next to
a package called exemplar.

Hope this helps,

kind regards

Alan

-- 
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223                          mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573                           Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.


Article: 59330
Subject: Free VHDL Simulator
From: "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg>
Date: Fri, 15 Aug 2003 17:17:20 +0800
Links: << >>  << T >>  << A >>
Hi All,


Anyone can give some ideas, is there any free VHDL simulator ?

Modelsim is very good but the price is quite expensive :(


Cheers.

Basuki


Article: 59331
Subject: Re: Old Xilinx FPGAs
From: "Ian Poole" <ian.poole@doulos.com>
Date: Fri, 15 Aug 2003 10:29:24 +0100
Links: << >>  << T >>  << A >>
I too have run into this problem, but with a ** Virtex 300 ** device. (I
have an $1800 demo board with an XCV-300PQ240). I tried downloading the free
ISE Webpack, and lo!, no Virtex support. So I downloaded every archived
version I could find, and still no Virtex support. How come none of the
archived versions of Webpack include Virtex support? Did Webpack ever
support Virtex? I can hardly remember what I did last week, let alone what
Webpack did or did not support in 1998 (?) when Virtex came out. If Webpack
did support Virtex at some point in time, does anybody have a copy of said
Webpack? I do still have a 486 PC, an AMD K6 PC, my win3.11 floppies, win95
CD, win98 CD etc so compatability is no issue. Somewhere I even have an
Amstrad CPC6128 as well...

--
Ian Poole, Consultant


"Jeff Sampson" <jsampson@pobox.com> wrote in message
news:3F3AEA81.6020104@pobox.com...
> [Please pardon an intrusion from a really casual FPGA/CPLD user]
>
> I have a collection of old Xilinx parts. XC2018, XC3020, XC3030, XC3064,
> XC4004A. I gave up years ago trying to find software for the XC2018 parts.
But I
> assumed my software would do the XC30xx and XC40xx when I got around to
using
> them. Now I notice that the Xilinx web page doesn't have spec sheets for
the
> base XC30xx and XC40xx or XC40xxA parts. I also notice that me oldest
software,
> Foundation Base 1.4 is too new to include these parts. (after casual
browsing
> through Foundation Base 1.4, WebPack 4.2, WebPack 5.1i, Student 2.1i)
>
> So, my question is, am I missing someting? Or do I just need older
software?
>
> Can I use XC3030A to create code for a XC3030? I'm guessing that I can't.
>
> What about the XC4004A? Can I use XC4003E or XC4003XL to create code for
the
> XC4004A? I'm guessing not.
>
> If I need older software, does anyone have any old software they want to
part with?
>
> I'm guessing old software falls into 3 catagories:
>
>    1. Better keep it in case we have to update this old stuff.
>    2. It is still here on the shelf because I couldn't bear to throw it
away.
>    3. Threw it away years ago.
>
> Or should I just throw these old parts away and get some Spartan ot Virtex
parts?
>
> --
> Jeff Sampson
> http://tcrobots.org/members/jsamp.htm
>



Article: 59332
Subject: Re: Free VHDL Simulator
From: "Ian Poole" <ian.poole@doulos.com>
Date: Fri, 15 Aug 2003 11:03:31 +0100
Links: << >>  << T >>  << A >>
There are free simulators, but since you like Modelsim, several vendors
bundle free versions of Modelsim with their free development software. For
example, the free Xilinx Webpack includes a free version of Modelsim.
Alternatively, a quick search in google for "free vhdl simulator" hits over
10k pages!

--
Ian Poole, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.


"Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message
news:1#hxH4wYDHA.2580@exchnews1.main.ntu.edu.sg...
Hi All,


Anyone can give some ideas, is there any free VHDL simulator ?

Modelsim is very good but the price is quite expensive :(


Cheers.

Basuki




Article: 59333
Subject: jamplayer on WinXP ?
From: Jan Buytaert <buytaert@cern.ch>
Date: Fri, 15 Aug 2003 12:47:08 +0200
Links: << >>  << T >>  << A >>
Hi,
I installed jamplayer2.3 on a windows XP (professional) and also the
jampatch.exe .
I can configure the apex fpga and verify the EPC2, but not program the
epc2.
I am using a byteblasterII bought from altera.
Maybe the parallel port driver is not the correct one, since it
specified support only for NT and dates from the year 2000. But
neitheron the Altera website or elsewhere , I could not find a xp
version.
Thanks for any help or hint
Jan Buytaert


--

      Jan Buytaert


http://public.web.cern.ch/Public/
CERN division EP/ED         |    ("`-''-/").___..--''"`-._
CH 1211 Geneva 23           |     `6_ 6  )   `-.  (     ).`-.__.`)
Tel : 00-41-22-7675737      |     (_Y_.)'  ._   )  `._ `. ``-..-'
Fax : 00-41-22-7679355      |   _..`--'_..-_/  /--'_.' ,'
Office :301-r-008          /|\ (il),-''  (li),'  ((!.-'
Email : buytaert@cern.ch



Article: 59334
Subject: Re: Upgrading OS or WebPack
From: Aart van Beuzekom <aart@westcontrol.com>
Date: Fri, 15 Aug 2003 13:33:56 +0200
Links: << >>  << T >>  << A >>
Report: I tested WebPACK 5.2i, ModelSim XE II v5.6a and iMPACT 5.2.03i
on Windows NT and it all works fine.

Aart


Ralph Mason wrote:
> 
> "Aart van Beuzekom" <aart@westcontrol.com> wrote in message
> news:3F374368.2FADD7D0@westcontrol.com...
> > yes, I am aware of other advantages of running W2K, but the major
> > disadvatage is that this also implies buying a new PC and using a lot of
> > time installing all current programs again. If possible, I want to stick
> > to NT until I've got time to install a new OS (which probably means that
> > I will run NT as long as I work here :-)).
> >
> > Although it is not supported, I installed WebPack 5.2i under NT and the
> > example program (traffic light) runs fine. Does anybody foresee where
> > the problems may rise?
> >
> 
> At a guess I think you should be fine except for impact via a parallel
> cable.
> 
> Ralph

Article: 59335
Subject: Re: Free VHDL Simulator
From: syemetsxp@hotmail.com (Serg_Y)
Date: 15 Aug 2003 06:29:52 -0700
Links: << >>  << T >>  << A >>
try the link
http://sal.kachinatech.com/Z/1/index.shtml
BR

Article: 59336
Subject: Re: jamplayer on WinXP ?
From: Rienk van der Scheer <R.van.der.Scheer@no.3t.spam.nl>
Date: Fri, 15 Aug 2003 15:49:48 +0200
Links: << >>  << T >>  << A >>
Jan Buytaert wrote:
> Hi,
> I installed jamplayer2.3 on a windows XP (professional) and also the
> jampatch.exe .
> I can configure the apex fpga and verify the EPC2, but not program the
> epc2.
> I am using a byteblasterII bought from altera.
> Maybe the parallel port driver is not the correct one, since it
> specified support only for NT and dates from the year 2000. But
> neitheron the Altera website or elsewhere , I could not find a xp
> version.

No problem here with jamplayer 2.3 and byteblasterMV on XP. What error 
message do you get on the EPC2? Did you make sure the JTAG chain in your 
hardware matches the one in the jam file?

Regards,

Rienk


Article: 59337
Subject: Re: Free VHDL Simulator
From: "Nial Stewart" <nial@spamno.nialstewart.co.uk>
Date: Fri, 15 Aug 2003 15:34:37 +0100
Links: << >>  << T >>  << A >>
> Basuki Endah Priyanto <EBEPriyanto@ntu.edu.sg>
> wrote in message news:1#hxH4wYDHA.2580@exchnews1.main.ntu.edu.sg...
> Hi All,
> Anyone can give some ideas, is there any free VHDL simulator ?
> Modelsim is very good but the price is quite expensive :(
> Cheers.
> Basuki

Have a look at

http://www.symphonyeda.com


Nial
------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk




Article: 59338
Subject: Re: Synthesisable fixed-point arithmetic package
From: Jim Lewis <Jim@SynthWorks.com>
Date: Fri, 15 Aug 2003 08:32:18 -0700
Links: << >>  << T >>  << A >>
You may also be interested to know that there is both a fixed point
and floating point package being developed under IEEE 1076.3.

You can find out more information at:

1076.3 General:    http://www.vhdl.org/vhdlsynth/
Floating Point:    http://www.eda.org/fphdl/
Fixed Point:       http://www.vhdl.org/vhdlsynth/proposals/dave_p3.html

Cheers,
Jim Lewis
-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jonathan Bromley wrote:
> Six months after I said "it's nearly done", I've now finished an
> alpha-test version of the synthesisable VHDL fixed-point package
> I promised.  Doesn't time fly when you're enjoying yourself? :-)
> 
> I've published it on our corporate website but, as yet, there are
> no links to it from elsewhere on the site.  So you need to go
> straight to it using this link:
> 
>   http://www.doulos.co.uk/knowhow/vhdl_models/fp_arith/
> 
> At present, all you get is a VHDL package and package body,
> and a PDF doc describing it.
> 
> Any feedback is welcome.  Please note that it is very much
> in an experimental state at present.  It is in desperate need
> of example designs and a validation test suite;  contributions
> towards either will be gratefully received, and acknowledged in
> future releases.
> 
> I would be especially grateful for any indication of whether it's
> aiming in the right direction, and how it could be enhanced or
> made more useful.
> 
> My employers are not responsible for any part of the package.
> Any comments on it should come directly to me at the
> address given below.
> --
> Jonathan Bromley, Consultant
> 
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
> 
> Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
> Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
> Fax: +44 (0)1425 471573                           Web: http://www.doulos.com
> 
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


Article: 59339
Subject: Re: Old Xilinx FPGAs
From: Steve Lass <lass@xilinx.com>
Date: Fri, 15 Aug 2003 09:42:27 -0600
Links: << >>  << T >>  << A >>
Ian Poole wrote:

>I too have run into this problem, but with a ** Virtex 300 ** device. (I
>have an $1800 demo board with an XCV-300PQ240). I tried downloading the free
>ISE Webpack, and lo!, no Virtex support. So I downloaded every archived
>version I could find, and still no Virtex support. How come none of the
>archived versions of Webpack include Virtex support?
>
WebPACK was originally intended for CPLDs.  When we decided to add 
FPGAs, Virtex-E was
available and was faster and cheaper than Virtex.   So, Virtex was never 
considered for WebPACK.

Steve

> Did Webpack ever
>support Virtex? I can hardly remember what I did last week, let alone what
>Webpack did or did not support in 1998 (?) when Virtex came out. If Webpack
>did support Virtex at some point in time, does anybody have a copy of said
>Webpack? I do still have a 486 PC, an AMD K6 PC, my win3.11 floppies, win95
>CD, win98 CD etc so compatability is no issue. Somewhere I even have an
>Amstrad CPC6128 as well...
>
>--
>Ian Poole, Consultant
>
>
>"Jeff Sampson" <jsampson@pobox.com> wrote in message
>news:3F3AEA81.6020104@pobox.com...
>  
>
>>[Please pardon an intrusion from a really casual FPGA/CPLD user]
>>
>>I have a collection of old Xilinx parts. XC2018, XC3020, XC3030, XC3064,
>>XC4004A. I gave up years ago trying to find software for the XC2018 parts.
>>    
>>
>But I
>  
>
>>assumed my software would do the XC30xx and XC40xx when I got around to
>>    
>>
>using
>  
>
>>them. Now I notice that the Xilinx web page doesn't have spec sheets for
>>    
>>
>the
>  
>
>>base XC30xx and XC40xx or XC40xxA parts. I also notice that me oldest
>>    
>>
>software,
>  
>
>>Foundation Base 1.4 is too new to include these parts. (after casual
>>    
>>
>browsing
>  
>
>>through Foundation Base 1.4, WebPack 4.2, WebPack 5.1i, Student 2.1i)
>>
>>So, my question is, am I missing someting? Or do I just need older
>>    
>>
>software?
>  
>
>>Can I use XC3030A to create code for a XC3030? I'm guessing that I can't.
>>
>>What about the XC4004A? Can I use XC4003E or XC4003XL to create code for
>>    
>>
>the
>  
>
>>XC4004A? I'm guessing not.
>>
>>If I need older software, does anyone have any old software they want to
>>    
>>
>part with?
>  
>
>>I'm guessing old software falls into 3 catagories:
>>
>>   1. Better keep it in case we have to update this old stuff.
>>   2. It is still here on the shelf because I couldn't bear to throw it
>>    
>>
>away.
>  
>
>>   3. Threw it away years ago.
>>
>>Or should I just throw these old parts away and get some Spartan ot Virtex
>>    
>>
>parts?
>  
>
>>--
>>Jeff Sampson
>>http://tcrobots.org/members/jsamp.htm
>>
>>    
>>
>
>
>  
>


Article: 59340
Subject: Re: Problem with Modelsim Lisence server...
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Fri, 15 Aug 2003 09:12:24 -0700
Links: << >>  << T >>  << A >>
Debashish wrote:

> Here i have a problem with my Modelsim lisence server.I have 2
> lisences for modelsim in my office. But many a times if someone dont
> close the modelsim properly or dont release the lisence (by command
> quit -sim), lisence stays active even if he is not working.So most of
> the time i am not able to use 2 linces. So being a Windows 2000 server
> we had to restart it again and agian atleast once everyday, two kill
> those process and regain the 2 lisences.

1. Learn the lmstat command to find out who is holding licenses,
    and train them to close the gui.

2. Learn to use command line execution: vcom -c and vsim -c.
    vcom (command line) does not require a license. Bringing up
    the gui with vsim.exe holds a licenses for the whole
    session, even if you are just editing and compiling.

    Running a text testbench with vsim -c only holds the license
    during a sim and then relinquishes it.


      -- Mike Treseler


Article: 59341
Subject: Re: comp.lang.vhdl
From: "Colin Jackson" <jacksoncolin@fake_yahoo.com>
Date: Fri, 15 Aug 2003 12:26:49 -0400
Links: << >>  << T >>  << A >>
It's still there.
Perhaps your News Service doesn't subscribe anymore.
There are a lot of free ones.  Pick one that covers comp.lang.vhdl.


"Arie Zychlinski" <arie_zy@bezeqint.net> wrote in message
news:3f3cfea7@news.bezeqint.net...
> sorry to ask here BUT has anything happened to comp.lang.vhdl ?
>
> -- 
>
>                            yours -
>                                      Arie Z.
>
> ============================================
>  Arie  Zychlinski
>  R&D Consulting & Development
>  P.O.Box  536
>  Kfar-Saba  44104
>  ISRAEL
>
>  Mobile: 972-58-320230
>  Phone:  W: 972-9-7673074   H: 972-9-7658268
>
>  E-Mail:  arie_zy@bezeqint.net
>  ===========================================
>
>



Article: 59342
Subject: Re: Free VHDL Simulator
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Fri, 15 Aug 2003 16:27:29 +0000 (UTC)
Links: << >>  << T >>  << A >>

"Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message
news:1%23hxH4wYDHA.2580@exchnews1.main.ntu.edu.sg...
Hi All,


Anyone can give some ideas, is there any free VHDL simulator ?

Modelsim is very good but the price is quite expensive :(



The free demo version of Sonata might do what you want:

http://www.symphonyeda.com/

Leon
-- 
Leon Heller, G1HSM
leon_heller@hotmail.com
http://www.geocities.com/leon_heller



Article: 59343
Subject: comp.lang.vhdl
From: "Arie Zychlinski" <arie_zy@bezeqint.net>
Date: Fri, 15 Aug 2003 18:37:52 +0200
Links: << >>  << T >>  << A >>
sorry to ask here BUT has anything happened to comp.lang.vhdl ?

-- 

                           yours -
                                     Arie Z.

============================================
 Arie  Zychlinski
 R&D Consulting & Development
 P.O.Box  536
 Kfar-Saba  44104
 ISRAEL

 Mobile: 972-58-320230
 Phone:  W: 972-9-7673074   H: 972-9-7658268

 E-Mail:  arie_zy@bezeqint.net
 ===========================================



Article: 59344
Subject: where can I find DWT source code(verilog or vhdl)?
From: "walala" <mizhael@yahoo.com>
Date: Fri, 15 Aug 2003 11:51:40 -0500
Links: << >>  << T >>  << A >>
Dear all,

Can anybody give me a hand by telling me where to find Discrete Wavelet
Transform source code implementation?

Thanks a lot,

-Walala



Article: 59345
Subject: Re: Free VHDL Simulator
From: Stephen Williams <spamtrap@icarus.com>
Date: Fri, 15 Aug 2003 10:12:10 -0700
Links: << >>  << T >>  << A >>
Basuki Endah Priyanto wrote:
> Hi All,
> 
> 
> Anyone can give some ideas, is there any free VHDL simulator ?
> 
> Modelsim is very good but the price is quite expensive :(

I hvae no idea how good it is (may be a dud, may be great)
but there is GHDL: <http://ghdl.free.fr>


-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


Article: 59346
Subject: Re: Data Structure Viewer
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Fri, 15 Aug 2003 11:06:04 -0700
Links: << >>  << T >>  << A >>


Jim Wu wrote:
> Data Structure Viewer is a GUI based tool written in Perl and Perl-Tk. It
> allows you to convert between a data structure (e.g. IPv4 header) and
> individual fields in the data structure by simple mouse clicks. It can be
> configured to support almost any data structure definition. Please check it
> out at http://www.geocities.com/jimwu88/chips/
> 
> Please let me know about any questions or suggestions.

Thanks.
Well done.
Useful for creating/checking bit packed fields.
Easy to extend to other headers.

  -- Mike


Article: 59347
Subject: Re: Problems with ModelSim (Atmel's System Designer)
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Fri, 15 Aug 2003 11:57:09 -0700
Links: << >>  << T >>  << A >>


Slawek wrote:
> I am trying to simulate small VHDL project (which I syntheze before
> with Exemplar logic) and recive errors like below:
> 
> # Loading project 
> vcom -reportprogress 300 -work work

> # ERROR: Could not find exemplar.exemplar
> # ERROR: Could not find exemplar.exemplar_1164


Try commenting out the USE commands containing exemplar.
There is a good chance that these are not really being referenced.

If they are, consider fixing up the code to use
the standard ieee packages:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

There is no longer much upside to using
vendor specific packages.

  -- Mike Treseler


Article: 59348
Subject: Re: Memory map in Altera NIOS
From: kempaj@yahoo.com (Jesse Kempa)
Date: 15 Aug 2003 12:10:25 -0700
Links: << >>  << T >>  << A >>
Hi,

I am assuming that you are referring to a peripheral connected to
Avalon. There are really two variables (design choices) which will
affect this. First is whether you choose "Avalon Memory Slave" or
"Avalon Register Slave" in the I/F to user logic. Choosing "memory
slave" activates an Avalon feature called "Dynamic Bus Sizing", while
"register slave" activates native bus alignment. The second variable
is the width of the master connecting to the slave peripheral... with
these in mind, please take a look at the most recent version of the
Avalon Bus Spec (http://www.altera.com/literature/manual/mnl_avalon_bus.pdf
- look for the "Bus Address Alignment Options" section) to see how the
master address is wired up to the slave address - it also lists
several detailed examples of how the addressing on the master side is
translated to the slave.

Jesse Kempa
Altera Corp.
jkempa at altera dot com
 

jwing23@hotmail.com (J-Wing) wrote in message news:<d6e7734d.0308132137.558c5c8f@posting.google.com>...
> Can anyone tell me how the memory map in the Altera NIOS works (in
> software-C and hardware-VHDL)? I am not sure how the layout is and
> where to read and write data to user logic.

Article: 59349
Subject: Re: Replacement for Cypress Delta 39K part
From: spam_hater_7@email.com (Spam Hater 7)
Date: 15 Aug 2003 12:57:01 -0700
Links: << >>  << T >>  << A >>
Take a close look at Altera's offerings.

True 5V parts, supported by current software, and FIFOs are available
as standard macros.

HTH

"Brad Smallridge" <bsmallridge@dslextreme.com> wrote in message news:<vjom3o4qtbgube@corp.supernews.com>...
> Hello fpga group,
> 
> I am thinking about replacing a Cypress 39K CPLD (CY39100V208B-200NTC) with
> another technology.  Not to sure how to size the task but the volume is low
> enough, and the development cycle is early enough that I can spend money to
> get a fairly good size fpga, but would rather stay away from the bleeding
> edge of technology. If you know what I mean.
> 
> The size of the Cypress chip seemed to be OK, so far, that is, the Warp
> synthesis tool handled anything I was doing.  However I did intend to use
> the dedicated FIFO's that were part of the Cypress architecure, part of the
> channel memory or something, they call it.  The XILINX Spartan parts seem to
> have dedicated multipliers, that I am not interested in, so perhaps these
> are not a good match for me?  What part is best for me?
> 
> Thanks for any advise.
> 
> Brad



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