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Messages from 59400

Article: 59400
Subject: DDFS question
From: "David Lamb" <gretzteam_nospam@yahoo.com>
Date: Mon, 18 Aug 2003 13:58:57 -0500
Links: << >>  << T >>  << A >>
Hi everyone,
I need to generate a 16khz clock from a 13mhz input clock. I read a lot of
post on DDFS but I still don't understand how precise is the output clock.
Fout = Fclock * N / 2^k
If I use k= 21 bits and N=2581, I would obtain a 15.9993 khz clock.
However, I read that there is jitter on the output clock up to the input
clock period. I thus wonder if this <complicated> clock divider would really
yield better result than generating a pulse at every 812/813 (alternating)
input clock pulse. On average, this is a 16khz clock, and it jitters by one
input clock period. Am I missing something here?
Thanks
David



Article: 59401
Subject: Re: serial communication between pc and altera fpga
From: Joe <xxxxx@yyyyy.com>
Date: Mon, 18 Aug 2003 20:13:55 +0100
Links: << >>  << T >>  << A >>
sarah wrote:

> thanks.
> 
> For fpga, the uart is working.
> 
> For pc part, what is the meaning MFC? IS it microsoft? Can you tell me
> the name of Petzold's Richter's or Oney's books ?
> 
> Thank you.
> 
> Sarah
> 

MFC is Microsoft Foundation Classes.
You can also access to the serial port by serial driver API
function calls. (API = Application Programming Interface)

If you use visual basic, there is one example on the CD-ROM
of a book call Viusal basic Programmer's Guide to the Win32 API.
ISBN 0-672-31590-4.  But it didn't go into too much detail
either.

Joe





Article: 59402
Subject: Re: serial communication between pc and altera fpga
From: "Jean Nicolle" <j.nicolle@sbcglobal.net>
Date: Mon, 18 Aug 2003 19:25:11 GMT
Links: << >>  << T >>  << A >>
here's a very simple sample code in C
http://www.fpga4fun.com/files/LCDmodule_com.zip


"sarah" <sarahshen2003@yahoo.ca> wrote in message
news:d51c0c2.0308171312.59523daa@posting.google.com...
> hI,
>
> I have a project. I need to realise the serial communication between
> PC
> and Altera APEX20KE FPGA in c or c++. The function of UART in FPGA is
> working well. It can send data through uart to PC. For PC, The task is
> to receive the data from FPGA UART and give the control signal to FPGA
> through the serial port in pc. My operating system is win2000.
>
> Does anybody know how to realise it in c or c++?
>
> Thanks.
>
> Sarah



Article: 59403
Subject: Re: Anyone familiar with ispXPLD?
From: paul_sereno@hotmail.com (Paul Sereno)
Date: 18 Aug 2003 12:29:19 -0700
Links: << >>  << T >>  << A >>
Jay,

Basically, the XPLD is a CPLD with the option of using the MFB (former
GLB) as memory (Dual Port RAM, Single Port RAM, FIFO, CAM, etc). This
is due to the fact that the logic is actually implemented in SRAM
cells (like FPGAs). The part has the EE memory integrated in the same
die. After programming the EE, the SRAM is configured in less than
200us (like almost any CPLD), what is called instant-on.
Another good point is that the software is free from the Lattice
website.

Hope this helps, 

Paul

"Jay" <yuhaiwen@hotmail.com> wrote in message news:<bhesmv$sdl$1@ID-195883.news.uni-berlin.de>...
> Hi all,
> 
> I only have used xc9500 and coolrunnerII before, and we all know such CPLDs
> has so little FF resources.
> For my current applications I need to map some memorys and I think ispXPLD
> is what I'm looking for.
> But before I start my work on it, I'd like make something clear:
> 1.It sounds great that ispXPLD has plennty of memory resources, and that's
> what I want most. So what's the payoff compared with common CPLDs, cost?
> performance?
> 2.ispXPLD has a new architecture MFB which I'm not familiar with. From a
> designer's point of view, is there any difference between XPLD and CPLD? Do
> I need extra knowledges or skills?
> 
> Thanks.

Article: 59404
Subject: Re: Altera JTAG verification
From: gregs@altera.com (Greg Steinke)
Date: 18 Aug 2003 12:48:26 -0700
Links: << >>  << T >>  << A >>
Rajeev,
It's very unlikely that the device's configuration is getting
corrupted after entering user mode. To prevent this, the Altera device
has a circuit that monitors the VCC. If the VCC drops to near the
level needed to sustain the SRAM bits (which is well under the 3.0V
spec for ACEX devices), then the device resets itself and pulls
nSTATUS low. This happens before actually reaching the point at which
the VCC dips and causes SRAM corruption. While nothing is impossible,
it's not likely that this is the cause of the problem.

To answer your direct question - there's no way to read back the
programming file from the ACEX device. However, since SRAM corruption
is unlikely, this would not help anyhow. BTW, the MAX+PLUS II Verify
option is for verifying the programming of EEPROM based ISP devices
like MAX 3000A, which have a different mechanism for programming.

For the broader question of "Why do some of the devices function
incorrectly?" there's many possibilities. If the device's CONF_DONE
has gone high, it has correctly received the configuration file. Any
corruption during the transmit process will be captured by the CRC on
each configuration frame. If the device is not operating at all, it
may have received the configuration data but not been initialized into
user mode. If it is operating, but not as desired, then it's more
complicated; there's many possible reasons for that, and it's hard to
diagnose without more details.

I suggest checking some of the items in the last paragraph. If it is
configured, and has entered user mode, but is doing something
unexpected, I suggest filing a service request with MySupport on
www.altera.com so someone will work with you to solve the issue.

Sincerely,
Greg Steinke
gregs@altera.com
Altera 


rrr@ieee.org (Rajeev) wrote in message news:<c0f37b00.0308180607.97eec69@posting.google.com>...
> We have a board with approx 30 ACEX devices.  For pin count
> reasons, the devices are configured via the JTAG port.  
> I have built a small dumb PC peripheral that allows us to
> do bit-banging of the JTAG lines with some efficiency.  At
> the PC end we have ported Altera's JAM player, we build and
> use text JAM files rev 2.0, we call the JAM player with the
> -ACONFIGURE option.
> 
> The system works.
> 
> The problem we have is that we will sometimes get a successful
> load of all devices, but one or the other device does not
> function correctly.  I am speculating that perhaps a device
> is correctly configured, but gets corrupted later during the
> configuration cycle.  What I would like to do is use JTAG to
> verify all devices, _after_ all the devices are configured.
> 
> Unfortunately, the JAM file build option in MaxPlus2 shows a 
> verification option but it is grayed out.
> 
> What I'm hoping someone will be able to help me with is:
> 
> 1. How hard is this ?  Are there some options somewhere that would
> allow me to use existing tools to readback and verify all the 
> config bits post-facto ?  Or is more engineering called for ?
> 
> 2. If it's hard, where can I go to get help, paid or otherwise ?
> 
> Thanks !
> -rajeev-

Article: 59405
Subject: Re: DDFS question
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 18 Aug 2003 20:00:03 GMT
Links: << >>  << T >>  << A >>
You've got it right.

You could control any divider to switch between a divide by n or n+1 to
achieve a frequency between F/n and F/(n+1).  You get the simple case where
the control is a square wave.  If it wasn't a square wave, how would you
control the fraction?  With an accumulator.  Just like the standard DDFS.

DDFS (DDS to some) gives you flexibility that you don't get with an
implementation for a specific frequency divider.

The jitter will be about 77 ns with either approach but - at 16kHz - what
does it really matter?

If you have a higher frequency clock available, you could get better jitter
characteristics.  If you can divide your clock into multiple phases, you can
get better jitter characteristics.


"David Lamb" <gretzteam_nospam@yahoo.com> wrote in message
news:bhr7jv$dl7$1@home.itg.ti.com...
> Hi everyone,
> I need to generate a 16khz clock from a 13mhz input clock. I read a lot of
> post on DDFS but I still don't understand how precise is the output clock.
> Fout = Fclock * N / 2^k
> If I use k= 21 bits and N=2581, I would obtain a 15.9993 khz clock.
> However, I read that there is jitter on the output clock up to the input
> clock period. I thus wonder if this <complicated> clock divider would
really
> yield better result than generating a pulse at every 812/813 (alternating)
> input clock pulse. On average, this is a 16khz clock, and it jitters by
one
> input clock period. Am I missing something here?
> Thanks
> David
>
>



Article: 59406
Subject: Re: Which software from Xilinx
From: orgulhosamenteso@hotmail.com (Pedro Claro)
Date: 18 Aug 2003 13:07:39 -0700
Links: << >>  << T >>  << A >>
"Davo" <dgwood@optushome.com.au> wrote in message news:<3f3f8e6f$0$10355$afc38c87@news.optusnet.com.au>...
> I want to work from home on my University project. The University uses
> Foundation 4.2 and I want to know if any of the free downloads (i.e Webpack)
> will be compatitble so that I can take me designs into Uni done from home
> and have no trouble simulating on their platform. I am sure this question
> has been asked and answered many times. Apologies if so.
> 
> Dave

I believe the Xilinx Webpack is compatible with the ISE 4.2. You can
also save only the vhdl files and the waveforms.

Pedro Claro

Article: 59407
Subject: Re: Which software from Xilinx
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Mon, 18 Aug 2003 13:56:22 -0700
Links: << >>  << T >>  << A >>

Hi,

Based on my experience teaching a Xilinx lab
course at SJSU, I suggest you do not try to
mix and match versions...

I tell my students to go out and buy the XSE
4.2i product, which is available from Prentice
Hall.  This way, you can use the same thing at
home as you are using in the lab.

Eric

Pedro Claro wrote:
> 
> "Davo" <dgwood@optushome.com.au> wrote in message news:<3f3f8e6f$0$10355$afc38c87@news.optusnet.com.au>...
> > I want to work from home on my University project. The University uses
> > Foundation 4.2 and I want to know if any of the free downloads (i.e Webpack)
> > will be compatitble so that I can take me designs into Uni done from home
> > and have no trouble simulating on their platform. I am sure this question
> > has been asked and answered many times. Apologies if so.
> >
> > Dave
> 
> I believe the Xilinx Webpack is compatible with the ISE 4.2. You can
> also save only the vhdl files and the waveforms.
> 
> Pedro Claro

Article: 59408
Subject: Re: Xilinx DLL driving multiple off chip clocks
From: "Ken Morrow" <junk@not_morro.co.uk>
Date: Mon, 18 Aug 2003 22:24:04 +0100
Links: << >>  << T >>  << A >>
Marc and Martin,

Thank you very much for your help.

The XCELL article was very useful. Its a pity that the Search facility on
the Xilinx web site does not seem to pick up such articles.

I have eventually went with Marc's idea of using the DDR output flip-flop,
clocked by the global clock and its inverse, to output
the clock. Sounds like this solution would require less work for the router
.
I did find a very useful answer on the Xilinx site describing this, but I
don't seem to be able to find it again.
I will post the URL when I do find it.

Thanks Again,

Ken Morrow.





Article: 59409
Subject: Re: DDFS question
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 18 Aug 2003 15:01:44 -0700
Links: << >>  << T >>  << A >>
If you really care about nanosecond jitter, here is the best solution:
Double your 13 MHz input frequency and then divide the result by 1625.
If you use "my" frequency doubler (TechXclusives, 6 easy pieces), you
end up with the perfect frequency and a jitter equal to the duty-cycle
error of the 13 MHz, probably less than 10 ns.  The whole circuit costs
you a dozen flip-flops.
Peter Alfke, Xilinx Applications.
========================
David Lamb wrote:
> 
> Hi everyone,
> I need to generate a 16khz clock from a 13mhz input clock. I read a lot of
> post on DDFS but I still don't understand how precise is the output clock.
> Fout = Fclock * N / 2^k
> If I use k= 21 bits and N=2581, I would obtain a 15.9993 khz clock.
> However, I read that there is jitter on the output clock up to the input
> clock period. I thus wonder if this <complicated> clock divider would really
> yield better result than generating a pulse at every 812/813 (alternating)
> input clock pulse. On average, this is a 16khz clock, and it jitters by one
> input clock period. Am I missing something here?
> Thanks
> David

Article: 59410
Subject: Re: Altera JTAG verification
From: Andrew Paule <lsboogy@qwest.net>
Date: Mon, 18 Aug 2003 17:39:44 -0500
Links: << >>  << T >>  << A >>
Greg:

one thing not pointed out here is signal integrity - seen too many 
boards with bounce and jounce on lines - not just VCC.  Good reflection 
on a TDI/TDO pair might cause the problem.  That's why I suggested he 
read out the data and compare it to the serial file he's putting in. 

Andrew

Greg Steinke wrote:

>Rajeev,
>It's very unlikely that the device's configuration is getting
>corrupted after entering user mode. To prevent this, the Altera device
>has a circuit that monitors the VCC. If the VCC drops to near the
>level needed to sustain the SRAM bits (which is well under the 3.0V
>spec for ACEX devices), then the device resets itself and pulls
>nSTATUS low. This happens before actually reaching the point at which
>the VCC dips and causes SRAM corruption. While nothing is impossible,
>it's not likely that this is the cause of the problem.
>
>To answer your direct question - there's no way to read back the
>programming file from the ACEX device. However, since SRAM corruption
>is unlikely, this would not help anyhow. BTW, the MAX+PLUS II Verify
>option is for verifying the programming of EEPROM based ISP devices
>like MAX 3000A, which have a different mechanism for programming.
>
>For the broader question of "Why do some of the devices function
>incorrectly?" there's many possibilities. If the device's CONF_DONE
>has gone high, it has correctly received the configuration file. Any
>corruption during the transmit process will be captured by the CRC on
>each configuration frame. If the device is not operating at all, it
>may have received the configuration data but not been initialized into
>user mode. If it is operating, but not as desired, then it's more
>complicated; there's many possible reasons for that, and it's hard to
>diagnose without more details.
>
>I suggest checking some of the items in the last paragraph. If it is
>configured, and has entered user mode, but is doing something
>unexpected, I suggest filing a service request with MySupport on
>www.altera.com so someone will work with you to solve the issue.
>
>Sincerely,
>Greg Steinke
>gregs@altera.com
>Altera 
>
>
>rrr@ieee.org (Rajeev) wrote in message news:<c0f37b00.0308180607.97eec69@posting.google.com>...
>  
>
>>We have a board with approx 30 ACEX devices.  For pin count
>>reasons, the devices are configured via the JTAG port.  
>>I have built a small dumb PC peripheral that allows us to
>>do bit-banging of the JTAG lines with some efficiency.  At
>>the PC end we have ported Altera's JAM player, we build and
>>use text JAM files rev 2.0, we call the JAM player with the
>>-ACONFIGURE option.
>>
>>The system works.
>>
>>The problem we have is that we will sometimes get a successful
>>load of all devices, but one or the other device does not
>>function correctly.  I am speculating that perhaps a device
>>is correctly configured, but gets corrupted later during the
>>configuration cycle.  What I would like to do is use JTAG to
>>verify all devices, _after_ all the devices are configured.
>>
>>Unfortunately, the JAM file build option in MaxPlus2 shows a 
>>verification option but it is grayed out.
>>
>>What I'm hoping someone will be able to help me with is:
>>
>>1. How hard is this ?  Are there some options somewhere that would
>>allow me to use existing tools to readback and verify all the 
>>config bits post-facto ?  Or is more engineering called for ?
>>
>>2. If it's hard, where can I go to get help, paid or otherwise ?
>>
>>Thanks !
>>-rajeev-
>>    
>>


Article: 59411
Subject: Re: DDFS question
From: symon_brewer@hotmail.com (Symon)
Date: 18 Aug 2003 15:52:38 -0700
Links: << >>  << T >>  << A >>
Hi David,
       If your 13 MHz (I assume you mean MHz not mHz!!) clock has a
50% duty cycle, you could use both edges of it to get 16kHz spot on.
Might be simpler than the DDFS.
       The Xilinx guys will suggest using a DCM to double the clock
frequency. You need to use the CLKFX output as the clock in is less
than 25MHz IIRC. Or, Peter Alfke as has some dodgy circuit ;-) to
double clocks, check out Xilinx's Tech Exclusives page.
         All the best, Syms.


"David Lamb" <gretzteam_nospam@yahoo.com> wrote in message news:<bhr7jv$dl7$1@home.itg.ti.com>...
> Hi everyone,
> I need to generate a 16khz clock from a 13mhz input clock. I read a lot of
> post on DDFS but I still don't understand how precise is the output clock.
> Fout = Fclock * N / 2^k
> If I use k= 21 bits and N=2581, I would obtain a 15.9993 khz clock.
> However, I read that there is jitter on the output clock up to the input
> clock period. I thus wonder if this <complicated> clock divider would really
> yield better result than generating a pulse at every 812/813 (alternating)
> input clock pulse. On average, this is a 16khz clock, and it jitters by one
> input clock period. Am I missing something here?
> Thanks
> David

Article: 59412
Subject: Re: DDFS question
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Mon, 18 Aug 2003 16:10:00 -0700
Links: << >>  << T >>  << A >>
Symon,

Actually the "Xilinx Guy" (Peter) suggested using a simple clock doubler.....

The DCM will not operate in DLL mode below 24 MHz, so one has to use the DFS CLKFX output with M=2,
and D=1 if you want to double that way (and it works fine if you have a DCM to spare in the V2, V2P,
or the S3).

Austin

Symon wrote:

> Hi David,
>        If your 13 MHz (I assume you mean MHz not mHz!!) clock has a
> 50% duty cycle, you could use both edges of it to get 16kHz spot on.
> Might be simpler than the DDFS.
>        The Xilinx guys will suggest using a DCM to double the clock
> frequency. You need to use the CLKFX output as the clock in is less
> than 25MHz IIRC. Or, Peter Alfke as has some dodgy circuit ;-) to
> double clocks, check out Xilinx's Tech Exclusives page.
>          All the best, Syms.
>
> "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message news:<bhr7jv$dl7$1@home.itg.ti.com>...
> > Hi everyone,
> > I need to generate a 16khz clock from a 13mhz input clock. I read a lot of
> > post on DDFS but I still don't understand how precise is the output clock.
> > Fout = Fclock * N / 2^k
> > If I use k= 21 bits and N=2581, I would obtain a 15.9993 khz clock.
> > However, I read that there is jitter on the output clock up to the input
> > clock period. I thus wonder if this <complicated> clock divider would really
> > yield better result than generating a pulse at every 812/813 (alternating)
> > input clock pulse. On average, this is a 16khz clock, and it jitters by one
> > input clock period. Am I missing something here?
> > Thanks
> > David


Article: 59413
Subject: Re: custom memory array implementaion
From: Ray Andraka <ray@andraka.com>
Date: Mon, 18 Aug 2003 19:34:03 -0400
Links: << >>  << T >>  << A >>
Absolutely.  It reduces area and therefore part cost and static power
dissipation, and usually results in increased throughput as well because the
routing is easier.

Martin Euredjian wrote:

> I think that, in general, it is more efficient to run FPGA's as fast as
> they'll go and serialize a solution as opposed to creating huge wide
> parallel paths that eat-up a lot of logic while running well below the
> attainable clock rates on some of these devices.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 59414
Subject: "sniffing" signals
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Tue, 19 Aug 2003 10:16:47 +1000
Links: << >>  << T >>  << A >>
Hi folks,

In Xilinx FPGA editor it is possible to assign probes to signals - a 
very useful feature.  However as far as I'm aware it is only possible 
for probes to take a given signal and bring it out to an IOB.

I'm interested in a more general capability to take an arbitrary 
internal signal and bring it to the top level of a design without having 
to modify the original vhdl (which may not even bve available), where it 
would be available to other modules in the design.

For example, say I want to create a hardware core that monitors the 
internals of a microblaze system, e.g. I want to "listen" on the 
instruction fetch.  In FPGA editor I can determine the full signal names 
that are necessary - can I then somehow get those signals to my 
"sniffer" module and proceed like that?

Thanks,

John


Article: 59415
Subject: Re: "sniffing" signals
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Tue, 19 Aug 2003 00:19:45 GMT
Links: << >>  << T >>  << A >>
I think you can do that, however, you'd have to do something so that your
"sniffer" module doesn't get optimized out for not having any inputs.  I've
never done this, so I could be wrong.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"





"John Williams" <jwilliams@itee.uq.edu.au> wrote in message
news:bhrpmp$hda$1@bunyip.cc.uq.edu.au...
> Hi folks,
>
> In Xilinx FPGA editor it is possible to assign probes to signals - a
> very useful feature.  However as far as I'm aware it is only possible
> for probes to take a given signal and bring it out to an IOB.
>
> I'm interested in a more general capability to take an arbitrary
> internal signal and bring it to the top level of a design without having
> to modify the original vhdl (which may not even bve available), where it
> would be available to other modules in the design.
>
> For example, say I want to create a hardware core that monitors the
> internals of a microblaze system, e.g. I want to "listen" on the
> instruction fetch.  In FPGA editor I can determine the full signal names
> that are necessary - can I then somehow get those signals to my
> "sniffer" module and proceed like that?
>
> Thanks,
>
> John
>



Article: 59416
Subject: Re: Old Xilinx FPGAs
From: Ray Andraka <ray@andraka.com>
Date: Mon, 18 Aug 2003 20:24:12 -0400
Links: << >>  << T >>  << A >>
Add to the list:
    Cutting out half the LUT RAMs/SRL16s in SpartanIII
    Changes to the RLOC formats

Peter Alfke wrote:

> In Xilinx we have been pretty careful to always make the next generation
> a functional superset of the previous one.
> There are only a few exceptions:
> XC5200 and XC6200 are orphans.
> The Xtal oscillator-inverter was discontinued after XC3000.
> There were some "wide-edge decoders" in early XC4000.
> And of course the pin-outs and the packages and supply voltages changed.
> Other than that there should be no problem for "Project Nostalgia".
> Staying with Xilinx might be less troublesome than switching to Stratix.
>  :-)
>
> Peter Alfke, Xilinx Applications
> =================================
>
> Symon wrote:
> >
> > If you're that nostalgic, I wonder if you could use a modern FPGA to
> > emulate an old one? You see old arcade games emulated, I guess there's
> > no reason you couldn't code an XC2018 in HDL and implement it in a
> > Stratix if you're mad/sad enough! Sort of a Meta-FPGA.
> > I just searched, someone's already done something similar!
> > http://ce.et.tudelft.nl/~reinoud/mpga/README.html
> >         cheers, Syms.
> >
> > Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F3BAA07.462EBCB3@xilinx.com>...
> > > Jeff,
> > >
> > > For these ancient devices (see Peter's threads regarding the aging rate of FPGAs),
> > > there are archived versions of software, but it also takes a computer system that is
> > > compatible (ie DOS, Windows 3.0, etc).
> > >
> > > By submitting a hotline case online, you will be able to get a response for what
> > > devices are upward (or downward) bitstream compatible (not all are).
> > >
> > > The early software also used the early hardware keys (dongles), so that is also
> > > something that is needed....(if anyone offers you some old software -- get the old key
> > > too!).
> > >
> > > Not something that would interest me in spending time on, as you could probably pick up
> > > surplus grey market models of much more recent devices that are supported by the free
> > > Webpack software.
> > >
> > > But, if you are nostalgic.....I hear that folks have FPGA versions of PDP-8
> > > computers....and cross compilers for IBM 1130's that run on PC's.....strange
> > > hobbies....but some folks collect stamps, so I suppose I can't really understand any of
> > > it.
> > >
> > > Austin
> > >
> > > Jeff Sampson wrote:
> > >
> > > > [Please pardon an intrusion from a really casual FPGA/CPLD user]
> > > >
> > > > I have a collection of old Xilinx parts. XC2018, XC3020, XC3030, XC3064,
> > > > XC4004A. I gave up years ago trying to find software for the XC2018 parts. But I
> > > > assumed my software would do the XC30xx and XC40xx when I got around to using
> > > > them. Now I notice that the Xilinx web page doesn't have spec sheets for the
> > > > base XC30xx and XC40xx or XC40xxA parts. I also notice that me oldest software,
> > > > Foundation Base 1.4 is too new to include these parts. (after casual browsing
> > > > through Foundation Base 1.4, WebPack 4.2, WebPack 5.1i, Student 2.1i)
> > > >
> > > > So, my question is, am I missing someting? Or do I just need older software?
> > > >
> > > > Can I use XC3030A to create code for a XC3030? I'm guessing that I can't.
> > > >
> > > > What about the XC4004A? Can I use XC4003E or XC4003XL to create code for the
> > > > XC4004A? I'm guessing not.
> > > >
> > > > If I need older software, does anyone have any old software they want to part with?
> > > >
> > > > I'm guessing old software falls into 3 catagories:
> > > >
> > > >    1. Better keep it in case we have to update this old stuff.
> > > >    2. It is still here on the shelf because I couldn't bear to throw it away.
> > > >    3. Threw it away years ago.
> > > >
> > > > Or should I just throw these old parts away and get some Spartan ot Virtex parts?
> > > >
> > > > --
> > > > Jeff Sampson
> > > > http://tcrobots.org/members/jsamp.htm

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 59417
Subject: Re: DDFS question
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Tue, 19 Aug 2003 10:24:23 +1000
Links: << >>  << T >>  << A >>
John_H wrote:

> You've got it right.
> 
> You could control any divider to switch between a divide by n or n+1 to
> achieve a frequency between F/n and F/(n+1).  You get the simple case where
> the control is a square wave.  If it wasn't a square wave, how would you
> control the fraction?  With an accumulator.  Just like the standard DDFS.
 >
> DDFS (DDS to some) gives you flexibility that you don't get with an
> implementation for a specific frequency divider.
> 
> The jitter will be about 77 ns with either approach but - at 16kHz - what
> does it really matter?

The jitter generated by this particular divider is actually 38ns, which 
is *half* of one period of the input clock.  77ns (one period) is the 
upper limit for an arbitrary frequency division, but often the jitter is 
much less.

It's time to plug my free fractional-N divider generator at 
http://fractional-divider.tripod.com/

It will generate VHDL and Verilog for this exact application.

> If you have a higher frequency clock available, you could get better jitter
> characteristics.  If you can divide your clock into multiple phases, you can
> get better jitter characteristics.

This is an excellent idea.

Regards,
Allan.


Article: 59418
Subject: Re: Problem with Modelsim Lisence server...
From: pra_verilog@yahoo.com (Prasanna)
Date: 18 Aug 2003 17:35:07 -0700
Links: << >>  << T >>  << A >>
deb_astro@yahoo.co.in (Debashish) wrote in message news:<fe977b7a.0308172249.673167c6@posting.google.com>...
> Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3F3D0668.3080103@flukenetworks.com>...
> > Debashish wrote:
> > 
> > > Here i have a problem with my Modelsim lisence server.I have 2
> > > lisences for modelsim in my office. But many a times if someone dont
> > > close the modelsim properly or dont release the lisence (by command
> > > quit -sim), lisence stays active even if he is not working.So most of
> > > the time i am not able to use 2 linces. So being a Windows 2000 server
> > > we had to restart it again and agian atleast once everyday, two kill
> > > those process and regain the 2 lisences.
> > 
> > 1. Learn the lmstat command to find out who is holding licenses,
> >     and train them to close the gui.
> > 
> > 2. Learn to use command line execution: vcom -c and vsim -c.
> >     vcom (command line) does not require a license. Bringing up
> >     the gui with vsim.exe holds a licenses for the whole
> >     session, even if you are just editing and compiling.
> > 
> >     Running a text testbench with vsim -c only holds the license
> >     during a sim and then relinquishes it.
> > 
> > 
> >       -- Mike Treseler
> 
> 
> Thank you Mike i have downloaded the FLEXLM enduser guide.This solved
> all my problems.I am using lmstat -a and lmremove

Hi,

Use "lmremove" command with the license admin privileges. To recognize
that the process is dead, there are unix ways and I am not aware of
windows ways.

I suggest wrap your modelsim command with a shell script that takes
care of these issues.

Regards,

- Prasanna

Article: 59419
Subject: Re: VHDL for FPGA VME Slave
From: Tullio Grassi <tullio@Glue.umd.edu>
Date: Mon, 18 Aug 2003 21:03:58 -0400
Links: << >>  << T >>  << A >>
Have a look to :

http://schwick.home.cern.ch/schwick/muctpi/FPGAdocu/LIB/VMELIB/index-long.html

It seem a well organized job (not mine).



On Fri, 15 Aug 2003, Colin Jackson wrote:

> I'm working on a FPGA that is to have a few R/W registers on a VME bus.
>
> Anybody have some VHDL code they would like to share?
>
> If I use your ideas then your name will forever be in lights!
>
> Thanks!
>
>
>


Article: 59420
Subject: determine clock cycles (wait states) in interface to user logic in NIOS.
From: jwing23@hotmail.com (J-Wing)
Date: 18 Aug 2003 18:39:45 -0700
Links: << >>  << T >>  << A >>
How can one determine the clock cycles needed for the wait state in
the interface to user logic in sopc builder? Is there any specific
method to test the hardware for the wait state? what does the setup
and hold state mean?
Please advice.

Article: 59421
Subject: Re: ALTERA Byte BlasterII <--Link Inside
From: anyone@anywhere.com
Date: Tue, 19 Aug 2003 02:14:45 GMT
Links: << >>  << T >>  << A >>
http://www.altera.com/literature/an/an088.pdf

On Wed, 30 Jul 2003 18:32:27 +0200, "Lev Razamat"
<lrazamat@vyyo.co.il> wrote:

>If anybody have a chematic of the ALTERA Byte Blaster II. Or if anybody can
>send me link to this schematic
>
>Thanks in advance
>
>Lev
>


Article: 59422
Subject: Re: Anyone familiar with ispXPLD?
From: "Jay" <yuhaiwen@hotmail.com>
Date: Tue, 19 Aug 2003 10:32:33 +0800
Links: << >>  << T >>  << A >>
Hi Paul,

Thanks.
It seems XPLD is something like the XPGA, which is also based on SRAM and
EECMOS.

Jay
"Paul Sereno" <paul_sereno@hotmail.com>
??????:3d7510b4.0308181129.2ce2f33f@posting.google.com...
> Jay,
>
> Basically, the XPLD is a CPLD with the option of using the MFB (former
> GLB) as memory (Dual Port RAM, Single Port RAM, FIFO, CAM, etc). This
> is due to the fact that the logic is actually implemented in SRAM
> cells (like FPGAs). The part has the EE memory integrated in the same
> die. After programming the EE, the SRAM is configured in less than
> 200us (like almost any CPLD), what is called instant-on.
> Another good point is that the software is free from the Lattice
> website.
>
> Hope this helps,
>
> Paul
>
> "Jay" <yuhaiwen@hotmail.com> wrote in message
news:<bhesmv$sdl$1@ID-195883.news.uni-berlin.de>...
> > Hi all,
> >
> > I only have used xc9500 and coolrunnerII before, and we all know such
CPLDs
> > has so little FF resources.
> > For my current applications I need to map some memorys and I think
ispXPLD
> > is what I'm looking for.
> > But before I start my work on it, I'd like make something clear:
> > 1.It sounds great that ispXPLD has plennty of memory resources, and
that's
> > what I want most. So what's the payoff compared with common CPLDs, cost?
> > performance?
> > 2.ispXPLD has a new architecture MFB which I'm not familiar with. From a
> > designer's point of view, is there any difference between XPLD and CPLD?
Do
> > I need extra knowledges or skills?
> >
> > Thanks.



Article: 59423
Subject: Re: Never used FPGA board for sale
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 18 Aug 2003 23:40:22 -0400
Links: << >>  << T >>  << A >>
Martin Schoeberl wrote:
> 
> OK, I'll try it here: For sale:
> 
>     6 pcs Altera EP1K50TC144-3
>     7 pcs Altera MAX7032AETC44-10
>     ca. 130 pcs async RAM 128kBx8
>     ca. 15 boards with ACEX 1K50 + 128 kB RAM + 512 kB Flash + MAX for
> config from Flash

I might be interested in one or two of the ACEX boards.  Is there any
way to connect this board to external signals?  In particular I would
want to interface it to an ARM IO bus and a PC/104 (ISA) bus.  This
would be a nice test jig for some FPGA code I am doing.  It might help
me save a board spin on my board.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 59424
Subject: Async logic in FPGAs
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 19 Aug 2003 00:17:58 -0400
Links: << >>  << T >>  << A >>
After reading a post by Jonathan Bromley on the VME interface, I thought
I would see if anyone had any comments on a design I am doing.  I have
to interface to the PC104 bus which is just the PC ISA interface on a
small board.  After beating my head against the wall for a couple of
trys, I decided to dump the BCLK since it is not really part of the spec
and treat the command stobes as async lines.  My design is further
complicated by the fact that my system clock ranges from 2 MHz to 50 MHz
to allow power conservation.  

I finally decided that the only way to get the job done was to treat the
command strobes as clock lines.  Read cycles are done normally by muxing
the data from various registers based on the address lines and the
tristate outputs are controlled with the strobes.  Writes to simple
registers are done on the trailing edge of the write strobe.  For reads
that need to update or clear bits, a strobe is generated that is sync'ed
to the system clock using a circuit to remove the metastable problem.
The same circuit works with writes that need to set flags or control
FIFOs.  

I don't see any problem with any of the circuits I have used.  I don't
even see the need to use a clock tree for the command strobes since
there are no race conditions where a few ns will matter.  Unless there
are *huge* differences in routing delays, this circuit should work just
fine.  

Anyone had big problems with similar async circuits?  BTW, here is the
simple sync circuit to generate a single pulse in the target clock
domain regardless of the relative speed of the clocks. 

   |------- Metastable -------|         
            __________
           |          |                        _____
   |------O| inverter |-------|---------------|     | Pulse
   |       |__________|       |               | XOR |---->
   |    ______       ______   |   ______   |--|_____| Out
   |   |      |     |      |  |  |      |  |
   |---| D  Q |-----| D  Q |--|--| D  Q |--|
Strobe |      |     |      |     |      |
/Clock |      |     |      |     |      |
-------|>     |  ---|>     | |---|>     |
       |______|  |  |______| |   |______|
                 |           |
                 |___________|___________  Output Clock

The pulse out should be clean by the next clock edge as long as the
routing is kept short.  Or if the clock period is very short another FF
can be added to feed the other leg of the XOR gate and assure a clean
output. 

If the input clock is faster than the output clock, extra clock edges on
the input will be ignored until the signal has clocked through the other
clock domain.  

You can also tap the second FF for the feedback if you want to use it
for a handshake.  A second FF on the input side and an XOR gate will
give you a pulse on "acknowledge" of the pulse crossing the clock
domain. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX



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