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Messages from 59600

Article: 59600
Subject: Re: Thinking out loud about metastability
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 23 Aug 2003 11:47:15 -0400
Links: << >>  << T >>  << A >>
Jon Elson wrote:
> 
> rickman wrote:
> 
> >I am designing a FPGA interface for an MCU which uses only async
> >strobes.  However they are not truely async, in reality the timing to
> >the clock is simply not spec'd.  So if I understand metastability
> >correctly, I can not use the standard circuit to reduce the failure rate
> >to insignificant rates.  Since there is a fixed relationship between the
> >clock and the command strobes (even though it is unknown) no matter how
> >I choose to clock the circuit, I may end up balancing the pencil well
> >enough on end that I will see a much higher failure rate than predicted
> >by the standard formula.
> >
> >
> I think you need to make some measurements, if you can't get info from
> the manufacturer.  Most likely, the timing will be pretty simple to figure
> out, as signals, especially strobes, will almost certainly either be clocked
> through a flip-flop right at the output, or have a minimum of gates between
> the last FF and the output.
> 
> You really CAN'T work with so little information.  What is the setup time
> of data and address signals from the CPU, relative to the strobes?  What is
> the required setup and hold time of data and addresses presented to the
> CPU from outside?
> 
> Or, do they provide all this in great detail, just never referencing any
> of this
> to the CPU clock?

Exactly.  I have found that although all MCUs and DSPs are synchronous,
unless they are interfacing to synchronous memory, they don't provide
info on timing in relation to the clock.  

> If you can't beat this information out of the manufacturer, then you
> should be
> able to measure it fairly easily.

I can't measure it for two reasons; one, the chips are not available
except as samples (no eval boards yet); two, even if I measure it, there
is no guarantee that the chips will not change since this is not a
spec'd parameter.  Processes are improved constantly and many aspects of
timing can change.  I don't want to design to an early chip only to find
that in six months they change.  

For now I am working with the assumption that if I provide enough
settling time, the timing of the signals will not matter.  The window of
failure is pretty small.  The more time allowed for settling, the
smaller the window.  I may expand the time to a full clock cycle (20ns -
5 ns routing) which should make the window way too small to hit with any
frequency.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 59601
Subject: Re: Thinking out loud about metastability
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Sat, 23 Aug 2003 16:01:31 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3F478C83.E7EA5466@yahoo.com>,
rickman  <spamgoeshere4@yahoo.com> wrote:
>> Or, do they provide all this in great detail, just never referencing any
>> of this
>> to the CPU clock?
>
>Exactly.  I have found that although all MCUs and DSPs are synchronous,
>unless they are interfacing to synchronous memory, they don't provide
>info on timing in relation to the clock.  

Silly question:  Does it ever CROSS the clock boundry, or is it always
before or always after?  Or is it always CLOSE, in which case you
could use the 180 out-of-phase clock to clock it in?
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 59602
Subject: Re: Altera ACEX 1K IOE
From: "Valeria Dal Monte" <aaa@bbb.it>
Date: Sat, 23 Aug 2003 17:16:30 GMT
Links: << >>  << T >>  << A >>

"rickman" <spamgoeshere4@yahoo.com> ha scritto nel messaggio
news:3F46D425.7C4FFE1B@yahoo.com...
>
> Is there really only one FF in the IOE so that it can be either input or
> output?  Is the OE FF always in an LE rather than the IOE?  Seems like
> this would make for some trouble getting the timing in tight
> situations.

Rick,
the I/O Element has really only one FF. The data sheet of Flex 10KE
(the older and more expensive version of the Acex serie, but functionally
identical) shows more honestly the real I/O Element structure.



Article: 59603
Subject: Re: Thinking out loud about metastability
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 23 Aug 2003 13:30:00 -0400
Links: << >>  << T >>  << A >>
"Nicholas C. Weaver" wrote:
> 
> In article <3F478C83.E7EA5466@yahoo.com>,
> rickman  <spamgoeshere4@yahoo.com> wrote:
> >> Or, do they provide all this in great detail, just never referencing any
> >> of this
> >> to the CPU clock?
> >
> >Exactly.  I have found that although all MCUs and DSPs are synchronous,
> >unless they are interfacing to synchronous memory, they don't provide
> >info on timing in relation to the clock.
> 
> Silly question:  Does it ever CROSS the clock boundry, or is it always
> before or always after?  Or is it always CLOSE, in which case you
> could use the 180 out-of-phase clock to clock it in?
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

I don't know, it is not spec'd and I don't have samples.  But even if I
had samples to test, if it is not spec'd, I would have no way of knowing
it won't change.  For now I am using the falling edge to clock it in and
the rising edge to reclock to allow for settling.  This gives me some 5
ns or more for settling.  

The problem is that if the chip changes (or even wanders over
temperature, voltage, phase of the moon) it could put me right smack in
the critical window to cause a failure.  But after hashing it around I
think this is still a very, very remote possibility given enough
settling time.  I don't know if 5 ns is enough, but certainly 10 ns is. 
I may consider using the same edge for clocking it in and the second
reg.  This would give me some 15 ns which certainly should be way more
than enough.  

Another result of them not specing the clock relationship is the async
nature of the WAIT input.  My circuit requires using this signal to make
sure the cycle ends after the data setup time.  Since there is no way of
knowing when the signal is sampled (and the fact that the setup time is
about the same as the clock period) I will not be able to design the
circuit to work in a fixed number of clock cycles.  I will be able to
define a max value, but not set it to a fixed number.  I guess this is
not a big issue, but I like to be able to do calulations on throughput
and the bus cycle will determine that.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 59604
Subject: Re: Altera ACEX 1K IOE
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 23 Aug 2003 13:41:39 -0400
Links: << >>  << T >>  << A >>
Valeria Dal Monte wrote:
> 
> "rickman" <spamgoeshere4@yahoo.com> ha scritto nel messaggio
> news:3F46D425.7C4FFE1B@yahoo.com...
> >
> > Is there really only one FF in the IOE so that it can be either input or
> > output?  Is the OE FF always in an LE rather than the IOE?  Seems like
> > this would make for some trouble getting the timing in tight
> > situations.
> 
> Rick,
> the I/O Element has really only one FF. The data sheet of Flex 10KE
> (the older and more expensive version of the Acex serie, but functionally
> identical) shows more honestly the real I/O Element structure.

Thanks for the info, but my copy of the 10KE data sheet shows the same
text and illustration as the 1K sheet.  But I think I get the point.  I
would like to use the register in the IOE if the software will let me. 
I guess that is what I will need to figure out.  I think for the pins
where I want the registered and non-registered inputs, I will have to
use an LE register.  It does not look like the IOE lets you bring in
both. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 59605
Subject: Re: Signal within block
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Sat, 23 Aug 2003 10:47:25 -0700
Links: << >>  << T >>  << A >>
Isaac wrote:

> I am using 12 same entitites using Component decleration method. 

Perhaps you mean a top architecture with 12 instances of some entity.

> I am
> giving input to 12 entities in such a way that the internal signal's
> in each entity has different values from each other at any time. Now
> the top vhdl final in which all the component decleration are defined
> , I want to use the internal signal's of each block to perform some
> calculation. The probelm is that in each of the 12 entities signal has
> the same name (as I am using component decleration method to generate
> same entity 12 time).

Each instance has a unique label:

    my_entity_1 : entity work.my_entity
       port map (reset  => reset_sig,  -- [in]
                 clk    => clk_sig,    -- [in]
                 i      => i_1_sig,    -- [in]
                 o      => o_1_sig);   -- [out]

    my_entity_12 : entity work.my_entity
       port map (reset  => reset_sig,  -- [in]
                 clk    => clk_sig,    -- [in]
                 i      => i_12_sig,   -- [in]
                 o      => o_12_sig);  -- [out]

The signal associated with an instance port is whatever
you define it to be in the port map.
I think of this as "wiring up" the instances.
These "wire" signals must be declared between
the IS and BEGIN of the top architecture.
It can be a different signal for each instance if you like.

 > Is there is any way to access these Signal in VHDL?

These signals are accessible anywhere in the top architecture.

  -- Mike Treseler




Article: 59606
Subject: Re: Thinking out loud about metastability
From: Jon Elson <elson@pico-systems.com>
Date: Sat, 23 Aug 2003 14:32:07 -0500
Links: << >>  << T >>  << A >>


rickman wrote:

>"Nicholas C. Weaver" wrote:
>  
>
>>In article <3F478C83.E7EA5466@yahoo.com>,
>>rickman  <spamgoeshere4@yahoo.com> wrote:
>>    
>>
>>>>Or, do they provide all this in great detail, just never referencing any
>>>>of this
>>>>to the CPU clock?
>>>>        
>>>>
>>>Exactly.  I have found that although all MCUs and DSPs are synchronous,
>>>unless they are interfacing to synchronous memory, they don't provide
>>>info on timing in relation to the clock.
>>>      
>>>
>>Silly question:  Does it ever CROSS the clock boundry, or is it always
>>before or always after?  Or is it always CLOSE, in which case you
>>could use the 180 out-of-phase clock to clock it in?
>>--
>>Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
>>    
>>
>
>I don't know, it is not spec'd and I don't have samples.  But even if I
>had samples to test, if it is not spec'd, I would have no way of knowing
>it won't change.  For now I am using the falling edge to clock it in and
>the rising edge to reclock to allow for settling.  This gives me some 5
>ns or more for settling.  
>  
>
This is insane!  What imbecile wrote the data sheets?  Is it impossible that
someone would ever want to build a synchronous memory controller or
other peripheral for this MCU?  Can you get hold of someone at the
manufacturer to help you with this?  I've never run into this problem, where
the timing of the strobes, etc. was so vague.  Is this chip real, or is it
vaporware, where the only physical reality is a piece of paper?

Jon


Article: 59607
Subject: What is the context switching time
From: Kuan Zhou <zhouk@rpi.edu>
Date: Sat, 23 Aug 2003 16:00:15 -0400
Links: << >>  << T >>  << A >>
Hi,
   I am wondering how fast can the Virtex does the context switch.
I heard it's slow because the CMOS response very slowly. Is it true?

  Thank you very much!


sincerely
-------------
Kuan Zhou
ECSE department



Article: 59608
Subject: Re: Some questions about Xilinx ISE
From: Christian Schneider <cgs-news@cgschneider.com>
Date: Sat, 23 Aug 2003 23:35:29 +0200
Links: << >>  << T >>  << A >>
Aman Gayasen wrote:
> Hi,
>  I am using Xilinx ISE (Synthesis using XST VHDL) to implement my
> design on a Virtex2 FPGA.
>  I have the following questions.
> 
> a) Is there a way to constrain ISE to place a "process" in a VHDL
> design, to a particular region on the FPGA? COnstraints guide says that
> AREA_GROUP is applicable to logic blocks. Can I make a VHDL "process" a logic
> block? I understand that this may not be a very efficient thing to do (in
> terms of area optimization), but can this be done (area is not a big
> constraint for my design)?

AREA_GROUPS are used for whole modules, e.g. a VHDL entity. Well, you 
can place a single process in an entity or module.

> b) The constraints guide says that AREA_GROUP affects routing too. How
> does it affect routing?

Since you limit the placement, the routing will also be affected ...

> c) Some modules of my design are in EDIF format, using a different
> target library than Synopsys or Xilinx. How do I go about adding them
> into my design? This must be a pretty common problem. The Development
> System Reference guide says that we need to include definition of all
> macros. I am not sure how to do this. It will help if you could point
> me to some reference that describes this.

Simply put all edf-files in the same directory: The top level and the 
modules.

> Your help will be deeply appreciated.
> 
> Thanks,
> Aman

BR Chris


Article: 59609
Subject: Altera RBF format CRC
From: "crj" <mail@deeptrace.com>
Date: Sun, 24 Aug 2003 12:33:21 GMT
Links: << >>  << T >>  << A >>
Does anyone know how to calculate the CRC for the frames in the Altera RBF
format?  I want to be able to change the logic in specific portions of the
chip by changing the download file, and I don't want to have to recompile to
change the initial contents of some internal ROMs.

Thanks

Chris



Article: 59610
Subject: Re: Thinking out loud about metastability
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 24 Aug 2003 08:36:24 -0400
Links: << >>  << T >>  << A >>
Jon Elson wrote:
> 
> rickman wrote:
> >I don't know, it is not spec'd and I don't have samples.  But even if I
> >had samples to test, if it is not spec'd, I would have no way of knowing
> >it won't change.  For now I am using the falling edge to clock it in and
> >the rising edge to reclock to allow for settling.  This gives me some 5
> >ns or more for settling.
> >
> >
> This is insane!  What imbecile wrote the data sheets?  Is it impossible that
> someone would ever want to build a synchronous memory controller or
> other peripheral for this MCU?  Can you get hold of someone at the
> manufacturer to help you with this?  I've never run into this problem, where
> the timing of the strobes, etc. was so vague.  Is this chip real, or is it
> vaporware, where the only physical reality is a piece of paper?
> 
> Jon

I don't think this is uncommon.  In fact, I believe most devices that
use an async interface to memory don't spec timing to the CPU clock. 
This chip does have an SDRAM interface, but they provide separate
control strobes and clock.  

As to reaching support at the manufacturer, I have had no luck
contacting them directly.  I have to go through my local sales rep (who
is an engineer, not just another pretty face).  But this makes it even
harder to get a question and answer communicated than going through the
entry level people they have manning most support lines.  I got one
email that had been handled by some 4 or 5 people in each direction.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 59611
(removed)


Article: 59612
Subject: Interfacing to pc parallel port?
From: "michele bergo" <michelebergo@libero.it>
Date: Sun, 24 Aug 2003 18:33:25 GMT
Links: << >>  << T >>  << A >>
I want to interface altera cyclone(3.3V) to the pc parallel port(5V). Is it
possible without using further external devices?

Thanks




Article: 59613
Subject: Re: Question about slew rate for SpartanII using ISE5.1
From: stephen@postec.co.nz (Stephen du Toit)
Date: 24 Aug 2003 13:30:34 -0700
Links: << >>  << T >>  << A >>
Hi guys,

Thanks very much for your help, but I am still stuck.

I do indeed manage to get the string : NET "pad_name" FAST; into the
UCF by using the constraints editor. I also tried another syntax,
namely: NET "pad_name" slew = FAST; by editing the .UCF directly.

My UCF is definitely processed, because it obeys the constraint of
making the IO standard = PC133_5 and also the pin allocation. In the
pad report though, the pin is still shown as "slow" and I confirmed
that by measurement - about 40 nS rise and fall times.

Is there a chance that, if I specify PC133_5 as an IO standard, that I
am stuck with the slow option?

Thanks very much for trying to help me.

Stephen
  
"John_H" <johnhandwork@mail.com> wrote in message news:<F_q1b.54$AH1.7501@news-west.eli.net>...
> Comments inline, additional at the end.
> 
> "Jacques athow" <jaxlau@yahoo.com> wrote in message
> news:acc717b2.0308220345.6d058151@posting.google.com...
> > Isnt the proper way to do this...
> 
> Sure it is, there's just more than one way to do it.  Your way is valid for
> the FPGAs but not the CPLDs.
> The original poster's method of "NET yadayada FAST;" should work as should
> "INST yada_obuf FAST;" both of which I use withouth problem.
> 
> > ---- 
> > # SLEW sets the speed of an IOB output rise/fall time.
> >
> > NET mysignal slew=FAST;
> >
> > # Legal values: FAST, SLOW.
> > # FPGA Families: All.
> 
> # CPLD Families:  None.
> 
> > # Applies to output and I/O pads or the net connected to an output pad
> > ---
> >
> > The pad report indeed says that I have a fast slew rate on the pad ive
> > designated to have the fast slew rate attribute.
> >
> >
> > alternatively you could use the constrain editor to edit your ucf file
> > and add, with the advance option, the required constrain that you
> > want, in this case the fast slew rate. Both gives you the same end
> > result.
> >
> > jacques.
> >
> > stephen@postec.co.nz (Stephen du Toit) wrote in message
>  news:<798f0979.0308211905.d2b451@posting.google.com>...
> > > Hi,
> > >
> > > If someone can help me with this, I'll be very happy.
> > >
> > > I would like to change the slew rate of some of my output pins of a
> > > SpartanII to "FAST". Tried to put it in the UCF file, it obeys all the
> > > other constraints that I put in there, but not the "FAST" one. The
> > > syntax used was
> > > NET "c" FAST;
> > >
> > > I also declared some stuff in my VHDL source as follows:
> > > attribute FAST : string;
> > > attribute FAST of c : signal is "true";
> > >
> > > I looked at the properties of the Place-and-route but cannot find
> > > anywhere where the option has to be enabled.
> > >
> > > The software is happy with all of this, but the PAD report still says
> > > that pin c is "SLOW".
> > >
> > > Thanks very much.
> > >
> > > Stephen du Toit
> > >
> > >
> > > I tried
> 
> Did you set the IOSTANDARD for those signals?  The propagation rules and
> applicable elements are the same for those two attributes.  I'm wondering if
> the net name ended up being something different by the time it got to the
> pad, making the propagation rules inapplicable.
> 
> If you can see the net names in FPGA Editor but your IOBs are still SLOW,
> try using the INST format on the OBUF, OBUFT, IOBUF, or IOBUFT primitives
> that were generated by your VHDL code.
> 
> If all the other constraints are showing up properly, is there somewhere you
> have a SLOW that might inadvertantly be overriding the constraint?  If the
> timing constraints are succussful, the checkbox for "Ignore Timing
> Constraints" in the GUI probably isn't checked so that shouldn't be a
> problem either.
> 
> I hope you find what's going on!

Article: 59614
Subject: Re: Question about slew rate for SpartanII using ISE5.1
From: stephen@postec.co.nz (Stephen du Toit)
Date: 24 Aug 2003 15:50:41 -0700
Links: << >>  << T >>  << A >>
Problem sorted - got hold of the SpartanII hardware manual. The slew
rate can only be set for LVTTL output buffers, I used PCI33_5, so it
ignored my requests.

Thanks

Stephen
 
"John_H" <johnhandwork@mail.com> wrote in message news:<F_q1b.54$AH1.7501@news-west.eli.net>...
> Comments inline, additional at the end.
> 
> "Jacques athow" <jaxlau@yahoo.com> wrote in message
> news:acc717b2.0308220345.6d058151@posting.google.com...
> > Isnt the proper way to do this...
> 
> Sure it is, there's just more than one way to do it.  Your way is valid for
> the FPGAs but not the CPLDs.
> The original poster's method of "NET yadayada FAST;" should work as should
> "INST yada_obuf FAST;" both of which I use withouth problem.
> 
> > ---- 
> > # SLEW sets the speed of an IOB output rise/fall time.
> >
> > NET mysignal slew=FAST;
> >
> > # Legal values: FAST, SLOW.
> > # FPGA Families: All.
> 
> # CPLD Families:  None.
> 
> > # Applies to output and I/O pads or the net connected to an output pad
> > ---
> >
> > The pad report indeed says that I have a fast slew rate on the pad ive
> > designated to have the fast slew rate attribute.
> >
> >
> > alternatively you could use the constrain editor to edit your ucf file
> > and add, with the advance option, the required constrain that you
> > want, in this case the fast slew rate. Both gives you the same end
> > result.
> >
> > jacques.
> >
> > stephen@postec.co.nz (Stephen du Toit) wrote in message
>  news:<798f0979.0308211905.d2b451@posting.google.com>...
> > > Hi,
> > >
> > > If someone can help me with this, I'll be very happy.
> > >
> > > I would like to change the slew rate of some of my output pins of a
> > > SpartanII to "FAST". Tried to put it in the UCF file, it obeys all the
> > > other constraints that I put in there, but not the "FAST" one. The
> > > syntax used was
> > > NET "c" FAST;
> > >
> > > I also declared some stuff in my VHDL source as follows:
> > > attribute FAST : string;
> > > attribute FAST of c : signal is "true";
> > >
> > > I looked at the properties of the Place-and-route but cannot find
> > > anywhere where the option has to be enabled.
> > >
> > > The software is happy with all of this, but the PAD report still says
> > > that pin c is "SLOW".
> > >
> > > Thanks very much.
> > >
> > > Stephen du Toit
> > >
> > >
> > > I tried
> 
> Did you set the IOSTANDARD for those signals?  The propagation rules and
> applicable elements are the same for those two attributes.  I'm wondering if
> the net name ended up being something different by the time it got to the
> pad, making the propagation rules inapplicable.
> 
> If you can see the net names in FPGA Editor but your IOBs are still SLOW,
> try using the INST format on the OBUF, OBUFT, IOBUF, or IOBUFT primitives
> that were generated by your VHDL code.
> 
> If all the other constraints are showing up properly, is there somewhere you
> have a SLOW that might inadvertantly be overriding the constraint?  If the
> timing constraints are succussful, the checkbox for "Ignore Timing
> Constraints" in the GUI probably isn't checked so that shouldn't be a
> problem either.
> 
> I hope you find what's going on!

Article: 59615
Subject: TIG Constraint
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Mon, 25 Aug 2003 00:31:38 GMT
Links: << >>  << T >>  << A >>
The constraint guide indicates that the TIG constraint can be used in HDL
(Verilog in my current design).  However, an attempt to use it produces the
following error:

ERROR:Xst:1582 - The constraint 'tig=' is not supported neither in BEGIN
MODEL/END section in the XCF file, nor in HDL code.

I have not been able to find further information on this error message or
issue in the Xilinx site.  Does anyone know if TIG is truly supported in
HDL?  I'd hate to place it in the UCF file, to me it feels much more
approprite to have this constraint move with the HDL source.

The form I'm using is:

// synthesis attribute TIG of <net_name> is "";

As a point of interest, the nets in question are the output of the registers
of a microprocessor interface.  The values are only sampled a few times per
second by the receiving module.  There is not need to have any of these nets
meet nanosecond level timing constraints as other parts of the design must.
Is there a better approach than "TIG"?

Thanks,


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 59616
Subject: [ann] Microblaze uClinux Demo released
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 25 Aug 2003 10:49:24 +1000
Links: << >>  << T >>  << A >>
Microblaze uClinux Demo Package Released
----------------------------------------

We are pleased to announce the first public release of the Microblaze 
uClinux demo package, available for download from the project web site:

http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux

We have ported the uClinux operating system to the Microblaze soft 
processor core, developed by Xilinx for their FPGA family.  The demo 
provides an easy-to-use package that demonstrates the progress and 
potential of uClinux running on Microblaze.  The uClinux kernel is 
released under the GNU GPL.

The package contains an operating system image, FPGA bitstreams and 
scripts to get everything working.  Currently, the Insight/Memec 
V2MB1000 prototyping boards are supported.  If you have a different 
board, contact us and we may be able to help you port the hardware to 
your platform.

If you have any problems downloading or using the demo, please send an 
email to jwilliams@itee.uq.edu.au with the subject "uclinux demo".

Regards,

John Williams
-- 
Dr John Williams, Research Fellow,
Reconfigurable Computing, School of ITEE
University of Queensland, Brisbane, Australia
Ph : 61-7-3365-8305


Article: 59617
Subject: Problem configuring Cyclone
From: matt@ettus.com (Matt Ettus)
Date: 24 Aug 2003 18:14:36 -0700
Links: << >>  << T >>  << A >>
I am trying to configure a Cyclone EP1C12 using a microprocessor. 
Basically, I pull nConfig high, and wait for nStatus to go high. Once
it does, I start loading data.  When it is done, I never get CONF_DONE
going to high indicate success.  Also, I never get nStatus going low
again to indicate failure either.

I've tried clocking in millions of zeros after my bitstream, but that
doesn't change anything.

Any ideas?

Thanks
Matt

Article: 59618
Subject: Reusing CCLK line after configuration for Spartan-II
From: pablobleyer@hotmail.com (Pablo Bleyer Kocik)
Date: 24 Aug 2003 23:12:36 -0700
Links: << >>  << T >>  << A >>
Hello.

 I know this has been asked several times before but I am struggling
to get this straight and I still don't find a definite answer.

 I have a Spartan-II device connected to a small 5V micro which does
the configuration process. I want to multiplex the same micro's pin
for CCLK generation during Spartan-II configuration and as a timer
output to another device after that. The CCLK signal is 5V -- I know
that during configuration this is ok since the Spartan-II has 5V
tolerant pins.

 Is it ok for me to do this? What happens to the CCLK pin in the
Spartan-II after DONE has gone high?

 Thank you in advance. Warmest regards.

-- Pablo Bleyer Kocik -- pbleyer at embedded dot cl --
"The paradox of learning a really new competence is this: that a
 student cannot at first really understand what he needs to learn,
 can only learn it by educating himself, and can only educate himself
 by beginning to do what he does not yet understand" -- Schön, 1987

Article: 59619
Subject: quetions about configure altera fpga(apex20k) using ppa scheme
From: anfm@ele.pku.edu.cn (pkuanfm)
Date: 25 Aug 2003 00:03:22 -0700
Links: << >>  << T >>  << A >>
hello,everyone,i am trying to configure apex20k200e-1x using ppa
scheme.i have read the altera databook an116.in figure 24 of page 42,i
learned that after sending the last byte ,the signal "conf_done" go
high. i want to know how much time after the nws go high,conf_done can
go high. it will result in some extra bytes being sent to apex20k if
the delay time is too long,   because i check the signal conf_done  to
judge whether the confige is complete.

Article: 59620
Subject: Which Adder?
From: nagaraj_c_s@yahoo.com (Nagaraj)
Date: 25 Aug 2003 00:29:19 -0700
Links: << >>  << T >>  << A >>
Hi all,
   I am using XST (ISE 5.1i sp3) for my logic synthesis. If I write a
piece of VHDL code as in " c <= a + b ", an N-bit adder will be
inferred (assuming a,b,c are N bits).
   As there are many types of adder algorithms/implementations
available (like Carry Look Ahead, Carry Save etc.), I want to know
which one does XST infer? Can I have a control over the type of adder
?

Regards,
Nagaraj

Article: 59621
Subject: Xilinx Webpack 5.2i tutorial
From: srisurya@yahoo.com (Srisurya Konduri)
Date: 25 Aug 2003 01:26:03 -0700
Links: << >>  << T >>  << A >>
Hi, 
I am using ISE webpack 5.2i, I recently downloaded from the web, I am
going through the in-depth tutorial. I am stuck at the point of
generating a core using the core generator. The manual says to open
COREGEN and go into basic elements and then counters but the counters
sub entry is not available. I would really appreciate if you could
help me out in telling me how to add these elements and from where.
Thanks

Article: 59622
Subject: parallel port and cyclone?
From: "michele bergo" <michelebergo@libero.it>
Date: Mon, 25 Aug 2003 08:47:11 GMT
Links: << >>  << T >>  << A >>
I want to interface altera cyclone(3.3V) to the pc parallel port(5V). Is it
possible without using further external devices?

Thanks





Article: 59623
Subject: Re: [ann] Microblaze uClinux Demo released
From: antti@case2000.com (Antti Lukats)
Date: 25 Aug 2003 02:42:52 -0700
Links: << >>  << T >>  << A >>
John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<biblqa$206$1@bunyip.cc.uq.edu.au>...
> Microblaze uClinux Demo Package Released
> ----------------------------------------
> 
> We are pleased to announce the first public release of the Microblaze 
> uClinux demo package, available for download from the project web site:
> 
> http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux

question: if I take the mbvanilla EDK project from your website and
recompile it for example for ML300 would it work with the supplied
linux bootimage? I mean if I keep all the peripherals the same
as in the vanilla design, or is the hardware in the supplied .bit
images from some other design?

antti lukats

Article: 59624
Subject: Re: Reusing CCLK line after configuration for Spartan-II
From: antti@case2000.com (Antti Lukats)
Date: 25 Aug 2003 02:48:09 -0700
Links: << >>  << T >>  << A >>
pablobleyer@hotmail.com (Pablo Bleyer Kocik) wrote in message news:<bb2f07d6.0308242212.6707fd90@posting.google.com>...
> Hello.
> 
>  I know this has been asked several times before but I am struggling
> to get this straight and I still don't find a definite answer.
> 
>  I have a Spartan-II device connected to a small 5V micro which does
> the configuration process. I want to multiplex the same micro's pin
> for CCLK generation during Spartan-II configuration and as a timer

ASFAIK CCLK is dedicated pin that can not be used are user IO at all.
if you need to use the same pin from micro as io to your user logic
in the fpga then you need to connect some regular io pin parallel
to cclk pin.

antti



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