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Master wrote: > "Giuseppe³" <miaooaim@inwind.it> wrote in message news:<bj9a6r$gfbou$1@ID-61213.news.uni-berlin.de>... > >>I don't sure to undestood your question but using the M0-M1-M2 pins is not >>the right way to do what you want? >> >>Regards >>Giuseppe >> >>"master" <ff@pla.it> ha scritto nel messaggio >>news:iMM5b.292163$Ny5.9019956@twister2.libero.it... >> >>>Someone knows like turn off the "pull up" that the family "spartan2" >>>connects for default to " tristate" placed inner lines in, from buffer " >>>Tbuf"? >>>I use "Xilinx ISE 4.1ģ" and language "vhdl". >>>thanks >>> >>> > > > excuse me for the little clear english. > I reformulate the question. > > I use tool ise 4,1ģ, family spartan2 and language vhdl . When I > synthetize a project that uses internal buffer tristate (tbuf), Pull > up component have been connected to buffer output for default. I would > want to disable this option and to put on the buffer output some pull > up or pull down to my choice. Does some environment variable or some > procedure exist in order to make that? > > thanks - I don't like to insert directly pull-up in VHDL source file, because pullups in the pads are technology dependant. But I put that in the UCF file by : ############################ ## PULL RESISTOR DESCRIPTION ############################ NET your_padname PULLUP ; NET your_padname PULLDOWN ; So, remove all pull-ups and pull-downs in your source file and add what you need in the UCF. Laurent Gauch www.amontec.com Your FPGA Design PartnerArticle: 60126
"John K." <INVALIDANTISPAM@aol.com> wrote in message news:bj9sb1$gc4bj$1@ID-50260.news.uni-berlin.de... > > Hello people, > > I am strictly a schematic user, please don't turn this thread > into a "but HDLs are really better!!". I know you don't want to hear this, but I'll try to give a reasoned arguement rather than a blanket statement. As fpgas get bigger and bigger, there is no doubt that most designers are using hdls rather than schematics (or sometimes a mixture). For big systems, there are few that are made using pure schematics. This means that tool designers will put far more effort into the HDL support for their tools than schematic support. I haven't tried doing schematic design for an fpga, so I can't comment directly, but I have heard complaints on this newsgroup about the quality of the schematic tools for some fpgas. It also means that if you are learning about fpgas, there is a lot to be said for looking at using HDLs - you are going to get better tool support, better online tutorials and introductions, and end up with a more useful skill. If you really want to use schematics, it may be that the best route is to do the design using your current schematic design software and then use edif netlists to import it into the fpga toolkit - I'm sure there are others in this group who could give you ideas there. > I'd like to get a new hobby, i.e. to design some (simple for > now, but then also complex) devices on a SpartanII 300E board. > The kind of devices I'd like to design range from TTL style at > the begin, till, someday, complete CPUs and simple multimedia > devices (e.g. graphic chips as seen in the '80s home computers). > > I downloaded and installed Webpack, but I've been very > disappointed. It looks totally HDL oriented to me.. maybe > I'm wrong, but I couldn't see there what I'm looking for. > > What I'm looking for (pardon the redundancy) is a simple > but yet powerful editor that will let me enter a schematic > (NAND gates, Flip-Flops, etc..); will also let me make new > devices from schematics (i.e. macros!); then *possibly* > simulate all of that; and then finally burn it into my > SpartanIIE chip, letting me also setup various features > of the FPGA (e.g. how to load the initial contents of > block RAM, etc..). > > I have some money to invest, eventually, if the software > is not free.. but I'd like to know all the options before. > > Please.. can anybody shed some light? I'm very confused > and lost.. > > Greets, > John >Article: 60127
"Alvin Andries" <Alvin_Andries@nowhere.agilent.com> wrote in message news:1062770360.212993@cswreg.cos.agilent.com... > Hi Ken, > > "Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote in message > news:bj9oe8$sjq$1@dennis.cc.strath.ac.uk... > > > > Hi folks, > > > > I have generated a DA filter in coregen with the following specs: > > > > Decimation by 2 > > 40 taps symmetric > > 18 bit coes (signed) > > 12 bit input > > 2 clock cycles per output > > > > The input <sampling> rate is 100MHz down to 50MHz. > > > > However, I want to clock it at 200MHz down to 100MHz to save area - hence > > the 2 clocks per output. > > > > I am targetting an xc2v3000fg676-5 and I am pretty sure this is achievable > > since the polyphases need only run at 100MHz - only the data demuxing > needs > > to run at 200MHz. > > > > Constraining the whole lot via the CLK signal to 5ns (200MHz) doesn't > work - > > gets to about 177MHz with 16 logic levels across what is clearly a carry > > chain (which needs only to run at 100MHz). > > > > Here is what I tried in the ucf to try and tell ISE 5.2.03i what to do: > > > > NET "CLK*" TNM_NET = "CLK"; > > TIMESPEC "TS_CLK" = PERIOD "CLK" 5 ns HIGH 50 %; > > NET "ND*" TNM_NET = "ND"; > > TIMESPEC "TS_CLK_ND" = FROM "CLK" TO "ND" "TS_CLK" * 2; > > > > This doesn't work though - the timing report still moans about a carry > chain > > failing the 5ns constraint even though it would meet the 10ns constraint > it > > should be tied to. I think the logic will work at these rates but it > would > > be nice to know for sure via correct contraints. > > > > So, can someone suggest some ucf details I can use to tell the tools what > to > > do please? Do I need to specify some internal signal rather than ND? > > > > Thaks for your time, > > > > Ken > > > > > > -- > > To reply by email, please remove the _MENOWANTSPAM from my email address. > > > > What you've described is known as a multi-cycle path (data updates only > every X clock cycles allowing for the operation to span multiple clock > cycles). > I don't remember the exact ucf syntax, but I think it's a generic device to > device constraint (the example in the Xilinx documentation is very good). > Please note that you may specify this time as "X * <clock_period_name>", > which allows your design to be easily scaled for different frequencies. > > Hope this helps, > Alvin. > > Thanks for the response Alvin. I am aware that I am trying to specify a multicycle path - I have used the syntax I posted above (which does have an X * BTW) in other similar situations and successfully specified a multicycle path - that was for VHDL that I wrote however and not for an edif generated by coregen. Cheers, KenArticle: 60128
SRL16's are fine for muxes that are relatively static. I wouldn't use them in
a barrel shift used for floating point normalize or denormalize though, as it
takes 16 clocks to change it. If you have that much time between samples and
are that concerned about area, you should be doing bit or digit serial logic.
As long as you are keeping the floating point reasonable, the barrel shifts are
not too bad. Reasonable means maybe 12-16 bits mantissa and a few bits of
exponent. In most cases, you don't need full IEEE floating point. Another
trick I use frequently is to do a series of operations treating the mantissa a
fixed point and renormalizing after the series instead of after each
operation. This saves quite a bit of area and latency that would otherwise be
needed for de/re-normalizing. Block floating point works well in situations
where the dynamic range within a block of data is small but you don't know
apriori what the scaling will be. This is often used in FFTs.
Glen Herrmannsfeldt wrote:
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3F579ECC.D5C92BF@andraka.com...
> > Actually, the xilinx structure can make a very efficient cross bar. One
> way is
> > to do a partial reconfiguration to switch the crossbar connections, in
> which
> > case it uses mostly just the routing resources, not CLBs. If partial
> > reconfiguration is not your cup of tea, you can make efficient 4:1 muxes
> using
> > SRL16's. These take 16 clocks to reroute, and require a simple loader
> which can
> > be shared among many bits, but they are compact and fast.
>
> A subject that comes up reasonably often is doing floating point arithmetic
> in FPGA's. For example, as a systolic array. The
> prenormalization/postnormalization for floating point add/subtract, using
> barrel shifters in CLB's are so big that it is just about impractical. I
> was considering the crossbar switch as an array of muxes, which would also
> be huge.
>
> I do believe that reconfiguration is too slow for floating point
> normalization, but maybe the SRL16's.
>
> There is something called block floating point (I have never used it) where
> you have a whole array that has one characteristic but different mantissa
> for each element. (Apparently very useful for some algorithms.) In that
> case, the 16 clocks to load the SRL16's might be fast enough for a whole
> array of numbers. Post normalization could still be a problem, though.
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60129
There is if you are also decimating or interpolating, otherwise I guess not.
Christos wrote:
> Hi Ray,
> Forgive me that I still haven't found any time to read about the CIC filter,
> but from the way you describe its operation it does not require less read
> and write operations from a simple implementation of a subtract and
> accumulate which I am testing at the moment. I still need the same read
> pointer and the same memory.
> My point is, is there an advantage with CIC that I don't see?
>
> Christos
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3F578C86.2D04C220@andraka.com...
> > Regardless which method is used, using a CIC limits the number of memory
> > transactions per sample to just two: a read and a write. The memory is
> used as
> > a delay queue, so the read pointer is N samples behind the write pointer.
> The
> > memory required for all those channels is pretty big, so DRAM would be the
> way
> > to go if you are using semiconductor memories. Since the addressing can
> easily
> > be made linear, you can simplify it by using page mode or burst accesses.
> This
> > should make it fast enough to multiplex many channels into one memory .
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60130BTW, the statement about 4 pins is not correct. I use 2 pins for transmission, but only 1 pin for reception (I have 2 transistors to create a differential input from the 10BASE-T RD+/RD- wires to the FPGA). "Jean Nicolle" <j.nicolle@sbcglobal.net> wrote in message news:XuX5b.5$Y15.5657658@newssvr13.news.prodigy.com... > I managed to transmit and receive traffic on a 10BASE-T network using some > simple Verilog code and 4 pins of an FPGA connected almost directly to the > wires. > > Most microcontrollers require an external Ethernet MAC, but it seems that we > can do without if we limit ourselves to IP/UDP. > I think that there are potentially plenty of interesting applications. > > The project is working well already, so I documented a good chunk of it. > http://www.fpga4fun.com/10BASE-T.html > > Comments are welcome! > Jean > >Article: 60131
Gerald Weile <GWE@msc-ge.com> wrote in message news:<bj9n6g$gef09$1@ID-18746.news.uni-berlin.de>... > Hello, > > is there any way to create a PROM programming file that contains > not only Xilinx BIT files but also a Lattice BIT file ? yes sure from a company called Xilice :) NO the answer is NO. if you need several bitstream in one PROM file then you need to write your own tool todo this. hmm you did ask for Parallel PROM and doing download by some micro? or do you want one serial PROM to hold bitsrtreams for multiply vendor FPGAs? if you want to use singel serial config prom for Xilinx and Lattice this maybe a bigger problem, multi chip promfiles are of course possible but how it works if there are fpgas from different vendors I dont know. might be possible, but then its even more problems with bitstreams I would guess. one thing though Xilinx SYSACE configuration solution is capable to play back SVF files, so it may be possible to have a mixed chain of xilinx and lattice using sysace, unfortunatly the backstage of sysace file generation and SVF usage are not docemented ASFAIK anttiArticle: 60132
> I use tool ise 4,1ģ, family spartan2 and language vhdl . When I > synthetize a project that uses internal buffer tristate (tbuf), Pull > up component have been connected to buffer output for default. I would > want to disable this option and to put on the buffer output some pull > up or pull down to my choice. Does some environment variable or some > procedure exist in order to make that? > > thanks Hi, In Spartan-IIe Pull-up resistor on internal Tri-state net is unavoidable as by documentation. It should be the same in Spartan-II. Please correct me if it is wrong or not the same. AndreyArticle: 60133
Aart van Beuzekom <aart@westcontrol.com> wrote in message news:<3F584F36.2B55FA1E@westcontrol.com>... > Hei, > > When using the Xilins HDL bencher, the memory usage is running up to > 1GB. I understood this is a known problem and it is suggested to write > your own test bench. Can anybody give me a clue on how to do this? On > the Xilinx site I was not able to find a description on this, but that > probably is caused by the fact that there is such a huge amount of data > there. To be more specific, I am looking for information on for example > adjusting/sizing simulation time, preferably with example files. All > quite basic, I think. > > Thanks, > > Aart Check out www.opencores.org. Many, many free IP cores, most with excellent test benches. Also a few white papers ... Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 60134
Everybody,
(Excuse my sales pitch at this forum..
but lots of folks are asking about where to
start with FPGAs..)
A new FPGA Development Board is out at:
http://www.cmosexod.com/fnd.htm
This board is ideal for:
- Novice or everyone else just wanting to start out
exploring FPGAs.
- SW engineers wishing to get into HW
( no need to mess with solder and irons
and plug-in boards - unless you
want to )
- HW engineers wishing for a low-cost and yet
capable and expandable development board
which can be turned into a permanent board.
( no need to design another board
after your FPGA design is completed. Use
this board to permanently house your design. )
- The board is specially design to have the most
needed features. You won't be buying an expensive
"everything board" just to use 1 or 2 features
of the board. Similarly, if you need features
not present on the board, you can plug in your
own board.
This is a low-cost (relatively speaking), complete with
most frequently used peripherals. Lots of expansion connectors
allows cascading several boards or add your own "daughter" board.
YOU GET A BOARD AND A COMPUTER:
===============================
The Board comes with a complete Computer System core, so
it works right out of the box. It shows the potentials
of the board. Plug in a VGA monitor a keyboard and mouse
and start writing your own application.
The Computer core is yours to keep. The bitstream image of
it is included in the CD, so you can always reload the
board with it.
Article: 60135Followup to: <3F562773.EC0F14B8@yahoo.com> By author: rickman <spamgoeshere4@yahoo.com> In newsgroup: comp.arch.fpga > > Luiz Carlos wrote: > > > > > Electron spin has all the same measurement issues that a FF has. If the > > > state of the electron spin is changing as the measurement is made, then > > > what state is it in? What will be the result of the measurement? > > > > > > > Rick, the electron spin is +1/2 or -1/2, there is no in between state, > > it changes instantaneously (in one fundamental clock tick, ~10^-43 > > seconds). > > > > Luiz Carlos > > But the measurement is not instantaneous. So the transistion could > occur during a measurement. Result... inconclusive measurement which is > what metastability is all about. > Well, actually it is. It might *affect* the spin (Heisenberg wins again) but unlike classical measurements there shouldn't be any ifs about the result. There is a lot of things in the quantum world which is completely counterintuitive to everything we have learned. If you look at quantum teleportation, for example, you'd have to conclude information was conducted backwards in time... <thhgttg>This is of course, impossible.</thhgttg> -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 60136
Hi, I develop Xilinx FPGAs and I am interested in dealing with a maximum fanout of a signal issued from a FF and going to an increasing number of FF. What kind of constraint and/or attribute I can set to this signal so that when the fanout exceeds a certain number I am SURE an extra FF is created. I am using Leonardo and M5.1i. I have used the max_fanout attribute of leonardo but it doesn't seem to make much of anything (anyway there is no replication). Thank you for any suggestion. JFArticle: 60137
Update on the problem: somewhere the LUTs are removed from the project. Any VCC sites I instantiate are removed too. The LUT's and VCC's can be found inside the .edf, but not later (.pcf). Someone? A hint?Article: 60138
Spartan-II internal tristates are different than Spartan-II IOB tristates. IOB tristates to the outside world have user programmable pullups. Spartan-II internal tristates are tristate emulators, not actual tristate lines. I'm having trouble finding the datasheet reference, but the behavior is "like" there is a pullup with strong low drivers. When there are no drivers, the state is high. When there are multiple drivers with conflicting states, the part does not smoke but instead gives a logic low. If you need a logic low when there are no drivers, either add the additional circuitry to drive a logic low when no selects are active *or* invert the logic so your re-inverted TBUF defaults to low when there are no drivers and settles conflicts with a logic-high. "Master" <fabrizio@planet1.it> wrote in message news:d9da09be.0309050300.51dba2b2@posting.google.com... > "Giuseppe³" <miaooaim@inwind.it> wrote in message news:<bj9a6r$gfbou$1@ID-61213.news.uni-berlin.de>... > > I don't sure to undestood your question but using the M0-M1-M2 pins is not > > the right way to do what you want? > > > > Regards > > Giuseppe > > > > "master" <ff@pla.it> ha scritto nel messaggio > > news:iMM5b.292163$Ny5.9019956@twister2.libero.it... > > > Someone knows like turn off the "pull up" that the family "spartan2" > > > connects for default to " tristate" placed inner lines in, from buffer " > > > Tbuf"? > > > I use "Xilinx ISE 4.1ģ" and language "vhdl". > > > thanks > > > > > > > > excuse me for the little clear english. > I reformulate the question. > > I use tool ise 4,1ģ, family spartan2 and language vhdl . When I > synthetize a project that uses internal buffer tristate (tbuf), Pull > up component have been connected to buffer output for default. I would > want to disable this option and to put on the buffer output some pull > up or pull down to my choice. Does some environment variable or some > procedure exist in order to make that? > > thanksArticle: 60139
[snip] > Thank you all. That helped me some, but I am still getting CRAZY!!! > Whenever I change something and tries to redraw the PBD window it just > change my changes back to the original and nothing happens!!! Could I > somehow switch this feature off in the EDK? > > John John, If you've got EDK 3.2 sp2 then you can turn this feature off by going to "Options -> Preferences" then selecting the top button "Redraw schematic layout to synchronize changes." The .pbd will still come up when you open the project but I typically just close it and don't save changes. Best regards, Ryan Laity Xilinx ApplicationsArticle: 60140
Hello, What is the status of the old, 5V Spartan family from Xilinx? I have 2 current products that use them. (XCS10-3PC84 and XCS30-3TQ144) I suddenly noticed all the distributors either no longer list these parts or indicate they are special order. Newark has a part that matches the part number, but lists the manufacturer as Mux-Lab Inc, and the price is outrageous, $42.48, with no discount at any quantity. I got them just a couple of months ago for $16 in small quantity. I was assured by somebody at Xilinx, possibly Peter Alfke, that the 5 V Spartan line would continue to be available for a long time. I suppose if they sold off the masks to an obsolete chip supplier, that is "still available". JonArticle: 60141
Hi Jon - of course somebody from Xilinx can confirm this. However, I know for sure that it is well in production and still shipping volumes to many customers. --Neeraj "Jon Elson" <elson@pico-systems.com> wrote in message news:3F58C665.4070503@pico-systems.com... > Hello, > > What is the status of the old, 5V Spartan family from Xilinx? > I have 2 current products that use them. (XCS10-3PC84 and > XCS30-3TQ144) I suddenly noticed all the distributors either > no longer list these parts or indicate they are special order. > Newark has a part that matches the part number, but lists > the manufacturer as Mux-Lab Inc, and the price is outrageous, > $42.48, with no discount at any quantity. I got them just a couple > of months ago for $16 in small quantity. > > I was assured by somebody at Xilinx, possibly Peter Alfke, that > the 5 V Spartan line would continue to be available for a long > time. I suppose if they sold off the masks to an obsolete chip > supplier, that is "still available". > > Jon >Article: 60142
rickman wrote:
> There is no way to determine when a circuit is metastable or not.
It is possible -- I did it once for a FF design for another company. It
requires a separate, combinational output signal ("metastable flag-out").
But, of course, there's no way to use this to kick the FF circuit itself out
of metastability. All previous comments about this being a no-fix are true.
The flag is generated by taking advantage of the fact that the latch going
metastable has a cross-coupled gate with a known threshold point during
metastability. A 2-input logic gate with a different threshold can detect
that both inputs (ie, Q and Q-bar) are above (or below) it's own (different by
design) threshold point.
Cheers,
Ron Cline
Article: 60143Hi, John! John K. wrote: > Hello people, > > I am strictly a schematic user, please don't turn this thread > into a "but HDLs are really better!!". > I'd like to get a new hobby, i.e. to design some (simple for > now, but then also complex) devices on a SpartanII 300E board. > The kind of devices I'd like to design range from TTL style at > the begin, till, someday, complete CPUs and simple multimedia > devices (e.g. graphic chips as seen in the '80s home computers). > > I downloaded and installed Webpack, but I've been very > disappointed. It looks totally HDL oriented to me.. maybe > I'm wrong, but I couldn't see there what I'm looking for. > > What I'm looking for (pardon the redundancy) is a simple > but yet powerful editor that will let me enter a schematic > (NAND gates, Flip-Flops, etc..); will also let me make new > devices from schematics (i.e. macros!); then *possibly* > simulate all of that; and then finally burn it into my > SpartanIIE chip, letting me also setup various features > of the FPGA (e.g. how to load the initial contents of > block RAM, etc..). > > I have some money to invest, eventually, if the software > is not free.. but I'd like to know all the options before. > > Please.. can anybody shed some light? I'm very confused > and lost.. > > Greets, > John Take a look at IDaSS: http://www.xs4all.nl/~averschu/idass/ Schematic entry with interactive simulation and a seamless interface to the FPGA you're using through WebPACK... Have fun, Ad VerschuerenArticle: 60144
Aart van Beuzekom <aart@westcontrol.com> wrote in message news:<3F584F36.2B55FA1E@westcontrol.com>... > Hei, > > When using the Xilins HDL bencher, the memory usage is running up to > 1GB. I understood this is a known problem and it is suggested to write > your own test bench. Can anybody give me a clue on how to do this? On > the Xilinx site I was not able to find a description on this, but that > probably is caused by the fact that there is such a huge amount of data > there. To be more specific, I am looking for information on for example > adjusting/sizing simulation time, preferably with example files. All > quite basic, I think. Read The Book: Janick Bergeron's _Writing Testbenches: Functional Verification of HDL Models_. See here: http://www.janick.bergeron.com/wtb/default.htm --aArticle: 60145
John K. wrote:
> What I'm looking for (pardon the redundancy) is a simple
> but yet powerful editor that will let me enter a schematic
> (NAND gates, Flip-Flops, etc..); will also let me make new
> devices from schematics (i.e. macros!); then *possibly*
> simulate all of that; and then finally burn it into my
> SpartanIIE chip, letting me also setup various features
> of the FPGA (e.g. how to load the initial contents of
> block RAM, etc..).
If I were required to do schematics, I would use Altera Quartus.
It meets your requirements except for the device.
It has a non-hdl simulator, which I find tedious,
but you might like.
-- Mike Treseler
Article: 60146Allan, Correct! It was in New York before 1900 that the first buried lines were used, and if the battery was negative ground, the copper migrated away from the wires into the ground if there was leakage (which there always was with handwrapped cotton insulated wire cables...). When they flipped the ground to positive, the wires got fatter (with metal salts from the ground) and leakier, but they lasted longer. Austin Allan Herriman wrote: > On Thu, 04 Sep 2003 14:32:15 -0700, Austin Lesea > <Austin.Lesea@xilinx.com> wrote: > > >Tom, > > > >Although the x-bar relays were bi-directional, they were only used in a uni-directional fashion for toll switching (full duplex four wire). > >The only bidirectional metallic stage was the first level concentrator for the phone lines to the subscribers with the x-bar 5 WeCo Class 5 > >office. After that, the circuits were separated into transmit and receive. > > > >The older Strowger step by step relays were bidirectional switching from subsrciber to subscriber, and four wire for toll circuits. > > > >Telco lore bonus question: why is positive ground battery used in telecom? > > The voltage is negative with respect to ground to help reduce > corrosion problems. > > -48V is the standard voltage used in phone exchanges. (Actually > it's more like -52V when float charging, but you get the idea.) > (ETSI standard ETS 300 132-2 says -40,5 to -57,0 Vdc at the equipment > input. A "slight degradation in performance" may exist for voltages > in the range -40,5 to -44,0 Vdc. Telcordia will have similar specs.) > > The magnitude of the voltage is 48V because that voltage is a good > compromise between a number of factors, one major one being the > ability to drive enough power down a long (high resistance) line to > the phone. Really old phone exchanges needed a certain loop current > to activate the hook relay. > > ISDN lines are usually biased at a higher voltage which can be up to > 120V (max allowable for TNV), as the ISDN equipment needs more power. > > Note that some areas use -60V (= 5 x 12V) for POTS. > > Regards, > Allan. > > >Inter-office tie trunk tivia: a revertive dial trunk line would dial the foreign office by initiating the call, and telling the foreign > >office to start dialing. When the foreign office had dialed the right number of digits, the local office would signal it to stop, and go on > >to the next digit. > > > >Extra point question: which class 5 local electronic office switch was demanded by a PUC/PSC to be removed from service due to incredibly > >poor performance? What state's PUC/PSC? > > > >Austin > > > >Tom Seim wrote: > > > >> "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote in message news:<5TL5b.137460$JA5.3292926@news.xtra.co.nz>... > >> > "Brian Fairchild" <spam.spam@spam.com> wrote in message > >> > news:jhcclv0p5n1628t9s1cdfpthac60ltjub4@4ax.com... > >> > > >> > > efficient is a typical design? For instance, if I want to make a 16 by > >> > > 16 CPU controlled crosspoint how many FPGA gates will I need? I can > >> > > see that I need 16 OR gates each with 16 AND array inputs for the > >> > > output terms, 64 latches to store the selection and some more gates to > >> > > do the latch address decoding. Is there any easy way to choose the > >> > > >> > Just as an academic thing for myself. > >> > > >> > Is a bi-directional crosspoint switch able to be produced with a FPGA? My > >> > understanding is they are a matrix of fets each one having a memory cell to > >> > store it's setting. > >> > > >> > So I would say that it was impossible. Even a fully digital one would still > >> > require that an an I/O pin can be used for input and output at the same > >> > time. > >> > > >> > Can anyone confirm or deny? > >> > >> Deny. > >> > >> Crossbars are uni-directional. Now, the REAL relay crossbars used by > >> the telcos upto the 1970s ARE bi-directional.Article: 60147
Hi David Brown (david@no.westcontrol.spam.com), you wrote: > >"John K." <INVALIDANTISPAM@aol.com> wrote in message >news:bj9sb1$gc4bj$1@ID-50260.news.uni-berlin.de... >> >> Hello people, >> >> I am strictly a schematic user, please don't turn this thread >> into a "but HDLs are really better!!". > >I know you don't want to hear this, but I'll try to give a reasoned >arguement rather than a blanket statement. I always liked reasoned arguements.. go ahead. :) >As fpgas get bigger and bigger, there is no doubt that most designers are >using hdls rather than schematics (or sometimes a mixture). For big >systems, there are few that are made using pure schematics. I'm not saying you're wrong, but I don't understand what makes inherently more difficult to use schematic than HDL as projects get larger. I think in a "object oriented" way.. for example, I make Flip-Flops from NAND gates. So I get a Flip-Flop object. I make registers/latches from Flip-Flops, so I get a Latch object. I mean, complexity can naturally get encapsulated and encapsulated, till you have a whole ALU, or a whole processor, etc.. and your schematic always looks simple (circuits and subcircuits encapsulated into virtual devices). I don't have much experience with current schematic software (I used mostly my own.. nothing fancy anyway, but worked well for encapsulating at least), but I see no reason why schematic based (using macros) should be any slower or more confusing than HDLs? I can only think about one problem: simulation gets slower and slower. But neither this must be true: if simulating a whole Latch via NAND gates may be slow, after I know it works well and I have its timing characteristics known, I can encapsulate also them into the "black box" and simulation of a Latch will be very quick.. having just to simulate the function (and delays) from input to output. HDL's IMHO are very confusing, hardware wise. A schematic is much more natural and intuitive. IMHO of course. On the other hand the non-intuitive, too abstract HDLs will make you design things that then in silicon are very inefficient.. will not give you a good "big, real picture" of what you're doing, etc.. >This means that >tool designers will put far more effort into the HDL support for their tools >than schematic support. Yep, and that just makes me think that the problem is not in the schematic idea per se, but in the current software. This is a typical situation for the usual "no programs satisfied my needs, so I wrote my own". :D Too bad I don't have that much free time.. so I'd prefer to stick with something already available. I have my own schematic based simulator but its editor is nothing mature at all, and it's missing many features. >I haven't tried doing schematic design for an fpga, >so I can't comment directly, but I have heard complaints on this newsgroup >about the quality of the schematic tools for some fpgas. It also means that >if you are learning about fpgas, there is a lot to be said for looking at >using HDLs - you are going to get better tool support, better online >tutorials and introductions, and end up with a more useful skill. Right, I feel much "out of the world" by not following the HDL route.. but I can't help.. it's a hobbyst project and I have to enjoy it. This definitely means "no HDLs". ;) >If you really want to use schematics, it may be that the best route is to do >the design using your current schematic design software and then use edif >netlists to import it into the fpga toolkit - I'm sure there are others in >this group who could give you ideas there. That's very interesting. Please, can you elaborate more on this? You mean that I could do schematic entry and schematic simulation on any software that is able to save in EDIF format? What would be the best software (simulation-wise) capable of it, can you name a few? And then I could load the EDIF file into Webpack (?) and from there what should I do? Is further simulation (more FPGA-device targetted) possible? How could I express things like block-ram in the former schematic program, if it's quite totally separed from the back-end tools? Thanks for your time! JohnArticle: 60148
Hello!
I'm trying to build the following thing: a 7-segment-led that increases its
value every time a switch is pressed.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sevsegment is
Port (
clk_i: in std_logic;
sevseg : out std_logic_vector(6 downto 0);
reset : in std_logic;
switch: in std_logic);
end sevsegment;
architecture Behavioral of sevsegment is
signal sevseg_s: std_logic_vector(6 downto 0);
begin
process(reset,switch,clk_i)
variable counter: integer range 0 to 9;
begin
if clk_i'event and clk_i='1' then
if reset='0' then
counter:=0;
sevseg_s <= "1111110";
elsif switch'event and switch='0' then
if counter<9 then
counter:=counter+1;
else
counter:=0;
end if;
case counter is
when 0 => sevseg_s <= "1111110";
when 1 => sevseg_s <= "0110000";
when 2 => sevseg_s <= "1101101";
when 3 => sevseg_s <= "1111001";
when 4 => sevseg_s <= "0110011";
when 5 => sevseg_s <= "1011011";
when 6 => sevseg_s <= "1011111";
when 7 => sevseg_s <= "1110000";
when 8 => sevseg_s <= "1111111";
when 9 => sevseg_s <= "1111011";
end case;
end if;
end process;
sevseg <= sevseg_s;
end Behavioral;
Why doesn't it work? I know that "multiple clocks" are not allowed, but i
can't find any solution to solve my problem.... :-(((((((((
In the end, everything should be implemented to a spartanII-FPGA...
Thank you very much,
Simone
Article: 60149> Thank you all. That helped me some, but I am still getting CRAZY!!! > Whenever I change something and tries to redraw the PBD window it just > change my changes back to the original and nothing happens!!! Could I > somehow switch this feature off in the EDK? I found the PBD 200% useless, so doing all modifications in add/edit cores dialog. After closing it I always say 'regenerate' it will redraw PBD then I close PBD and say overwrite MHS it works that way but agree is ANNOYING, no idea how to disable that PBD update ... antti http:/www.graphprd.com/forum
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