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Hello, There seems to be a great deal of interest on this topic. I can tell you what I believe to be the case, and I invite others from Xilinx to correct what I write here, if I make any errors. Most of this I have learned from others. As I do not specify or guarantee device behavior, the device datasheet takes precedence over anything I might say... In devices like V2Pro and S3, the maximum allowed voltages (both positive and negative) on the I/O pins form a smaller window than in some previous families. In the I/O itself, there are structures that experience a "stress" that is: * Pin voltage above GND. * Pin voltage below VCCO. When you are using a VCCO of 3.3 volts, you must be diligent in your board design so that you do not have big reflections from signal integrity problems. If you have severe reflections when using a VCCO of 3.3 volts, you can possibly exceed the maximum ratings of the device. Yes, there are diode clamps on the pin, to both VCCO and GND, but with a VCCO of 3.3v, the clamps will allow the voltage to rise above the maximum rating of the device when VCCO is 3.3 volts. So, when using a VCCO of 3.3v, it is a wise idea to simulate the I/O you are using, along with your board, to make sure you are operating the device within the maximum ratings. I think this homework is worthwhile, even in other cases. If IBIS models aren't your thing, and you can't be bothered with them, you can read XAPP659 for pre-engineered solutions. > What about busses, like PCI, where the driver might be in > the middle so the effective line impedance is half of the > nominal 50 ohms. This is discussed in detail in XAPP653. You use a VCCO of 3.0 volts. It works, is PCI compliant (even if the PCI bus voltage VIO, which is an independent supply, rises as high as 3.6 volts -- which is allowed). Xilinx has verified this in hardware. The concept is that lowering VCCO to 3.0v reduces the "stress" applied: * (Pin voltage above GND) by clamp diode to VCCO = 3.0v. * (Pin voltage below VCCO) by reduced VCCO = 3.0v. An added benefit of our I/O design is that all programmable I/O are identical, so you won't find yourself forced into a larger part if (for example) you need more PCI capable I/O. It is unfortunate that someone (incorrectly) suggested the device I/O is not "robust". It is robust, and guaranteed by Xilinx, when you use it as directed in the FPGA device datasheet. Hope that helps, EricArticle: 60501
ISE version 6.1i supports mixed language flows. ISE Foundation is available now. ISE WebPACK will be ready by the end of this month. Valentin Tihomirov wrote: >My system has netlist in EDIF while some of technology elements used in the >netlist are >described in a separate VHDL file at logic level. WebPack supports only pure >EDIF, schematic, Verilog or VHDL design flows. Is ther a way to compile a >mixed design? >That is, I first elaborate VHDL and then load EDIF netlist which uses VHDL >components. > >May be ISE Foundation supports this? > > > >Article: 60502
> It means that inside the FPGA in evertying clock cycle the value the Or you are not waiting long enough. Another way to do this is to do some polling. Set a flag at some read address and drive bit0 to a one when you are ready to transfer data. SteveArticle: 60503
Neeraj Varma wrote: >FPGA express is obsolete (Xilinx removed it and Synopsys also does not have >it)...and I doubt there is anything anyone could do to setup the license >again (I may be wrong though...) > >If you are using any of the devices supported by the Xilinx Webpack (All >CPLDs, All Spartan-II, All Spartan-IIe except 400e and 600e, XCV50E-XCV300E, >XC2V40-XC2V250, XC2VP2, 3S50, 3S200, 3S400) you can use the XST tool for >synthesis. Webpack can be downloaded free from downloads page of >support.xilinx.com > > Well, that's the problem! I'm using 5V original Spartan chips, and need them for voltage compatibility. I suppose I could look into using later Spartans with some sort of logic level converter. The lower price of the newer (and smaller die) Spartan-II and such could easily pay for the converting circuits. But, I don't really want to redesign the boards on a current product. It bugs me they don't support the old Spartan. All it would require is a few data files, it seems. I have the software working on an old (retired) computer, but the license is locked to the hard drive serial number, and I can't move it to my current machine. JonArticle: 60504
Hi I am quite new in this field, Please excuse me if I talk something nonsence. I have 10 pressure sensors which measure pressure in 10 different points in a field. I need to aggregate all these values in realtime and send to a remote computer.For this, somebody suggested me to use fpga, I made little research and found out that we can actually run an some programs on fpga. I have this idea now, to build an fpga board which can read data from the sensor and send that data to a central computer in the field over a wireless network. and I will have an fpga at each sensor. CEntral computer will aggregate the data and send to a remote location via phone line etc. For this to be realized I have to know whether an fpga is capable of collecting date from a sensor and send the same data over a wireless network. Please give me pointers on this . Any help would be greatly appreciated. Thanks SrikanthArticle: 60505
I'm working on a project with USB to a XILINX FPGA. The interface chip I'm going with is Phillips ISP-1501 http://www.semiconductors.philips.com/cgi-bin/pldb/pip/isp1501 Good Luck, Colin "jakab tanko" <jtanko@ics-ltd.com> wrote in message news:bk4g4g$j0f$1@news.storm.ca... > Hi, > > I am looking for an USB transceiver chip that can be interfaced to an > FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok. > Any suggestions? > > Thanks, > --- > jakab > >Article: 60506
Rider, See inline. Regards, Wei > 1)What is meant by optional pull ups? There are options in the > Constraints Editor to insert pull ups at the I/Os. Are these PERMANENT > pull ups or just during configuration? If I select these pull ups, > then i also need to set M2M1M0=100 ? The pullup that you set in constraints editor is a post-config setting only. http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/lib/lib0338_306.html > 2)Alternatively if i DO NOT select those pull ups in the Constraints > editor, but i still set M2M1M0=100 then what will happen? Pull ups > will be used for configuration only? See above > 3) Do i need to connect all my VCCO pins to 3.3V and VCCINT to 2.5V? > All GND pins on the pacakge be grounded? Solution 17240 http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=17240 > 4)If I use one clock signal in my design, then it can be input on only > one IGCKO(input global clock buffer) or i need to connect all IGCK's > to this clk signal? As long as clock region rule is not violated. Check datasheet for more info. http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=172401 > Regards > RiderArticle: 60507
Jon Elson wrote: > > Neeraj Varma wrote: > > >FPGA express is obsolete (Xilinx removed it and Synopsys also does not have > >it)...and I doubt there is anything anyone could do to setup the license > >again (I may be wrong though...) > > > >If you are using any of the devices supported by the Xilinx Webpack (All > >CPLDs, All Spartan-II, All Spartan-IIe except 400e and 600e, XCV50E-XCV300E, > >XC2V40-XC2V250, XC2VP2, 3S50, 3S200, 3S400) you can use the XST tool for > >synthesis. Webpack can be downloaded free from downloads page of > >support.xilinx.com > > > > > Well, that's the problem! I'm using 5V original Spartan chips, and need > them > for voltage compatibility. I suppose I could look into using later > Spartans with > some sort of logic level converter. The lower price of the newer (and > smaller > die) Spartan-II and such could easily pay for the converting circuits. > But, I don't > really want to redesign the boards on a current product. It bugs me > they don't support > the old Spartan. All it would require is a few data files, it seems. > > I have the software working on an old (retired) computer, but the > license is locked to the > hard drive serial number, and I can't move it to my current machine. > > Jon There is help for this. Whenever I install a new hard drive in a machine, I give it the same serial number as all the others. Then I can use my license on any hard drive I happen to use. Since I swap out hard drives as a backup means, this is essential. If you need info on changing your hard drive serial number, there is a program available for that (as long as you are running a FAT drive and not NTFS). Or I can send you instructions for doing this manually using the old DOS DEBUG commands. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60508
I have looked at that one some time ago but there was a message on the Philips website that the chip is going obsolete and that scared me away... I tried to confirm with the Philips rep. here in Ottawa,Canada but all I got to talk to was an answering machine!. Did you manage to get an eval board for it? --- jakab "Colin Jackson" <jacksoncolin@fake_yahoo.com> wrote in message news:1sOdnZlEhZ77j_uiU-KYuA@comcast.com... > I'm working on a project with USB to a XILINX FPGA. > The interface chip I'm going with is Phillips ISP-1501 > http://www.semiconductors.philips.com/cgi-bin/pldb/pip/isp1501 > > Good Luck, > Colin > > "jakab tanko" <jtanko@ics-ltd.com> wrote in message > news:bk4g4g$j0f$1@news.storm.ca... > > Hi, > > > > I am looking for an USB transceiver chip that can be interfaced to an > > FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok. > > Any suggestions? > > > > Thanks, > > --- > > jakab > > > > > >Article: 60509
Thanks for the suggestion, it looks like they also have USB 2.0 chip, the board you have looks interesting too. I will search a bit more before deciding. --- jakab "Nial Stewart" <nial@spamno.nialstewart.co.uk> wrote in message news:3f65cb6d$0$10961$fa0fcedb@lovejoy.zen.co.uk... > jakab tanko <jtanko@ics-ltd.com> wrote in message > news:bk4g4g$j0f$1@news.storm.ca... > > Hi, > > > > I am looking for an USB transceiver chip that can be interfaced to an > > FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok. > > Any suggestions? > > The FTDI 245BM sounds like what you want (although it's only 1.1). > > See.. > > http://www.ftdichip.com/ > > ..for details. > > I've a board based on this I built for my own use (see under > downloads on my web site). I've a couple sitting here that > someone said they wanted but money hasn't been forthcoming. > > Yours for £30 each if you want one/both for prototyping. > > See my downloads page for details of an example project showing > how to drive it, it's relatively easy. > > > Nial Stewart > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > www.nialstewartdevelopments.co.uk > > >Article: 60510
Here is the answer I got from marketing: "As we make devices cheaper we optimize all of the backend steps (Assembly, Sort, FinalTest, Shipping quantities, Stocking, Distribution Stocking). All of these rely on having large volume . Consequently, Spartan lower-volume pricing is comparatively higher than is common in the industry. In this instance however the customer is also using an expensive package as opposed to a cheaper FG256 package, which makes the difference seem even larger. An FG256 would be a lot cheaper. However he has to get a quote from his regular channel." I hope this explains the surprising difference between $85 and the projected $20. It's due to relatively low volume and the choice of an expensive package. Peter Alfke ============================ Peter Alfke wrote: > > Pete, I have forwarded your e-mail to our marketing group. Let's see > what they say. > I do not have to explain to you that late 2004, slowest speed grade, > plus high volume are the parameters that get you the lowest price. Let's > hear it from Marketing... > Peter > ================= > Pete Fraser wrote: > > > > You mentioned in a recent thread that the 3S1000 would sell > > for $20 in CY2004 in the slowest speed grade and large > > quantities. > > > > I was recently quoted $85.65 for XC3S1000-4FG676C > > in 5000s for CY2004. Is there really such a huge difference > > between 5000 piece prices and "large quantities"? > > > > I ended up going with an off-the-shelf solution as being more > > cost-effective, but a $35 ish price might have made for > > a different decision.Article: 60511
Please investigate IEEE STD 1532 (IEEE Standard for Boundary-Scan-based In System Configuration of Programmable Devices) to see if that satisfies your needs. It is supported by all major programmable logic vendors. http://grouper.ieee.org/groups/1532/index.html Valentin Tihomirov wrote: > My university task involves use of reconfigurable logic. I need to automate > re-configuration > and organize data transfers between PC and FPGA. The netlist to be > downloaded into FPGA is described in EDIF file (I can have it as VHDL or > Verilog as well). I was recommended to use WebPack and TCL scripting for > automatic compilation. However, I want not to restrict my system with the > compiler/Xilinx FPGAs. I want my system to be as universal as possible. > > I want to let user to choose any off-the-shelf FPGA depending on its > requirements and financial opportunities. This also means that I want to use > existing HW(pci, isa, rs232, etc.) and SW (driver) interfaces. Are there any > existing re-configurable industry standards (cards, HW/SW interfaces) I can > relay on? An alternative would be to create a level of abstraction from the > board. > > > >Article: 60512
On a sunny day (Mon, 15 Sep 2003 14:01:17 -0500) it happened Srikanth Anumalla <srikanth@unlserve.unl.edu> wrote in <bk523v$355$1@unlnews.unl.edu>: >Hi > >I am quite new in this field, Please excuse me if I talk something >nonsence. I have 10 pressure sensors which measure pressure in 10 >different points in a field. I need to aggregate all these values in >realtime and send to a remote computer.For this, somebody suggested me >to use fpga, I made little research and found out that we can actually >run an some programs on fpga. I have this idea now, to build an fpga >board which can read data from the sensor and send that data to a >central computer in the field over a wireless network. and I will have >an fpga at each sensor. CEntral computer will aggregate the data and >send to a remote location via phone line etc. For this to be realized I >have to know whether an fpga is capable of collecting date from a sensor >and send the same data over a wireless network. Please give me pointers >on this . Any help would be greatly appreciated. > >Thanks >Srikanth > > If your pressure sensors have analog output, then why use FPGA? Use a PIC micro with build in AD and 4 channel input mux. 3 of these or one with an external mux, use the serial port of the PIC or make your own protocol or whatever. 12F675 is only 8 pins DIL, has a 10 bits AD with 4 input mux, internal oscillator, costs 2 dollars, so 4 of these set you back 8 dollars and the microchip tools are free from www.microchip.com Why use FPGA?Article: 60513
The Shortwave radio design I refer to on my website uses a 100K gate Spartan
(http://www.andraka.com). Not so long ago, 200K gates was considered an
enormous device. At that time (about 6 years ago), I was using mostly 25K gate
XC4025E's and doing some pretty sophisticated signal processing with 3 or four
of them on a board. With that in mind, 200K gates should be ample for what you
intend.
bobi wrote:
> I want to start with Xilinx FPGA's. How does one start cheap? I see a
> development kit from Digilent for $99 US.
> It is for a Spartan IIE. But then I see there is a Spartan III but no
> development kit for this.
>
> What are the options. Can the Spartan IIE 200K gate do a lot of designs. Is
> that enough gates?
>
> --
> Yours sincerely,
>
> Bobi Mageroski
> Practel Pty. Ltd.
>
> Tel: 61 2 9957 1797
> Fax: 61 2 9957 2892
>
> e-mail: bobi.mageroski@practel.com.au
> www.practel.com.au
>
> -----------------------------------------------------------------
> Important Notice:
> This email is for the named recipient only. Its contents are confidential.
> If you are not the authorised recipient you must not use, disclose or copy
> any of these contents. If you receive this email in error please contact us
> immediately and delete the email from your system.
> -----------------------------------------------------------------
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60514
It very heavily depends on your implementation. The fact that it is
radix2 and
not radix 4 or higher tells me already that your implementation is not a
very
efficient one. A radix 4 kernel is very little added complexity over a
radix 2
kernel and cuts the processing time and area considerable. Depending on
your
speed requirements and your design prowess, you can certainly fit a 128
point
real-only FFT in a much smaller part than a 1M gate part. As your speed
requirements decrease, you can take advantage of iterative or shared
hardware
to reduce the gate count considerably. I did a 4096 point design in a
Xilinx
XCV1000 that does the complex transform in 68 us (the floorplan and a
brief
description are on the gallery page on my website). That one only
occupies
about 40% of the FPGA and includes some floating point stuff as well as
windowing multipliers and some other goodies. It takes intimate
knowledge
of the FPGA structure and of algorithms to achieve that level of density
(the customer called the design "a work of art"), but even a novice can
achieve a density/performance level of half that design with some
carefully
thought out design.
PJ wrote:
> Hello,
>
> I am implementing a 128 point real Radix-2 fft, data and coefficient
> widths are 16 bit.
> I am synthezising it for use in an FPGA. However, it is taking a very
> long time to synthesize. (approx 3 days using Leonardo on a 2 GHz
> machine with 512 MByte RAM) I am using a 20K1000 Altera FPGA. The ram
> required by the fft will be internal to the FPGA
>
> Will this design take up all the space on the device. From past
> experience, can someone give me an indication of what area of the
> device the fft will occupy.
>
> Surely if it takes up most of the device, then it will be too big, as
> I have other features to implement in the FPGA also !!
>
> Thank you
> PJ
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60515On Mon, 15 Sep 2003 17:07:22 -0400, "jakab tanko" <jtanko@ics-ltd.com> wrote: >Thanks for the suggestion, it looks like they also have USB 2.0 chip, >the board you have looks interesting too. I will search a bit more before >deciding. Their chip will not run USB2.0 high speed, only full speed. ( I have been able to get 1 MB/sec max on a real board ) Otherwise it is great, I have used it on several boards. They are going to have a high speed chip but it is at least a year off as it is just in planning , this is a major bummer for my projects. >--- >jakab >"Nial Stewart" <nial@spamno.nialstewart.co.uk> wrote in message >news:3f65cb6d$0$10961$fa0fcedb@lovejoy.zen.co.uk... >> jakab tanko <jtanko@ics-ltd.com> wrote in message >> news:bk4g4g$j0f$1@news.storm.ca... >> > Hi, >> > >> > I am looking for an USB transceiver chip that can be interfaced to an >> > FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok. >> > Any suggestions? >> >> The FTDI 245BM sounds like what you want (although it's only 1.1). >> >> See.. >> >> http://www.ftdichip.com/ >> >> ..for details. >> >> I've a board based on this I built for my own use (see under >> downloads on my web site). I've a couple sitting here that >> someone said they wanted but money hasn't been forthcoming. >> >> Yours for £30 each if you want one/both for prototyping. >> >> See my downloads page for details of an example project showing >> how to drive it, it's relatively easy. >> >> >> Nial Stewart >> >> ------------------------------------------------ >> Nial Stewart Developments Ltd >> FPGA and High Speed Digital Design >> www.nialstewartdevelopments.co.uk >> >> >> > >Article: 60516
rickman wrote: > ... > If you need info on changing your hard drive serial number, there is a > program available for that (as long as you are running a FAT drive and > not NTFS)... VolumeID: http://www.sysinternals.com/ntw2k/source/misc.shtml -- My real email is akamail.com@dclark (or something like that).Article: 60517
It is pretty straight forward. See my article in XCell about digital
downcoverters. There is a link on the publications page of my website to
the paper.
Jan wrote:
> Hi,
>
> Can anyone point me at a vhdl design for a DDC, Digital Down Convertor,
> in an FPGA. Preferably free.
> It should be a wideband design with up to 10MHz and as low as 100KHz
> bandwidth. Resolution of adc is 14bits.
> Also it should be possible to synthesise it with the Xilinx Webpack.
>
> Thanks for any help
>
> Jan
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60518
Peter,
My understanding was that those pictures were of Xilinx parts. Of course if
you sample them at a low enough rate, it looks like an unpredictable delay
even if it is not.
Peter Alfke wrote:
> I have a lot of respect for Phil, we are personal friends and have
> worked together for over 20 years. I think he used old TTL pictures.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60519Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? I looked very closely at the 1.1 version and found it took only 6 pins and $1.75 transceiver chip. Ken "jakab tanko" <jtanko@ics-ltd.com> wrote in message news:bk4g4g$j0f$1@news.storm.ca... > Hi, > > I am looking for an USB transceiver chip that can be interfaced to an > FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok. > Any suggestions? > > Thanks, > --- > jakab > >Article: 60520
Hi folks, Does anybody know if there are machine readable versions of the Spartan3 pin tables, like those that exist for V2 and V2pro? e.g. http://www.xilinx.com/products/virtex2pro/package/2vp7fg456.txt I've tried extrapolating the naming scheme to make a guess at the url, but no luck. For Xilinx, a quick gripe: I spend a lot of time at the xilinx website, accessing it on an almost daily basis, and am a professional researcher. Yet still, I am often unable to navigate to information that I *know* is present. For example, I ended up finding these V2/V2Pro pin tables by digging out an old one I'd saved to my hard drive, and doing a google search on the file name. Anyway, enough whinging - how about those S3 pin tables? Thanks, JohnArticle: 60521
John Williams wrote: > > Hi folks, > > Does anybody know if there are machine readable versions of the Spartan3 > pin tables, like those that exist for V2 and V2pro? > > e.g. http://www.xilinx.com/products/virtex2pro/package/2vp7fg456.txt > > I've tried extrapolating the naming scheme to make a guess at the url, > but no luck. > > For Xilinx, a quick gripe: I spend a lot of time at the xilinx website, > accessing it on an almost daily basis, and am a professional researcher. > Yet still, I am often unable to navigate to information that I *know* > is present. For example, I ended up finding these V2/V2Pro pin tables > by digging out an old one I'd saved to my hard drive, and doing a google > search on the file name. > > Anyway, enough whinging - how about those S3 pin tables? I feel your pain. Many companies turn data sheet location into an easter egg hunt. Xilinx is far better than many and worse than some. I just downloaded the pin lists today. I think I had used a search on the Xilinx web page for datasheets on "Spartan 3". It gave me a list of the four data sheet parts, the complete data sheet (thanks Xilinx) and both ascii and excel pinouts. Here is the URL that showed up, I just happen to still have the page open... http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/Data+Sheets/FPGA+Device+Families/Spartan-3&iLanguageID=1 -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60522
Hi, Does anyone know what to do with the pin on V2P called "RSVD"? I guess I'm meant to leave it open, but I haven't found anything in the datasheet or the Xilinx answers database that says for sure. TIA, Allan.Article: 60523
John Williams wrote: > > Hi Rick, > > rickman wrote: > > Looks like I have not done my homework on this. I had done some > > research on modular configuration which was what I required. The > > Spartan lines seem to be supported for this although they don't yet list > > the Spartan3 chips. But I was under the impression that partial > > configuration was the down load technique to support this in the > > devices. I see that only Virtex and Virtex-II are supported by partial > > configuration. This is not good. > > Don't panic! the S3 still supports partial reconfiguration - the ICAP > primitive that Antti and I were talking about is a block that allows the > partial reconfigruration to be controlled from within the device itself > ie. self-reconfiguration. > > All the Virtex's and S3 can be partially reconfigured from *outside* the > device, via SelectMap or slave serial or whatever, either partial or > total reconfiguration. > > > So why the disconnect on partial configuration Xilinx? Why not support > > Spartan-3 devices? > > As I said, it's just the ICAP (internal configuration access port), not > the partial reconfig capability itself. > > Regards, > > John I am still in panic mode. I started digging and found that the Spartan 3 devices are not suitable for modular configuration. Seems the tbuf is one of the features in the V2 devices that has been taken out for "optimization" in the S3. The tbuf is required for signals that traverse modules. I have exchanged a couple of emails with Xilinx on this and am waiting for the final word. But it is looking like the Sparan 3 devices will not be able to do what I need in any defined timeframe. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60524
rickman wrote: > John Williams wrote: >>Anyway, enough whinging - how about those S3 pin tables? > > > I feel your pain. Many companies turn data sheet location into an > easter egg hunt. Xilinx is far better than many and worse than some. > > I just downloaded the pin lists today. I think I had used a search on > the Xilinx web page for datasheets on "Spartan 3". It gave me a list of > the four data sheet parts, the complete data sheet (thanks Xilinx) and > both ascii and excel pinouts. Here is the URL that showed up, I just > happen to still have the page open... > > http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/Data+Sheets/FPGA+Device+Families/Spartan-3&iLanguageID=1 Thanks Rick. For some bizarre reason these pin tables are in a different format to those provided for V2 and V2Pro! But anyway, I'll massage them as necessary. Actually what I'm trying to do is assess how to wire a board that might potentially contain any of the fg-456 parts. There are 3 each of spartan3, virtex2 and v2pro devices using the fg456 package. What I'm trying to achieve is a table that looks like: pin 2v250 2v500 2v1000 2vp2 2vp4 2vp7 3s1000 .... A1 GND GND GND ... A2 ... and so on, so I can look across and determine all common pins between parts, and all non-common pins, and go from there. Kind of like generalising Xilinx's pin compatability tool across the v2, v2pro and s3 families.. thanks again, John
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