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Is there a viewer for the schematic files generated by the Actel Desktop package. We have some designs generated with this package, no longer supported by Actel, license expired, original PC upgraded, and wish to view the schematics. Michael Dunbar EW Simulation Technology LtdArticle: 60601
Hello everyone
I was wondering if any congress on FPGA systems will take place on
China, Taiwan or HK in a near future. Any references?
Thank you,
Chang.
Article: 60602
Hello everyone,
What is the cheapest line of volatile Xilinx´s FPGAs?
What is the relation between Altera´s LEs and Xilinx´s Slices?
I need the cheapest Xilinx FPGA (or from any other manufacturer) that
has the aproximated same capacity as a 700-1000 Altera´s LEs. What would you
suggest?
Thank you very much,
Roberto.
Article: 60603> Hello everyone > > I was wondering if any congress on FPGA systems will take place on > China, Taiwan or HK in a near future. Any references? > Thank you, > Chang. Altera's SOPC world? Japan, China, South Korea, Taiwan, India. http://www.altera.com/corporate/promotions/specials/sopcworld/spc-sopc03.jsp ?xy=sopc_algh for details (you'll probably have to stitch the url back together). Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 60604
rob d wrote: > > Here is a solution that I can't yet find a hole in. > > Put a comparator on the output of the flip flop(ff1) and call its > output "meta" > comparator indicates meta when ff1 output is just above a logic 1 min > down to just below a logic 0 max. > > now create the next flip flop > > when meta then ff2 = not ff2 (if ff1 is metastable its input was > changing) > else ff2 = ff1. > > ff2 will never be meta stable as long as timing for meta is met. > > We can now use ff1 in a state machine by creating a combinatorial > signal that reflects what ff1 is doing or trying to do. > > when meta then ff1_meta_hard = ff2 else ff1_meta_hard = ff1. > > even if you don't shoot me down I don't expect thousands of > comparators in Vertex 4! :-) I don't understand why this is so hard to understand. Nothing personal, it is just that a lot of people keep trying to make the comparator solution work. The problem is that the output of the comparator has the same problem as the output of FF1. It can be inderterminate (between logic 0 and logic 1) for an indeterminate amount of time. "meta" can be in transition at the time that FF2 is clocked with will clearly lead to FF2 going metastable. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60605
Roberto Gallo wrote: > > Hello everyone, > > What is the cheapest line of volatile Xilinx´s FPGAs? > What is the relation between Altera´s LEs and Xilinx´s Slices? > I need the cheapest Xilinx FPGA (or from any other manufacturer) that > has the aproximated same capacity as a 700-1000 Altera´s LEs. What would you > suggest? > > Thank you very much, > Roberto. If you won't be in production until next year, the cheapest solution will likely be the Spartan 3. If you need parts now, it would likely be the Spartan IIE. Both families have about 1500 logic cells in the smallest part, regardless of what the data sheets says. Xilinx likes to pad the number since they feel they have "uber-cells" which count as more than 1 each. But then again, they don't define the term "logic cell", so I guess they can count them any way they want. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60606
"Lorenzo" <lorenzol@despammed.com> wrote in message news:<bk93jh$q2a5b$1@ID-202895.news.uni-berlin.de>... > "John Williams" <jwilliams@itee.uq.edu.au> ha scritto nel messaggio > news:bk841k$7hf$1@bunyip.cc.uq.edu.au... > > > It would be lovely if we could just put an 8MB xilinx > > platform flash > > part on the board and use it to store both the > > configuration and our > > software images. > > I think it's possible! You can store your custom code as it was a separate > "firmware", like if you have a second FPGA attached. Then the platform flash > will do the rest. Look at the app notes that show how to connect more than a > FPGA to a configuration flash/PROM. hm not as simple as that I am afraid, you can store multiply bitstreams but the second bitstream is streamed out at high speed immediatly after the real one, so after the FPGA comes alive it should start monitoring the serial data in (what platform flash send the second fake fpga) and 'capture' that bitstream and store as firmware. hm with some hardware overhead might be doable. but nothing what you can take 1:1 from appnotes I am afraid anttiArticle: 60607
"Antti Lukats" <antti@case2000.com> ha scritto nel messaggio news:80a3aea5.0309170609.54fbfda3@posting.google.com... > hm not as simple as that I am afraid, you can store > multiply bitstreams > but the second bitstream is streamed out at high speed > immediatly after > the real one, so after the FPGA comes alive it should > start monitoring the > serial data in (what platform flash send the second fake > fpga) and > 'capture' > that bitstream and store as firmware. You could do like Xilinx does, i.e. add a "preamble" at the start of firmware bitstream (e.g. some dummy '1', then a '0'), in order to give to the FPGA the time to start. However, if you use a low CCLK frequency (like 4 MHz - which is the default for Spartan2, if I'm not wrong) I think that the dummy bits needed could be very few... > but nothing what you can take 1:1 from appnotes I am > afraid Of course not 1:1, but the serial configuration protocol is very simple, so it should be easy to implement it into the FPGA! (maybe :)) -- LorenzoArticle: 60608
What Altera calls an LE, Xilinx calls a Logic Cell (yes, I know there is a slight marketing inflation), and two Altera LEs correspond to one Xilinx slice. So you are looking for the XC2S30 (the next-to-smallest member) with the equivalent of 864 LEs ( or the 2S50 with 1536 LE equivalents). Your best bet for low price is the Spartan3 XC3S50 with 1536 LE equivalents. This chip is available in an early version without BlockRAM. Peter Alfke, Xilinx Applications ========================= Roberto Gallo wrote: > > Hello everyone, > > What is the cheapest line of volatile Xilinx´s FPGAs? > What is the relation between Altera´s LEs and Xilinx´s Slices? > I need the cheapest Xilinx FPGA (or from any other manufacturer) that > has the aproximated same capacity as a 700-1000 Altera´s LEs. What would you > suggest? > > Thank you very much, > Roberto.Article: 60609
rickman wrote: > Xilinx likes to > pad the number since they feel they have "uber-cells" which count as > more than 1 each. But then again, they don't define the term "logic > cell", so I guess they can count them any way they want. Not really, the "padding" is exactly 12.5%, so it has been defined and is deterministic. Marketing wants to get credit for the additional multiplexers that the competition does not have. If you are a purist, just count slices and devide by 2, or multiply CLBs by 4 (Virtex and Spartan2) or by 8 (Virtex2 and Spartan3). That gets you the number of LUTs+flip-flops. Peter Alfke >Article: 60610
Well, no good answer yet, but I figured out how to make it much easier to restore all of the broken connections: Turn OFF Use Rubberbanding in the Tools->Options->Block/Symbol Editor->General dialog. Now you can move the block such that all the old pins realign and reconnect. Still, seems braindead for connections to break if the pin/signal names have not changed and I would like to know if this is avoidable. Ken "Kenneth Land" <kland1@neuralog1.com> wrote in message news:vmf84etmtns5a1@news.supernews.com... > Can anyone tell me how to avoid redoing all the Nios block port connections > whenever I edit the processor config? > > Whenever I add something to the Nios config in SOPC builder and update the > block, all of my connections are broken and all I know to do is reconnect > them one at a time manually. This takes quite awhile. > > Is there anyway to have the update preserve the existing connections? It > seems to be based only on physical possition within the graphical editor > which seems strange to me. > > Thanks, > Ken > >Article: 60611
I'm not sure what your cost requirements are, but for getting off the ground one recently released development platform comes to mind.... check out Omniwerks (www.omniwerks.com), who offers a complete 802.11 FPGA/Embedded CPU development kit, with board/software/IP. They use the Nios CPU & uc/OS II operating system on the software side. Jesse Kempa Altera Corp. jkempa at altera dot com > > The reason I went for fpga was to have wireless networking (802.11) > Actually, the sensors are 3-4 miles apart, I need the data until a > base station from where I will transfer the data to the internet. > the base station is located in the filed and will be 1-2 miles distant > from each sensor. So how do I transfer (in realtime) the data until the > base station from the sensor. Is it possible with PCI micro. > Please suggest me if there is a better solution other than fpga cpu > for doing this (wireless networking). > > Thanks in advance > SrikanthArticle: 60612
> We're looking for a high density serial flash part to hold microblaze > uclinux kernel and file system images. The problem with commodity > serial flash parts (SST, Nexflash etc) seems to be that they aren't > really available in high densities (~4 - 8 MB) yet. If someone can > correct me on this then please do! 3 years ago I had no trouble purchasing the Atmel Serial Dataflash AT45D161, which is 2 MBytes big. Certainly the higher densities became available in the meantime.Article: 60613
Then, please enlighten us as to how to use the block rams with Web-pack, without using the core generator. I looked at your web page and did not see in your example projects how you did it. Clyde Nial Stewart wrote: > Clyde R. Shappee <clydes@the_world.com> wrote in message > news:3F64ABE0.783CE26F@the_world.com... > > I just did a little experiment with the webpack software, instantiating a > > fifo in the block ram.... and the software black boxes it because it > doesn't > > know how to hook it up. > > The .edn file from the core generator is missing, and as such XST does > not > > know how to configure the block ram. > > This is consistent with information I received from the Xilinx Apps guy. > > Clyde > > What are you trying to instantiate? If it's a component that you > previously generated from Coregen then it won't work as coregen > stitches whatever Blockrams together to get the structure you > need, creates a wrapper round them and gives it a sensible name. > > If you try to instantiate the wrapper web-pack won't know what you're > talking about. > > Have a look at the data sheet for whatever device you're targeting to > see what the blockrams should be called. As an example a 256* 8 bit dual > port > ram in SpartanIIE is RAMB4_S8_S8, you'll have to check the data sheet for > port names. > > If you want bigger/wider structures than you get with one block ram you've > got to stitch them together yourself (with a wrapper if you want). > > It would be almost a complete waste of time for Xilinx to release web-pack > if you couldn't access blockrams. > > Nial. > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > www.nialstewartdevelopments.co.ukArticle: 60614
> They sell directly, but I live in Italy, and I am a little > scared about customs and shipping fees. I ordered a D2E board to spain, with express shipping. It arrived just 3 or so work days later and the total cost incl shipping was $162 US. I'm very happy with this!Article: 60615
Jesse Kempa wrote: > I'm not sure what your cost requirements are, but for getting off the > ground one recently released development platform comes to mind.... > check out Omniwerks (www.omniwerks.com), who offers a complete 802.11 > FPGA/Embedded CPU development kit, with board/software/IP. They use > the Nios CPU & uc/OS II operating system on the software side. > > Jesse Kempa > Altera Corp. > jkempa at altera dot com > > > > >>The reason I went for fpga was to have wireless networking (802.11) >>Actually, the sensors are 3-4 miles apart, I need the data until a >>base station from where I will transfer the data to the internet. >>the base station is located in the filed and will be 1-2 miles distant >>from each sensor. So how do I transfer (in realtime) the data until the >>base station from the sensor. Is it possible with PCI micro. >>Please suggest me if there is a better solution other than fpga cpu >>for doing this (wireless networking). >> >>Thanks in advance >>Srikanth I know development kits costs are high. Suppose If I want to have 10 such embedded system, do I need to have 10 development kits, I am very new to this, so please ignore my nonsence if any. SrikanthArticle: 60616
In article <3F688290.86C3AAC4@xilinx.com>, Peter Alfke wrote:
> So you are looking for the XC2S30 (the next-to-smallest member) with the
> equivalent of 864 LEs ( or the 2S50 with 1536 LE equivalents).
> Your best bet for low price is the Spartan3 XC3S50 with 1536 LE
> equivalents. This chip is available in an early version without BlockRAM.
The XC2S50E-6PQ208C is in-stock at Digi-Key for $14.55 quantity 1.
The cheapest theoretical price I have seen for the XC3S50J is $23.85
(for a -4TQ144CES), and I have yet to see a distributor claim stock.
I know which one I would choose.
- Larry
Article: 60617Well, newness has its price. But a year from now, the XC3S50 will be the low-cost champion, especially in high volume... But there is nothing wrong with using Spartan2, except for the smaller BRAM and the simpler clock manager, compared to the upcoming production Spartan3-50.... Peter Alfke =========================== Larry Doolittle wrote: > > The XC2S50E-6PQ208C is in-stock at Digi-Key for $14.55 quantity 1. > The cheapest theoretical price I have seen for the XC3S50J is $23.85 > (for a -4TQ144CES), and I have yet to see a distributor claim stock. > > I know which one I would choose. > > - LarryArticle: 60618
Leon Heller wrote: > > > Jon Elson wrote: > >> Hello, >> >> Has anyone bought anything from www.dragonsources.com? >> I'm having trouble finding any distributor in the US that will sell >> the XCS10-3PC84C (old, 5V Spartan) in less than 300 pc quantities, >> or for less than $42 ea. These guys claim they have them for $12 >> ea., but I don't know if they are for real. They are apparently >> in China, or thereabouts. > > > > > > Farnell might have them in stock: http://www.farnell.com > Yeah, sure, at $42 each, in quantity! I paid $16 for them a few months ago. Now, nobody stocks them in the US, or they want a min quantity of 300 pieces. One thing I'm worried about is that these parts from China are unauthorized clones of the Xilinx part. If they go so far as faking the markings, how could I tell they are counterfeit? JonArticle: 60619
I'm having a very odd problem... Quartus II (2.2) has started ignoring .mif file changes on me when doing "smart compile", which requires me to sit for 20 minutes and recompile the whole design for a simple memory change. The really weird part is that this is new behaviour -- I have one project on which this works beautifully and it was a major assistance debugging that design, but on a different (somewhat larger) project, it doesn't work at all -- Quartus seems to just ignore the .mif file changes and happily produces bitstream files with all the old memory contents. Is there a hidden option somewhere? I have added all the .mif files as project files; it doesn't seem to affect this behaviour. -hpa P.S. Upgrading to Quartus 3.0 is not an option due to the changes in platform requirements. -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 60620
Ken, This seems to be an evil of block-based schematic design. The more traditional blocks that we'd instantiate have a fixed set of ports... and no need to move connections around. For SOPC-type systems where peripherals and memory are added (or removed) with a mouse click, it becomes more difficult. One trick I use is to highlight an area in the schematic file containing groups of pins & wires (connected to a block), and then cut & paste them to a blank area of schematic (for example the SDRAM pins as a group). Since the sets of IO for some piece of IP such as the SDRAM controller don't change, any update you do to a Nios/SOPC system will produce part of the schematic block with the exact same arrangement of IO ports... after modifying my system (and having the schematic block updated), I just select (as a group) the original IO pins, and drag them to connect up to the schematic block. It seems though, that many folks are steering away from schematic blocks because of this in complex designs, in favor of hierarchic HDL. This approach can be taken for Nios designs as our top level (from SOPC Builder) is in fact an HDL file, but we provide schematic top-levels in our example designs for clarity & getting started purposes. Jesse Kempa Altera Corp. jkempa at altera dot com "Kenneth Land" <kland1@neuralog1.com> wrote in message news:<vmf84etmtns5a1@news.supernews.com>... > Can anyone tell me how to avoid redoing all the Nios block port connections > whenever I edit the processor config? > > Whenever I add something to the Nios config in SOPC builder and update the > block, all of my connections are broken and all I know to do is reconnect > them one at a time manually. This takes quite awhile. > > Is there anyway to have the update preserve the existing connections? It > seems to be based only on physical possition within the graphical editor > which seems strange to me. > > Thanks, > KenArticle: 60621
What format are they in? Michael Dunbar wrote: >Is there a viewer for the schematic files generated by the Actel >Desktop package. > >We have some designs generated with this package, no longer supported >by Actel, license expired, original PC upgraded, and wish to view the >schematics. > >Michael Dunbar >EW Simulation Technology Ltd > >Article: 60622
If you don't need a response (reporting typos, etc.) you can provide feedback by clicking on the "Helpful? Yes/No" link next to each app note link. For general technical support you can use the phone and web contacts shown at http://www.xilinx.com/support/services/contact_info.htm. Austin Lesea wrote: > Walala, > > You may email it directly to Peter Alfke, or myself. > > Austin > > (au s ti n ( a t ) x i l i nx.c o m) (to fool the spam scanners? > just remove spaces and replace at with the obvious) > > walala wrote: > > > Dear all, > > > > I think I read the application notes from Xilinx FPGA( I downloaded > > from their website), and I found a mistake(or maybe I have some > > problems myself), how I can contact the writer of Xilinx application > > author? ... I searched many options from their website and could not > > find one... which support team I should contact? > > > > Any insider please give me some contacts? > > > > Thank you very much, > > > > -Walala -- Marc Baker Xilinx Applications (408) 879-5375Article: 60623
The Xilinx web pages typically combine 5V Spartan with the 3.3V Spartan-XL and refer to the "Spartan/XL" together since they have the same basic architecture. The data sheet is also a combined document. Let me know what search options you used that came up empty for the XCS10. According to muxlab.com MuxLab is "is a leading designer of value-added connectivity hardware allowing audio-video and data equipment to be connected via cost-effective copper twisted pair." No relation to Xilinx and not a second source. I don't see them mentioned on the Newark web site. Jon Elson wrote: > Well, the Xilinx web pages show no mention of Spartan without the XL, > II, etc. and a search of XCS10 comes up with nothing. Digi-Key used to stock > the > XCS10 through XCS40 or so, and other distributors also had them in their > on-line catalogs. Now, when I search at various distributors, I either get no > match or > "special order". I'll have to talk to some people. Also, who is "MuxLab, > Inc."? They > are apparently supplying something to Newark with the part number > XCS10-3PC84C, and call it a CMOS-CPLD-xxx or something like that. Is that a > real second source? > > Or, is MuxLab just emptying out their warehouse full of old parts? > > Thanks, > > Jon -- Marc Baker Xilinx Applications (408) 879-5375Article: 60624
In comp.arch.fpga Clyde R. Shappee <clydes@the_world.com> wrote:
: Then, please enlighten us as to how to use the block rams with Web-pack, without
: using the core generator.
: I looked at your web page and did not see in your example projects how you did
: it.
Here is how I instantiate in in some verilog project:
RAMB4_S16_S16 ram0(.DOA(),.DOB(rdo_data_a),.ADDRA(rdo_wfifo_cnt),.ADDRB(rdo_rfifo_cnt),
.CLKA(!mclk_i),.CLKB(rclk),.DIA(dba_r[15:0]),.DIB(16'b0),
.ENA(1'b1),.ENB(1'b1),
.RSTA(1'b0),.RSTB(1'b0),.WEA(rdo_read_rrrr),.WEB(1'b0));
RAMB4_S16_S16 ram1(.DOA(),.DOB(rdo_data_b),.ADDRA(rdo_wfifo_cnt),.ADDRB(rdo_rfifo_cnt),
.CLKA(!mclk_i),.CLKB(rclk),.DIA(dbb_r[15:0]),.DIB(16'b0),
.ENA(1'b1),.ENB(1'b1),
.RSTA(1'b0),.RSTB(1'b0),.WEA(rdo_read_rrrr),.WEB(1'b0));
Hpe this helps.
Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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