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If you pick the right xilinx you could multiply the 27MHz up to 108MHz internally. Just use the internal PLL Simon "Guy Eschemann" <geschemann@yahoo.fr> wrote in message news:b9f16a5b.0310062304.4b75202a@posting.google.com... > > But you said that the clock was not truly asynchronous, but was 4 times > > the data rate, with an unknown ( but stable?) phase relationship. > > > > Maybe my description was a bit confusing, sorry for this. The clocks > really are asychronous. There is no stable phase relationship between > them, since the 27MHz clock is the ouput of a PLL locked on the H-Sync > of a video signal, and the 108MHz system clock is derived from a 27MHz > crystal oscillator.Article: 61576
"Martin Thompson" <martin.j.thompson@trw.com> wrote in message news:upth9h1p5.fsf@trw.com... > "Plenolo" <plenolo@freemail.it> writes: > > > Hi all i am new in the group, i am a italian student of computer science and > > i have hobbies for electronics, too... so i have using PIC, St6/7 > > microcontroller, etc.. now my dream is develop some circuit with fpga (or > > similar) and VHLD language. I have just a bit studing (only teorically) VHDL > > in my university, but now i would REALLY program some chip for develop some > > simple and medium project. > > I have not money (and i don't want :-) ) to buy some original developing > > system, so i would home build some free "programmer" (in-circuit JTAG ???) > > how i have do in pass for PIC / St6/7 programmers :-) > > > > You'd be better off on comp.arch.fpga, for the actual hardware > questions - I've crossposted to there and set the followups to go > there also. > > Regarding programming hardware, Altera have the Byteblaster schematics > downloadable from their site, in the Byteblaster datasheet. I can;t > recall if Xilinx have similar. If you hunt around on the web you can still finds the schematics for the old Xilinx Downloaders. > > > Thank you very much to all friends, and sorry for my very bad and poor > > english language :-) > > > > It's better than my Italian! > > Cheers, > Martin > > -- > martin.j.thompson@trw.com > TRW Conekt, Solihull, UK > http://www.trw.com/conektArticle: 61577
"Hal Murray" wrote: > >Perhaps a part of the registration process should require the students to > >email the teacher a list of their most important questions, or list what > >they're hoping to learn. > > If I knew enough to ask the right question I could probably find > the answer myself. Or ask here, or ... > > The main reason I go to a class is to learn something about a topic > when I don't know enough about it to ask the right questions. Not necesarily true. I would expect that anyone attending an intermediate or advanced class could generate a list of things they may have doubts about or want learn. Perhaps problems they've been having that he/she could use help with. Or maybe express a desire to concentrate on a certain topic. While you may know enough to ask the right question, getting from there to an answer might not be all that simple. You can bounce around the online documentation from manual to manual and not get very far. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 61578
Martin Euredjian wrote: > So...I have this little module that creates an RLOC'd SRL-based delay > pipe that will feed one side of an adder in an FIR filter. > Floorplanner confirms that the RLOCs are working as promised. > > However, if I instantiate more than one of these modules, only the > first one is placed per the defined RLOCs and the rest are placed > with SRL's and FF's outside of the required relative locations. I've > looked through every report and I cannot find any warnings that would > indicate that there's a problem of any kind. And the EDIF - always a pleasure to read - looks OK?Article: 61579
H. Peter Anvin <hpa@zytor.com> wrote in message news:<blsls6$n8a$1@cesium.transmeta.com>...
> Followup to: <bae769a6.0310060635.580b510c@posting.google.com>
> By author: irum4@yahoo.com (irum4)
> In newsgroup: comp.arch.fpga
> >
>
> Check through *all* the bits in the configuration space header to make
> sure you match the specification.
>
> -hpa
Vendor ID & Device ID 0007524d
Command &Status 02000187
04800000
00008000
0000bc01
f4400008
00000000
00000000
00000000
00000000
00000000
091e0000
00000000
00000000
00000000
00000103
Article: 61580Hi Subroto, Thank you for replying. I did what you said, but it made very little difference..ie...reduced LE count by 35 (now 111235 LE's)....still miles over the actual size of the device. This is a massive difference, between what Synplify Pro 6.1.3 says and Quartus II 3.0 I re-synthesized the design again in Synplify and got the same result as before so there is definitely some problem in the flow between the two tools. It certainly looks like I'm back to the drawing board design wise. If you can think of anything else, I would be very grateful. Bob "Subroto Datta" <sdatta@altera.com> wrote in message news:<9oegb.6513$TH.4903@newssvr16.news.prodigy.com>... > Bob, > I assume the first experiment was run with Quartus II 2.2 (the one where > it fit without atoms), and the second one was in Quartus II 3.0. As a rule > of thumb using the atom (vqm) netlist should give fairly close results in > the two versions of Quartus, assuming you are optimizing for area (lcell > count) or speed in both cases inside Quartus. > > You may want to run one more experiment. Use the vqm netlist, and in Quartus > II 3.0 > > 1. Set WYSIWYG Primitive resynthesis (aka atom resynthesis) to on. You can > do this from the Assignments->Settings->Compiler Settings->Netlist > Optimizations dialog. This will make Quartus take the vqm netlist, convert > it to a gate level netlist and synthesize it further. > > 2. Next set the Optimization Technique to Area. You can do this from the > Assignments->Settings->Default Logic Option Settings->Optimization > Technique - APEX20K/APEX20K... to Area. > > 3. Set Register Packing to off. You can do this from the > Assignments->Settings->Default Logic Option Settings->Auto Packed Register > Settings list box. Register Packing can sometimes hurt fiting in the APEX > architectures. > > 4.Compile this design with Quartus II 3.0 and check the results. > > If this works turn off the setting in Step 1 and follow recompile the > design. > > > - Subroto Datta > Altera Corp. > > "Bob" <stenasc@yahoo.com> wrote in message > news:20540d3a.0310060457.37847daf@posting.google.com... > > Hi, > > > > I am trying to fit this particular design. I run Synplify Pro to map > > the device. > > In Synplify, with mapping logic to atoms turned on, the design won't > > fit so I disable mapping logic to atoms and can get the design to fit > > (63 % of device) > > onto the device....see log file from synplify below. > > > > However, when I try to place and route the device in Quartus III, it > > cannot fit. > > Quartus uses the same project directory as Synplify so it has access > > to all constraints and tcl files. Can anybody shed any light on this > > subject. I have used Synplify in conjunction with Quartus before and > > the resource useage results > > from both are nearly always about the same. Why the large discrepency > > ? > > > > Do I manually need to read in some tcl files or have I forgotten to > > switch on > > a particular option in Quartus ? > > > > As always, thanks for any help > > Bob > > > > > > > > > > > > > > Found clock clk with period 33.3333ns > > --------------------------------------- > > Resource Usage Report > > > > Final cell packing will be performed by Max+plus II. > > Please select a Logic synthesis style of "FAST" in Max+plus II. > > The following resource values are estimates. > > > > Design view:work.comms(comms_architecture) > > Selecting part ep20k1000efc33-1 > > > > Logic resources: 24440 ATOMs of 38400 (63%) > > Number of Nets: 190215 > > Number of Inputs: 1298480 > > Register bits: 14312 (4094 using enable) > > Latch bits: 8106 > > ESBs: 0 (0% of 160) > > I/O cells: 0 > > > > Details: > > AND2: 8298 > > INV1: 3879 > > MUX1: 5834 > > SYNLPM_LAT1: 16356 > > S_DFF: 10218 > > S_DFFE: 4113 > > XOR2: 291 > > apex20k_lcell: 77185 > > apex20k_lcell_ff: 19 > > false: 7 > > inv: 9189 > > true: 7 > > > > Number of Inputs on ATOMs: 1298480 > > Number of Nets: 190215 > > > > Writing .vqm output for Quartus > > Writing Cross reference file for Quartus to > > c:\comms_vhdl\rev_1\comms.xrf > > Mapper successful! > > Process took 7284.92 seconds realtime, 7284.92 seconds cputimeArticle: 61581
Let's face it. The FPGA companies are really software companies that happen to
have very expensive dongles :-)
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61582On Tue, 07 Oct 2003 08:23:15 GMT, "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote: >So...I have this little module that creates an RLOC'd SRL-based delay pipe >that will feed one side of an adder in an FIR filter. Floorplanner confirms >that the RLOCs are working as promised. > >However, if I instantiate more than one of these modules, only the first one >is placed per the defined RLOCs and the rest are placed with SRL's and FF's >outside of the required relative locations. I've looked through every >report and I cannot find any warnings that would indicate that there's a >problem of any kind. > >I also wrote and compiled a simplified version of the above to see if >anything changed. The RLOC'd module consists of eight SRL's feeding eight >FF's, RLOC'd to form a column. I instantiated two of these to then feed an >8-bit adder that clocks out to 8 FF's. The layout I got confirms the >problem: The first module follows the RLOCs and the second does not. > >What's interesting is that section 7 of the MAP report lists two RPM's by >their set name (for the last example) but section 13's "Number of RPM >Macros" count is 1. > >Not sure where to go from here... Martin, Is keep_hierarchy on or off? Allan.Article: 61583
zaf wrote: > Hello members...i need urgent help with a digital design problem > > can some please help me expand the following function using shannon's > expansion theorem > > F = (A.B.C)' > = C' + A'C + AB'C > > I need to map this function to an Altera ACT 1 FPGA logic module with > three 2:1 MUX's and one OR Gate. > > any help would be greatly appreciated > > thanks > zaf You have by DeMorgan's Theorem that (A.B.C)'=A'+B'+C' so the cofactor wrt C is A'+ B', and the cofactor wrt A of A'+ B' is B'- so the Shannon expansion is C'."1" + C.( A'."1"+ A.B'), and this agrees with your expression. Now use Actel's "logic WHEEL" function to map it-) and you are 10% of the way there-)Article: 61584
Hi Martin, What kind of SET are you using? U_SET or HU_SET? Göran Martin Euredjian wrote: >So...I have this little module that creates an RLOC'd SRL-based delay pipe >that will feed one side of an adder in an FIR filter. Floorplanner confirms >that the RLOCs are working as promised. > >However, if I instantiate more than one of these modules, only the first one >is placed per the defined RLOCs and the rest are placed with SRL's and FF's >outside of the required relative locations. I've looked through every >report and I cannot find any warnings that would indicate that there's a >problem of any kind. > >I also wrote and compiled a simplified version of the above to see if >anything changed. The RLOC'd module consists of eight SRL's feeding eight >FF's, RLOC'd to form a column. I instantiated two of these to then feed an >8-bit adder that clocks out to 8 FF's. The layout I got confirms the >problem: The first module follows the RLOCs and the second does not. > >What's interesting is that section 7 of the MAP report lists two RPM's by >their set name (for the last example) but section 13's "Number of RPM >Macros" count is 1. > >Not sure where to go from here... > > > > >Article: 61585
Martin Thompson wrote: > "Plenolo" <plenolo@freemail.it> writes: > > >>Hi all i am new in the group, i am a italian student of computer science and >>i have hobbies for electronics, too... so i have using PIC, St6/7 >>microcontroller, etc.. now my dream is develop some circuit with fpga (or >>similar) and VHLD language. I have just a bit studing (only teorically) VHDL >>in my university, but now i would REALLY program some chip for develop some >>simple and medium project. >>I have not money (and i don't want :-) ) to buy some original developing >>system, so i would home build some free "programmer" (in-circuit JTAG ???) >>how i have do in pass for PIC / St6/7 programmers :-) >> > > > You'd be better off on comp.arch.fpga, for the actual hardware > questions - I've crossposted to there and set the followups to go > there also. > > Regarding programming hardware, Altera have the Byteblaster schematics > downloadable from their site, in the Byteblaster datasheet. I can;t > recall if Xilinx have similar. > > >>Thank you very much to all friends, and sorry for my very bad and poor >>english language :-) >> > > > It's better than my Italian! > > Cheers, > Martin > Hi Martin, Maybe the Chameleon POD can be a good start point for you. That's an small dongle with inside CPLD Coolrunner. You can use it for programming almost all processor on the market (From ARM, PPC to AVR and coldFire, ...) or you can customize the POD by your own VHDL code (I2C controller, PWM generator, motor control, ...). A great solution for small VHDL designs. www.amontec.com/chameleon.shtml All software is free. Regards, Laurent www.amontec.comArticle: 61586
Can someone suggest a project/application that would call for an XC2V6000-4BF957C? Thanks. -EmileArticle: 61587
Hal, Judge for yourself: http://www.xilinx.com/support/training/abstracts/adv-design.htm Describes the course, and what you should learn from it. Austin Hal Murray wrote: > >Perhaps a part of the registration process should require the students to > >email the teacher a list of their most important questions, or list what > >they're hoping to learn. > > If I knew enough to ask the right question I could probably find > the answer myself. Or ask here, or ... > > The main reason I go to a class is to learn something about a topic > when I don't know enough about it to ask the right questions. > > Another reason to go to a formal class is to get out of the office > and away from your phone/email so you can concentrate on learning > for long enough to make some progress. Sometimes you really do > learn things by going through "dumb" lab exercises. (Especially if > there is a good instructor who can answer questions when something > interesting happens.) > > ------ > > It sounds like the main part of Martin's comments was a mismatched > expectation about what "advanced" meant. Was there a good description > of the course? Did the course match the description? > > Did a bunch of students show up who weren't ready for an "advanced" > class? Maybe the instructor dropped back to their level without > noticing that a few people were ready for a tougher course. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.Article: 61588
In article <3f824f56$0$4845$afc38c87@news.optusnet.com.au>,
"Arthur Sharp" <arthur@nospam.com> writes:
<ise6.1 on Suse Linux>
|> I get the following error message :
|> Wind/U Error (294): Unable to install Wind/U ini file
|> (/media/cdrom/data/WindU).
|> See the Wind/U manual for more details on the ".WindU" file and the "WINDU"
|> environment variable.
I have copied the whole CD to hard disk first and started the setup in that
directory. It worked on Suse8.0. If you can find out which program causes the
message (run the script with "sh -x setup"), you can add a "strace " in front of
that command. Then you'll see all performed system calls and maybe the cause for
the problem...
|> After a while, a window appears saying "Warning : no data files were found
|> on CD image.
|> The installation will be terminated".
|> When I press ok, the installation finishes.
|>
|> The funny thing is that the directory "data" ((/media/cdrom/data/) on the
|> cdrom is empty on the CD I've got.
The same for me. The installation images are in idata.
--
Georg Acher, acher@in.tum.de
http://wwwbode.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 61589Brian, Comments below, Austin Brian Davis wrote: > Austin, > > > > >Sorry you are not satisfied with the agreement, and the positive > >response, and the acknowledgement and appreciation. > > > > I never said any of those things. > > I certainly appreciate your (and Peter's) time spent monitoring > the newsgroup. > > Thank you for the 'excellent list' comment. You are welcome. > > > I ( and any future users of the LVDS_25_DCI standards ) also > appreciate any prodding you can do to speed up the documentation > process so others can have a less painful experience. Will do. > > However... > > I stand by Item 13 as originally written. > > It is an alert to potential users of V2 differential I/O of > a critical component specification that they should be aware > of before starting a design. No problem: it is in the spec sheet, and users guide. An it is obvious in simulations. > > You disagreed with me on this issue, so in subsequent posts > I refuted the various arguments that you made contending that > the high V2 C_COMP value is unavoidable/not a problem/etc. It is. > > Instead of responding to my rebuttals, you changed the subject, > ignored those portions of my posts, and now threaten to take your > bat and ball and go home. Really? > > > > >No denial here. I explained why the capacitance is high. In fact, > why in must be high, and why > >we (and others) have no choice unless the LVDS inputs are dedicated > in their own bank, with no > >other standards attached (which no one wants in the FPGA world). > > > > Instead of ignoring my previous posts, go download the ORCA-4 > IBIS files, and take look at them: > > ALL OF THE GENERAL PURPOSE, NON-DEDICATED I/O STANDARDS HAVE > A C_COMP VALUE OF 2pf. > > If they can do it, why can't you? Since I can not see their data sheet (they block Xilinx domain), I have no means of verifying your claim. Have you simulated their IOB with IBIS? As I already said, when you can drive GTL, SSTL, HSTL, PCI all from the same IOB, you have to make some trade-offs. For dedicated inputs, it is not an issue (ie for the serdes). > > > I realize that the older families are unlikely to be improved, > but if Xilinx won't admit the problem, at least internally, > there's not as much hope for improvement in generation N+1. Get off that boat: I have admitted it many times now. It is you who seems to persist in dragging it on, and on, and on, and on, and on..... > > > > >Our parts meet the LVDS standard, they work. > > > What about the other specs I have mentioned, such as HyperTransport, > that have a tighter Cin or slew rate specification? Then we don't meet the "specs". Wasn't that simple? But we do interoperate, and many people choose to do so. > > > > >If you use them wrongly, they don't work. > > > They work just fine, but only with proper care and feeding. I think we are in "violent agreement." > > > > >As for wanting to "observe" the signal, that is about the best way to > mess it up (which you aptly > >point out). Rather than do that, how about using the existing > variable phase shift feature to > >measure the actual eye opening at the place where it counts: in the > FPGA? Our customers that do > >that are delighted that they no longer have to lose sleep over how > much margin they have: they > >measure it directly in the device itself. > > > > Amazing: I write a clear, concise (IMHO) explanation of how having > a BMFC on the device inputs make it impossible to probe, and you > blame the probe!!! No, it is just physics. Can't probe anyones 840 Mbs lines without affecting them. > > Life without probes is a fantasy: without a probe, I could have > run IBIS simulations from here to eternity without finding out > about the DCI amplitude modulation. Gee, I designed digital microwave radios for 5 years, and I never could "see" anything. Only could sniff at it with a spectrum analyzer. Everything was simulated. Guess where we are all headed? > > > The DCM phase shift is a very handy feature, but one must bear > in mind that any measurements made in such a fashion, such as your > SST IOB timing numbers, will also include DCM jitter. > > How is such an internal probe going to tell you anything about > the input waveform other than its' threshold crossing time? > What about amplitude, ringing, noise margin, or wacky, unexpected > problems like the DCI modulation? It all shows up in the error rate, and the timing margin. True, observing the signal is really nice (I try like hell to do that), but sometimes it isn't possible. For example, looking at the signal at the actual input itself is impossible, yet that is the only place where it counts. > > > > >You asked about the IBIS model, so I checked that. If the > coupled/uncoupled t-line are an issue, > >that is Mentor's responsibility. I hope you file bug reports with > them if that is the case. > > > > Ah, your response to this one quite aptly describes the > sophisticated, iterative IBIS model debugging process that > has been honed through years of industry experience: > > 1) Customer finds problem and calls IC vendor > 2) IC vendor blames simulator vendor > 3) Simulator vendor blames customer > 4) Goto 1 > > ( apologies for the sarcasm, but I'm tired of arguing about this ) Apology accepted, but I tried the model in a number of ways, and did not see a problem. Did it work for the simple t-line case? It did for me. > > > Brian > > Austin wrote: > > > >Brian, > > > >Wow. I agreed to move this up the list, and thanked you. Various CR > (change requests) are now in > >progress. > > > >I am so dissapointed. I agreed with you. I thanked you for putting > all of the items in a nice > >concise list. > > > >No denial here. I explained why the capacitance is high. In fact, > why in must be high, and why > >we (and others) have no choice unless the LVDS inputs are dedicated > in their own bank, with no > >other standards attached (which no one wants in the FPGA world). > > > >Our parts meet the LVDS standard, they work. If you use them > wrongly, they don't work. If you > >want 2pF inputs, go make your ASIC. That is how the ASIC/ASSP folks > try to lock us out of their > >markets. Unfortunately for them, there are plenty of folks who can > not afford their devices, and > >know how to properly simulate, and terminate and use capacitive > inputs. > > > >As for wanting to "observe" the signal, that is about the best way to > mess it up (which you aptly > >point out). Rather than do that, how about using the existing > variable phase shift feature to > >measure the actual eye opening at the place where it counts: in the > FPGA? Our customers that do > >that are delighted that they no longer have to lose sleep over how > much margin they have: they > >measure it directly in the device itself. > > > >You asked about the IBIS model, so I checked that. If the > coupled/uncoupled t-line are an issue, > >that is Mentor's responsibility. I hope you file bug reports with > them if that is the case. > > > >Sorry you are not satisfied with the agreement, and the positive > response, and the acknowledgement > >and appreciation. > > > >Austin > > > >Article: 61590
When I specify RLOCs in my UCF file manually, I have to associate a U_SET for each group to keep the RLOCs associated with the unique U_SET name. Are you using unique U_SET names for each instance of your module? Or are you using "hierarchical" HU_SETs? I haven't messed with those myself. Perhaps someone who regularly does RLOCs in their code can help explain how to make the groups unique and seperable since my experience hasn't touched on hierarchical RLOCs. "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:TJugb.12278$hT5.11925@newssvr25.news.prodigy.com... > So...I have this little module that creates an RLOC'd SRL-based delay pipe > that will feed one side of an adder in an FIR filter. Floorplanner confirms > that the RLOCs are working as promised. > > However, if I instantiate more than one of these modules, only the first one > is placed per the defined RLOCs and the rest are placed with SRL's and FF's > outside of the required relative locations. I've looked through every > report and I cannot find any warnings that would indicate that there's a > problem of any kind. > > I also wrote and compiled a simplified version of the above to see if > anything changed. The RLOC'd module consists of eight SRL's feeding eight > FF's, RLOC'd to form a column. I instantiated two of these to then feed an > 8-bit adder that clocks out to 8 FF's. The layout I got confirms the > problem: The first module follows the RLOCs and the second does not. > > What's interesting is that section 7 of the MAP report lists two RPM's by > their set name (for the last example) but section 13's "Number of RPM > Macros" count is 1. > > Not sure where to go from here... > > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > >Article: 61591
Bob wrote: > I re-synthesized the design again in Synplify and got the same result > as before so there is definitely some problem in the flow between the > two tools. It certainly looks like I'm back to the drawing board > design wise. > > If you can think of anything else, I would be very grateful. Maybe you can eliminate the flow between the tools. Try bypassing Synplify and process your source files directly with Quartus synthesis. -- Mike TreselerArticle: 61592
irum4@yahoo.com (irum4) wrote in message news:<bae769a6.0310070210.68f12baa@posting.google.com>... > H. Peter Anvin <hpa@zytor.com> wrote in message news:<blsls6$n8a$1@cesium.transmeta.com>... > > Followup to: <bae769a6.0310060635.580b510c@posting.google.com> > > By author: irum4@yahoo.com (irum4) > > In newsgroup: comp.arch.fpga > > > > > > > Check through *all* the bits in the configuration space header to make > > sure you match the specification. > > > > -hpa > Vendor ID & Device ID 0007524d (0x00 Device/Vendor ID) > Command &Status 02000187 (0x04 Command/Status) > 04800000 (0x08 Rev ID, Class Code) > 00008000 (0x0c Cache line, Lat timer, Hdr, BIST) > 0000bc01 (0x10 BAR0) > f4400008 (0x14 BAR1) > 00000000 (0x18 BAR2) > 00000000 (0x1c BAR3) > 00000000 (0x20 BAR4) > 00000000 (0x24 BAR5) > 00000000 (0x28 Cardbus CIS ptr) > 091e0000 (0x2c Subsystem/Subvendor ID) > 00000000 (0x30 Exp ROM base) > 00000000 (0x34 Cap. Ptr.) > 00000000 (0x38 reserved) > 00000103 (0x3c interrupt, grant, lat) Um, You've got completely stupid values for BAR0 and BAR1. Go re-read the PCI spec. --aArticle: 61593
Hi, I will try to explain it from my view. There exists an explanation on the RLOC in the ISE documentation. Look under RLOC in the constraint guide and you will see how it works. U_SET (User_SET) names have to be unique in the design and all RLOC attributes where ever they are specified in the design hierarchical works within the same U_SET name domain. ex. If you have a top level where you add a primitive to a U_SET (like X1Y0) and then in a submodule add another primitive to the same U_SET name with the values of (X1Y1) then they will be using the same co-ordinate system. But with HU_SET (Hierarchical User Set) or H_SET the submodule starts with a new co-ordinate system for each hierarchical level and so for each submodule you have to specify the relation between the level co-ordinate system and the submodule system. This makes it hard to down in a hierarchical design place a primitive close to another primitive in another branch of the hierarchical since you have to know all the relations of the co-ordinate systems between the two primitives. One difference between H_SET and HU_SET is with HU_SET you can give it a name instead of relying of the design hierarchical. The name has to be as for the U_SET unique within the design. Another difference is that with H_SET everything within a level with a RLOC is automatically in the set but with HU_SET, you have to manual assign the primitives to the SET (ala U_SET). Another way of looking at it is that U_SET flattens the hierarchical and all RLOCs within the same name uses the same co-ordinate system. HU_SET/H_SET preserves the hierarchical and each level has it's own co-ordinate system. Personally I only uses U_SET since it will give me one co-ordinate system independent where in the design I place something. The U_SET have the catch that you can only have one unique name in your design and if you want to have multiple instances, you need to name them differently. I have added a generic of the type string in my VHDL RPMs which the module uses as the U_SET name. For each new instance of the module, I give it a new name. Göran John_H wrote: >When I specify RLOCs in my UCF file manually, I have to associate a U_SET >for each group to keep the RLOCs associated with the unique U_SET name. Are >you using unique U_SET names for each instance of your module? Or are you >using "hierarchical" HU_SETs? I haven't messed with those myself. > >Perhaps someone who regularly does RLOCs in their code can help explain how >to make the groups unique and seperable since my experience hasn't touched >on hierarchical RLOCs. > > >"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message >news:TJugb.12278$hT5.11925@newssvr25.news.prodigy.com... > > >>So...I have this little module that creates an RLOC'd SRL-based delay pipe >>that will feed one side of an adder in an FIR filter. Floorplanner >> >> >confirms > > >>that the RLOCs are working as promised. >> >>However, if I instantiate more than one of these modules, only the first >> >> >one > > >>is placed per the defined RLOCs and the rest are placed with SRL's and >> >> >FF's > > >>outside of the required relative locations. I've looked through every >>report and I cannot find any warnings that would indicate that there's a >>problem of any kind. >> >>I also wrote and compiled a simplified version of the above to see if >>anything changed. The RLOC'd module consists of eight SRL's feeding eight >>FF's, RLOC'd to form a column. I instantiated two of these to then feed >> >> >an > > >>8-bit adder that clocks out to 8 FF's. The layout I got confirms the >>problem: The first module follows the RLOCs and the second does not. >> >>What's interesting is that section 7 of the MAP report lists two RPM's by >>their set name (for the last example) but section 13's "Number of RPM >>Macros" count is 1. >> >>Not sure where to go from here... >> >> >> >>-- >>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >>Martin Euredjian >> >>To send private email: >>0_0_0_0_@pacbell.net >>where >>"0_0_0_0_" = "martineu" >> >> >> >> > > > >Article: 61594
I have the Xilinx Virtex II Development Board sitting in front of me, and I am completely lost and need to get started soon. I have never worked with Xilinx FPGAs, so maybe some of you can share your expertise. The board comes only with the power-adaptor for the System ACE module. Questions: - How do I program the device? - Is it through the System ACE? - What cables do I need? - Where do these plug into? Any other tips on getting stared, I'm kind of lost. Thanks in advance.Article: 61595
Make sure you are preserving the hierarchy, it sounds like either the hierarchy
is being flattened or that you have overlapping RLOCs within the same Uset. I
generally don't use explicit USETs in my code, as I've had trouble on and off
with the tools properly passing them through. Look in your edif netlist to see
what it is doing. You should see one instance of your macro, and then multiple
instantiations of it in the main part of the code.
Martin Euredjian wrote:
> So...I have this little module that creates an RLOC'd SRL-based delay pipe
> that will feed one side of an adder in an FIR filter. Floorplanner confirms
> that the RLOCs are working as promised.
>
> However, if I instantiate more than one of these modules, only the first one
> is placed per the defined RLOCs and the rest are placed with SRL's and FF's
> outside of the required relative locations. I've looked through every
> report and I cannot find any warnings that would indicate that there's a
> problem of any kind.
>
> I also wrote and compiled a simplified version of the above to see if
> anything changed. The RLOC'd module consists of eight SRL's feeding eight
> FF's, RLOC'd to form a column. I instantiated two of these to then feed an
> 8-bit adder that clocks out to 8 FF's. The layout I got confirms the
> problem: The first module follows the RLOCs and the second does not.
>
> What's interesting is that section 7 of the MAP report lists two RPM's by
> their set name (for the last example) but section 13's "Number of RPM
> Macros" count is 1.
>
> Not sure where to go from here...
>
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
>
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_" = "martineu"
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61596
Have you tried increasing the effort level? If so, you might have to do
some floorplanning to improve the layout so that the routes don't get as
congested. As a last resort, you might also revisit the design to see
if you can re-architect it to have less global routing. The spartan3
and virtex2 parts really have quite an abundance of routing, so this
type of problem is much less common than it was with the 4K and earlier
families. Probably the most frequent causes of no route are: 1) use of
too many tbufs on a common bus line. These are relatively scarce and
require the tbufs to locate in the same row and in specific columns in
order to keep from eating up routing resources and killing performance.
The placer does a lousy job of placing the tbufs, so you'll probably get
much better results placing them by hand. 2) routing in/out of BRAM and
multipliers going to multiple places. These tend to congest the
routjng, and again, the placer does not do the greates job with these,
so they may be located away from the rleated logic and need routing
running across other dense areas.
Anjan wrote:
> Hi
> I have a design which takes about 74% resources on a sparta 3 1.5 m
> device.
> I am compiling on 5.2 sp3. The routing fails. In fact I tried lot of
> things but no use. Has anybody encountered similar problem. Thanks
> Rgd
> Anjan
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61597
I've used 2V6000's in several DSP applications including sonar and
radar beamformers.
Emile wrote:
> Can someone suggest a project/application that would call for an
> XC2V6000-4BF957C? Thanks.
>
> -Emile
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61598
Part of the problem is that they hire technical presenters that may or may not
have strong design experience. Obviously, if the presenter hasn't wrestled with
the tools on a real design, he is likely not going to be able to go too much
beyond what is on the slides. There is a good chance that the person teaching
the class learned the tools on the course materials and practiced with some
canned labs. I would want to know who the seminar presenter is and exactly what
his qualifications are before signing up for the course.
Also, Xilinx's idea of advanced design and a true expert's notion of the same
are quite different. Unfortunately much of the expertise carried by the guru is
the result of years of gruelling experience. While that experience can be
highlighted, there is not really any easy way to transfer such depth of
knowledge in a 2 day presentation. Xilinx used to use some of their "Xperts" to
teach these classes, and you got the luck of the draw. Some of these guys are
really good at teaching, some simply aren't. I don't know if they are still
using their XPERTs partners to teach or not, I suspect not since I have not
heard any requests to teach a seminar recently.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61599
Part of the problem is that they (not just Xilinx) hire technical presenters that
may or may not have strong design experience or a strong teaching background.
Obviously, if the presenter hasn't wrestled with the tools on a real design, he is
likely not going to be able to go too much beyond what is on the slides. There is
a good chance that the person teaching the class learned the tools on the course
materials and practiced with some canned labs. I would want to know who the
seminar presenter is and exactly what his qualifications are before signing up for
the course.
Unfortunately much of the expertise carried by the guru is the result of years of
gruelling experience with real designs. While that experience can be highlighted,
there is not really any easy way to transfer such depth of knowledge in a 2 day
presentation. It is also difficult to capture that experience and distill it into
a set of tips and rules that can be addressed in just two days. The presentation
material is generally not prepared by the presenter in most cases either: it is a
company wide presentation used by a number of presenters. Unfortunately, it has to
be that way in order to provide a standard course and still meet the fairly high
demand for the course. The problem of course, is that the material does not
necessarily match the presenter's experience. Some of the things in it will
invariably be new or done in a different way than the way the presenter handles
that problem, and some of the material will be perceived as the wrong way to do
things by some presenters. Hopefully the slides and any accompanying material
provide enough material to add value to the presentation, otherwise I doubt there
would be enough depth to have more than a feel-good value that would soon evaporate
after the class. The bottom line is that these 2 day wonder seminars can really
only serve to make you aware that there are techniques out there, and hopefully
give you guidance to find the information you need.
--
Mike Treseler wrote:
> Martin Euredjian wrote:
>
> > I'll have to respectfully disagree with some of what you said.
>
> That's what the newsgroup is all about.
>
> . . .
> > Then there's the issue of efficiency. I've taken a few very well taught
> > courses over the years where, within a few days, you go from a rudimentary
> > understanding of the subject to having a very clear and organized insight
> > from which to build. This isn't so much due to the verbal tradition I was
> > speaking of, but rather because someone who truly understands the subject
> > AND is a good teacher lays out the subject right there, in front of you, to
> > assimilate and build from. Good teachers are worth 1000 books. No doubt
> > about it.
>
> --
> I agree that instruction from a qualified and interested expert
> with recent industrial experience is ideal.
>
> The practical problem is finding such an expert who is
> also in the business of teaching.
>
> > So, if you attend a good course, you can be on your way very quickly. It's
> > a matter of efficiency. And, while it might be true that all in the
> > universe could be learned from books and, these days, the Internet, there's
> > a real imporant factor we must not forget: the business equation. If what
> > you do is a hobby then, by all means, burn time experimenting and reading
> > through hundreds of documents, surfing the Web or playing with dev boards.
> > However, in the context of a business that needs to get product out the
> > door, it is much more efficient to pay someone to show you the ropes quickly
> > and then get on with your work.
>
> --
> I agree that it makes good business sense to pay a
> consultant or take a course that teaches you something
> faster than you could learn in yourself. However, my
> experience with such seminars is that this just
> doesn't happen beyond the introductory tutorials.
>
> I set aside an hour or two a day for focused self-study, and
> I don't believe this has adversely affected the time
> it takes me to get working designs out the door. In fact I
> think it helps.
>
> > Let me ask you this. Do you think that spending 45 minutes listing all of
> > the I/O out of a DCM block has a place in an advanced class? Or how many
> > clocks can be distributed in a Virtex II?
>
> I agree with you. This is exactly what happens.
> This is where I walk out and why I no longer attend.
>
> > How about getting into how to
> > properly start-up a DCM with real-world issues and code?
>
> Yes. A little more *code* please.
> Design entry, inference, and simulation are routinely neglected.
>
> > $1,000 is a lot of money for a printed version of PowerPoint slides. I
> > would gladly pay $5,000 for a class that had the right content. Money is
> > not the issue here. If you tell me you'll teach an advanced class for $1K,
> > then do it. If that class requires $10K, then tell me so.
>
> Maybe other designers will post some good experiences with seminars or classes.
> I wish I had some to report.
>
> -- Mike Treseler
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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