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Settle down guys ..... Adam: Peter is right, XC5210 is an old device, 'not for new designs'. Down side is this has also made it a 'tool orphan', but if you go back far enough, there are tool flows for it. If Xilinx were like Borland, they would put this into a museum, but there are also side issues, like who owns all the code, which OS it can run on, and who will be lumbered with support ..... Peter: Adam may need 5V and/or low Icc of the simpler XC5210. A downside of the singular evolutionary focus on speed / die shrink, is that the voltage tolerance, and static Icc (and even startup Icc) have all taken hits. The XC5210 may indeed 'belong in the old folks' home', but it also illustrates that 'newer' spins do not guarantee better numbers. The CPLD sector _has_ woken to the importance of static Icc ( look at the spec-trading between Lattice and Xilinx on uA values in their newest cpld families ) Adam: Some newish devices do have 5V tolerant IOs ( see the other thread Re: SpartanXL ) Atmel still make low-end 5V FPGA devices, so they could be another candidate. Altera have some that have 5V tolerant IOs. You can design with single supply 5V FPGAs, but will pay more for the venerable devices, than if you add another regulator with a newish, cheaper device. (but not too new, or you loose 5V tolerance :) -jg Peter Alfke wrote: > > In a total time-span of seven hours and 29 minutes we have not been able > to come up with a satisfying answer. Shame on us ! > Peter Alfke > ============================================ > Adam wrote: > > > > I have to say I'm pretty disgruntled with Xilinx right now. I've > > talked to two people there so far, including a lengthy private email > > exchange with Peter, and nobody seems to want to tell me how to do > > this. Peter was unable to suggest a single newer 5V part, and was > > unwilling to tell me what tools can be used to program the older 5V > > parts. > > > > I'm beginning to look at other vendors; perhaps they support their > > customers a bit better than that. > > > > Peter Alfke <peter@xilinx.com> wrote in message news:<3F8C2262.633780A8@xilinx.com>... > > > Adam, why do you want to use such an old device? Unless you have very > > > special circumstances, it is best to throw away such old parts and > > > design with and for newer devices like Virtex and Spartan. > > > One year in the life of an FPGA equals 15 years in human life. That > > > means your 5210 really belongs in the old folks' home. > > > Rest assured that we still sell XC3000, 4000 and 5200 devices for > > > replacement purposes. But we discourage new designs with them. Newer > > > devices are so much better and cheaper, and supported by better software. > > > > > > Peter Alfke > > > =============== > > > Adam wrote: > > > > > > > > I have VHDL. I want to create a bitfile for a Xilinx XC5210. > > > > What tool(s?) do/can I use? > > > > > > > > I have ISE webpack 6.1, but it does not seem to support this device.Article: 61901
Here are some possible solutions: - If 5V tollerance will work, use SpartanXL. - If you need a true 5V device, use Spartan or XC4000E - Software for Spartan, SpartanXL and XC4000E is available for free at: http://www.xilinx.com/ise_classics/index.html - If you absolutely have to use the XC5200 family, you will need to get a copy of the XACT 6.0 software. You will probably need to contact our hotline to get this version. Steve Adam wrote: >I have to say I'm pretty disgruntled with Xilinx right now. I've >talked to two people there so far, including a lengthy private email >exchange with Peter, and nobody seems to want to tell me how to do >this. Peter was unable to suggest a single newer 5V part, and was >unwilling to tell me what tools can be used to program the older 5V >parts. > >I'm beginning to look at other vendors; perhaps they support their >customers a bit better than that. > >Peter Alfke <peter@xilinx.com> wrote in message news:<3F8C2262.633780A8@xilinx.com>... > > >>Adam, why do you want to use such an old device? Unless you have very >>special circumstances, it is best to throw away such old parts and >>design with and for newer devices like Virtex and Spartan. >>One year in the life of an FPGA equals 15 years in human life. That >>means your 5210 really belongs in the old folks' home. >>Rest assured that we still sell XC3000, 4000 and 5200 devices for >>replacement purposes. But we discourage new designs with them. Newer >>devices are so much better and cheaper, and supported by better software. >> >>Peter Alfke >>=============== >>Adam wrote: >> >> >>>I have VHDL. I want to create a bitfile for a Xilinx XC5210. >>>What tool(s?) do/can I use? >>> >>>I have ISE webpack 6.1, but it does not seem to support this device. >>> >>>Article: 61902
For the functions you are looking for (or close anyway) try Cypress Micro PSoC http://www.cypressmicro.com/ For the FPAA try Anadigm http://www.anadigm.com They might me close enough for what you are looking for. "Jos=E9 F. da Rocha" <jose_rocha@yahoo.com> wrote in message news:ee806ea.-1@WebX.sUN8CHnE... Hello. I'm new at the FPGA/CPLDs world and I'm currently subscribed to receive Xilinx email communications. I would like to know if is there some FPGA/CPLD incorporating some few analog functions or analog blocks like instrumentation amplifiers, OPerational AMPlifiers/(analog amplification), ADCs (Analog-to-Digital-Converter) and DACs? Thank you very much if you are kindly enough to answer. (jose_rocha@yahoo.com)Article: 61903
> Could anyone tell me of universities in the US that are strong in IC > design and/or DSP design? MIT Ga Tech StanfordArticle: 61904
john_doebertson@yahoo.com (Chip) writes: > How about using linear feedback shift registers instead of counters. > I've never actually used one so someone correct me if I'm wrong. Wouldn't make any difference. Either way you can cycle through all 216 combinations very rapidly.Article: 61905
> The original request reeked of 'late assignment'. I have to disagree with you. I think what we're seeing here is an enabling technology for a low latency, distributed, customer support system. Every time an end user has a problem with your equipment, instead of waiting on hold for a customer support representative, they receive immediate assistance by simply pressing a button and a 3-digit Instant Solution Code (tm) is generated. For example: Code #003 - Insufficient Memory The function you have chosen requires a Premium Platinum+ RAM Upgrade (tm). Internal diagnostics shows your equipment is a baseline model that contains only enough RAM to operate the Instant Solution Code (tm) functionality. Your local sales representative will be more than happy to assist you in improving your user experience. Code #012 - Undocumented Feature Congratulations End-User! You have discovered an undocumented feature. Please be kind enough to send us your day time phone number so we may forward to you all calls from other End-Users that also need to be educated. Win the adulation of your peers and support the user community today! Code #048 - Attention Deficit Disorder Please RTFM. Thank you. Code #192 - User Error Please forward the following message to your immediate supervisor: "Attention, I am a defective End-User. I do not meet the minimum system requirements. Please replace me with someone that has 5 more years of experience and a more advanced higher education degree, or two recent graduates." Code #768 - Product Defect You have possibly discovered a fault in our product. To be sure, press the Instant Solution Code (tm) button again to verify. If it generates Code #1000 then please contact us immediately. Otherwise, it's probably your fault. No longer does a user have to waste an inordinate amount of time becoming frustrated. Rather they can be frustrated immediately and use their precious time being productive in other ways. Forward thinking that keeps the customer's needs first is what will separate first class companies from second rate ones in this difficult economy. Regards, VinhArticle: 61906
Jim Granville <jim.granville@designtools.co.nz> writes: > No, but suppose this has a single push button ? > Each spin is going to be close to random, but the designer might be > a tad dissappointed at the correlation _across_ the 3 displays ? Why would there be a correlation? You hold the button for tens or hundreds of milliseconds, and the display will cycle through all 216 possible combinations in less than a microsecond. There will be no measurable correlation between the individual dice unless the counter doesn't work correctly.Article: 61907
> indicators with a simple counter ( three mod 6 counters cascaded). > The counter goes through all its 216 values once per microsecond, and I Why are we assuming that he's simulating six-sided dice? He could be talking about 1d4 or 1d8. Are there no gamers among us? Hmm then again a two-handed sword does 3d6 damage, so 1d6 would make sense. I have underestimated by peers. --VinhArticle: 61908
Eric Smith wrote: > > Jim Granville <jim.granville@designtools.co.nz> writes: > > No, but suppose this has a single push button ? > > Each spin is going to be close to random, but the designer might be > > a tad dissappointed at the correlation _across_ the 3 displays ? > > Why would there be a correlation? You hold the button for tens or > hundreds of milliseconds, and the display will cycle through all 216 > possible combinations in less than a microsecond. There will be no > measurable correlation between the individual dice unless the counter > doesn't work correctly. You are right - I missread Peter's example, and did not register the word cascaded. -jgArticle: 61909
I am urgently in search of a simple project that will demonstrate on the old Xilinx Spartan XCS10. Any intro to medium sized project that can perform functions on the demo board Digilab XLA5 at http://www.digilentinc.com/Catalog/digilab_xla.html with the LEDs and 7 SEG displays being utilized would be desirable. Examples may include simple timers, counters, traffic light controller, etc etc. I know this is a long shot, but I am desperate!! The files would need to be able to run on Xilinx Foundation 4.2i or equiv if possible. Schematic design entry would be preferrable over VHDL but not essential. Apologies to the experts in this NG and if I am looking in the wrong places can anyone suggest where else to look/ask/beg? A negotiated fee can be arranged through Kasamba.com. Anyone genuinely interested or that can help please email me direct. Kind Regards (and apologies for being of no help to anyone in a NG!!) DArticle: 61910
Arizona State University Electrical Dept, is good in IC design. brad@tinyboot.com (Brad Eckert) wrote in message news:<4da09e32.0310140810.50c39d21@posting.google.com>... > Hi all, > > Could anyone tell me of universities in the US that are strong in IC > design and/or DSP design? > > -- Brad Eckert > brad1.methinksnot@tinyboot.comArticle: 61911
In article <VA2jb.12306$ZH4.3057@twister.socal.rr.com>, Vinh Pham <a@a.a> wrote: >> indicators with a simple counter ( three mod 6 counters cascaded). >> The counter goes through all its 216 values once per microsecond, and I > >Why are we assuming that he's simulating six-sided dice? He could be >talking about 1d4 or 1d8. Are there no gamers among us? Hmm then again a >two-handed sword does 3d6 damage, so 1d6 would make sense. I have >underestimated by peers. It's a seven segment display, so it might be up to 1d16 To do it right, it would have to be a programmable (by DIP switches) between 1d2 and 1d16. Bonus points for only allowing configurations where an actual polygon would make a legal die (all sides the same area). -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 61912
Hi all, I am interested in doing partial reconfiguration using Xilinx Virtex 2 pro, i am having a HW AFX xilinx prototype baord. I tried the small bit manipulation method defined in Xilinx application note xapp290, with the simple example , Example 1 simple system desing from xilinx EDK examples web page. Ok , my desing is this, I am using PPC405, and uartlite and gpio with uart continiously writing some data in Hyper terminal and gpio is connected to four leds and writing '1' to it I tried to change the routing for the LEDs , I do have to mention here, my board has 8 user LEDS, i changed the routing from upper half to lower half and generated the partial bit stream. Everything goes well so far, but when i download this partial bitstream into FPGA, my uart stops putting out data, but LEDS gets rerouted and now the lower half LEDs o/p '1'. I would like to know wether what i am trying to do was right, also if anybody worked on small bit manipulations, I would appreciate their comments and advice. Thank you for the posting me a reply. bye RamArticle: 61913
no need to. The cycle time is short if clocked fast enough and the human interface injects enough
randomness to achieve a random result. See Peter's post above.
Why seven segment LEDs though? It would be more appropriate to use 7 LEDs arranged like the 'six' and 'one'
sides of the die superimposed.
Chip wrote:
> How about using linear feedback shift registers instead of counters.
> I've never actually used one so someone correct me if I'm wrong.
>
> They could be driven by a single clock. They each could be
> initialized with a different seed and could be long enough to run for
> a long time before repeating. They would still be coupled in the
> respect that each time the electronic dice is powered up each shift
> register will output the same pseudo random sequence. Then a roll
> consists of registering some of the lfsr bits when the dice button is
> released (the lsfr is still changing while the button is not pressed)
> Thus, if you could roll the dice at exactly the same times throughout
> an entire game you would get the same (pseuorandom) sequence of dice
> values. (But this would be highly unlikely)
>
> lange360@hotmail.com (Amstel) wrote in message news:<56f7756d.0310140824.7d8fe744@posting.google.com>...
> > Hi to all,
> >
> > I'm trying to make an electronic dice (3 die). Basically the dice has
> > 3 seven-segment displays and the 3 dice values will run randomly so
> > that we would always get different values combinations. However I
> > tried and was unable to write the program in VHDL .
> >
> > I need help urgently ..
> > Anyone know how to write the program ?
> >
> > Thanks a lot :-)
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61914> It's a seven segment display, so it might be up to 1d16 ... > between 1d2 and 1d16. Bonus points for only allowing configurations > where an actual polygon would make a legal die (all sides the same > area). Whew. I was freaking out for a moment there. I thought there was a gap in my gaming lore, that I had somehow gone through life ignorant of the 16-sided die :_)Article: 61915
A 5210? Yuck. The 5200 series is arguably the worst thing that Xilinx put out in its
history, which is why it was so short lived. If you need 5v, use a 4000E or Spartan. If
low power is important, then look back to the 3100, that is if you really need to use
legacy parts. For 5200, and if I remember right 3100 you'll need to go all the way back to
XACT 6, which also means you need to find a machine that runs windows 3.1. The xact 6
command line worked for most stuff under win95, but as I recall not all of the gui stuff
did (such as the floorplanner). I think Xilinx still has M1 tools available for download
that support the 4000E and Spartan lines.
Steve Lass wrote:
> Here are some possible solutions:
>
> - If 5V tollerance will work, use SpartanXL.
> - If you need a true 5V device, use Spartan or XC4000E
> - Software for Spartan, SpartanXL and XC4000E is available for free at:
> http://www.xilinx.com/ise_classics/index.html
>
> - If you absolutely have to use the XC5200 family, you will need to get
> a copy of the XACT 6.0
> software. You will probably need to contact our hotline to get this
> version.
>
> Steve
>
> Adam wrote:
>
> >I have to say I'm pretty disgruntled with Xilinx right now. I've
> >talked to two people there so far, including a lengthy private email
> >exchange with Peter, and nobody seems to want to tell me how to do
> >this. Peter was unable to suggest a single newer 5V part, and was
> >unwilling to tell me what tools can be used to program the older 5V
> >parts.
> >
> >I'm beginning to look at other vendors; perhaps they support their
> >customers a bit better than that.
> >
> >Peter Alfke <peter@xilinx.com> wrote in message news:<3F8C2262.633780A8@xilinx.com>...
> >
> >
> >>Adam, why do you want to use such an old device? Unless you have very
> >>special circumstances, it is best to throw away such old parts and
> >>design with and for newer devices like Virtex and Spartan.
> >>One year in the life of an FPGA equals 15 years in human life. That
> >>means your 5210 really belongs in the old folks' home.
> >>Rest assured that we still sell XC3000, 4000 and 5200 devices for
> >>replacement purposes. But we discourage new designs with them. Newer
> >>devices are so much better and cheaper, and supported by better software.
> >>
> >>Peter Alfke
> >>===============
> >>Adam wrote:
> >>
> >>
> >>>I have VHDL. I want to create a bitfile for a Xilinx XC5210.
> >>>What tool(s?) do/can I use?
> >>>
> >>>I have ISE webpack 6.1, but it does not seem to support this device.
> >>>
> >>>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61916Hi all, I am trying to do partial/dynamic reconfiguration using virtex 2 pro. I am working with xilinx tools since this MAY, i have gone thro a steep learning curve, to get to do some system design using EDK and some partial reconfig. whenever i call xilinx engineers at hotline for other help, i would ask themg them is there any other document than xapp290 that explains more abt this stuff.I might be wrong too, the document might explain well, but for a beginer like me, it still seems to be more theoritical than practical. sometimes i feel, the documents keep threading one after other,leads to quesitioning myself will this take ever to do this. I would like to get advice from experienced people how do they go abt like solving the trouble i am facing. thanx for the advice bye RamArticle: 61917
Ah, the clues were there! 'UK' anywhere in the post is a giveaway! Bloody island monkeys! Cheers, Syms. Peter Alfke <peter@xilinx.com> wrote in message news:<3F8C5BC4.641FA8DA@xilinx.com>... > I admit, my "irony detector" was temporarily asleep, and the German > seriousness took over... > But the scare story was really so neat. > Beware of these super-urgent class assignments! > Peter > ================== > Nial Stewart wrote: > > > > Peter Alfke <peter@xilinx.com> wrote in message > > news:3F8C3A8E.46F71A51@xilinx.com... > > > Hi, Jonathan, let me disagree. > > > I would run this with a single 200 MHz oscillator, and drive the > > > indicators with a simple counter ( three mod 6 counters cascaded). > > > The counter goes through all its 216 values once per microsecond, and I > > > am sure that the human hand cannot cheat with fractional microsecond > accuracy. > > > > > > Peter Alfke > > > > Peter, > > > > Was Jonathan not being ironic? > > > > The original request reeked of 'late assignment'. > > > > Nial. > > > > ------------------------------------------------ > > Nial Stewart Developments Ltd > > FPGA and High Speed Digital Design > > www.nialstewartdevelopments.co.ukArticle: 61918
Did you install the service packs I had some similar problem where my earlier synthesised design gave me error after re installation.I found that i didnt load the service packs. Hope this works for you Ram Jon Elson <jmelson@artsci.wustl.edu> wrote in message news:<3F8C7292.6000008@artsci.wustl.edu>... > Patrick Robin wrote: > > >Hello, > > > >I have been using Web ISE for over a year to program Xilinx CPLDs > >XC9572XL > > > >Everything was working fine for hundreds of units until my computer > >crashed and I had to resinstall ISE. I now get a "Programming failed" > >error. Everything else seems to work as far as communicating with the > >chip using the parallel cable. Impact detects the chip, I can query > >the ID compute the checksum (zero) and erase it fine. > > > >But I get the "Programming failed error" when I try to program chips. > >I tried a number of brand new CPLDs. Is there a way to get more > >specific error messages. At this point there are many variables since > >I had to resintall Windows XP and ISE. > > > > > You didn't change the computer, did you? Some motherboard parallel port > chips do not work well AT ALL with the parallel cable III. I have clearly > demonstrated it is the motherboard, as I can swap out the computer, > using all > the other hardware exactly as it was, and get a perfect programming > every time. > I think it is MB's with the UMC parallel port chip that have the problem. > > JonArticle: 61919
> How about using linear feedback shift registers instead of counters. One thing to keep in mind is that the LFSRs we mostly hear about are usually base-2. So if you're trying to emulate a 6-sided dice, you'll have to pick another number if an invalid value comes up. I have seen a base-5 LFSR combined with a base-2 one to create a base-10 one. I suppose you could do the same thing with a base-3 and base-2 for a six sided dice. I don't know the math involved in designing non base-2 LFSRs though. Plugging "lfsr gf(p)" into Google shows some promise but most of it is pretty math heavy and hard to read. gf() stands for Galois Field. I suppose there's no real difference with base-2 LFSRs. There's some sort of polynomial that dictates the taps for the LFSR and your adders are modulo-p instead of modulo-2 perhaps? Hopefully someone else can explain it more clearly. --VinhArticle: 61920
Hi,
I just got the following error today. I was compiling it yesterday with Xilinx ISE webpack 6.1, and don't know what caused this change. DELAYED attribute is unsupported? Has anyone hit that problem?? The following is the error, and after that is the source. Thanks.
ERROR:HDLParsers:1502 - c:/programs/vhdl/ise6/test.vhd Line 14. The
predefined attribute delayed is unsupported
tdtfi(vhdl) completed successfully.
Release 6.1.01i - spl2sym G.24
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Completed process "Create Schematic Symbol".
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
port(in_a: in std_logic; out_a: out std_logic);
end test;
architecture Behavioral of test is
signal in_a_delay: std_logic;
begin
in_a_delay <= in_a'delayed(1 ns);
process(in_a_delay)
begin
out_a <= in_a_delay;
end process;
end Behavioral;
Article: 61921Hi Eric, How will the core behave if the host will issue a type 1 configuration cycle while selecting the xilinx device with IDSEL? Can my internal logic sniff configuration transaction on the PCI bus? ThankX, NAHUM Eric Crabill <eric.crabill@xilinx.com> wrote in message news:<3F8C5BF0.CBC8810E@xilinx.com>... > Hello, > > > Well it is not just a bridge, and thats why I cant buy an ASSP. > > Fair enough. > > > In the Half Bridge application note from Xilinx, there is specific > > chapter dealing with bridging between several PCI-X cores. I do not > > need the core to be fully PCI bridge compliant, nor have PCI bridge > > configuration header within it. What I need is that the core will > > capture type 1 configuration cycles and reflect them on the user > > application side of the core. In this way I could have my own logic > > to translate those transactions to type 0 configuration transaction > > on other busses I have connected to our FPGA. > > The Xilinx PCI and PCI-X LogiCORE products do not accept Type 1 > configuration cycles. They can, however, generate both Type 1 > and Type 0 configuration cycles. This makes them suitable for > host bridge designs. It makes them unsuitable for the type of > design you described. > > You may ask, then, what the application note is referring to when > it discusses bridging bus segments. That application is for making > a "cross-link" bridge between two bus segments, where there is > already a host for each segment. I will admit that the document > is not entirely clear on this point, and I have asked the authors > to correct the application note. > > If you are interested in pursuing your desired application, you > should contact your Xilinx FAE, who will be able to assist you. > > Good luck, > Eric > > > > Hello, > > > > > > To get a better answer, you'll have to be more specific > > > about what you want to build. Are you trying to build a > > > fully compliant PCI(-X) to PCI(-X) bridge? If that is > > > the case, you should buy an ASSP to do the job. > > > > > > The Xilinx PCI and PCI-X LogiCOREs, as you might buy them > > > over the web, have Type 0 configuration spaces and are not > > > suitable for compliant bridging applications. However, > > > there are other options and it depends on what you are > > > trying to do. > > > > > > What exactly are you trying to do? > > > Eric > > > > > > > Hi. > > > > > > > > I'm considering Xilinx LogiCORE PCI-X core, and Xilinx > > > > HalfBridge core for building a PCI-X bridge. > > > > > > > > Can anyone share experience with these cores for PCI bridge > > > > application? Does these cores deal with the address > > > > translation from "type 1" to "type 0" ? > > > > > > > > Thankx > > > > NAHUMArticle: 61922
Hi Ivan, They both work but not perfect but you will get your EPCS1/4 programmed at least. The japanese page shows how you can rebuild your old byteblasterMV into a BB2. The only thing you don't get is 1.5V operation (one of the reasons for upgrading to BB2). Depending on how many systems you need to build a simpler way to do this is to use a Nios system and download the Flash image trough the serial interface (comming with the SOPC builder), the you can rip the ByteblasterMV schematic straight of the datasheet. Cheers FredrikArticle: 61923
> I'm trying to make an electronic dice (3 die). Basically the dice has > 3 seven-segment displays and the 3 dice values will run randomly so > that we would always get different values combinations. However I > tried and was unable to write the program in VHDL . Use an LFSR type pseudo random number generator (PRNG). [you will find a lot of documentation and VHDL example code in the crypto community, just google for the two acronyms]. Clock it at an arbitrarty rate. Write VHDL code to convert the output of the PRNG into dice values. Probably the easiest is to take 3 bits of output to form 1 dice value (0-5 => 1-6) and flag the other states as illegal. Clocking the PRNG should not stop until all 3 dice are legal. That solves the bias-by-mapping problem without adding lots of complexity to the logic. Write code to output the dice value on the 7-seg LCD. Write code to stop the PRNG on user request (respecting the legal state thing mentioned above). Quite easy once you know how to do the "random" portion of it. MarcArticle: 61924
> John wrote: > > > > I would like to obtain a hard copy of the Programmable Logic Design > > Handbook (featuring FPGAs and CPLDs). I cannot find one listed on the > > Xilinx web site, though I might have missed it. The downloadable pdf > > probably works for most people, but I prefer having a book to thumb > > through. Thanks, > > John Forgot to reply first time around, and can't find the original posting, but... if you don't mind paying money you could try these people: http://www.printme.com/ They will take a PDF from you and ship a booklet to you. Haven't used them myself (they won't ship outside the US currently - so they might not be any use to you either) If you decide to use their service, I'd be interested in finding out how they do! -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt
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