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Pratip Mukherjee <pratipm@hotmail.com> writes: > I am looking for PicoBlaze (or similar) processor implementation for Altera > ACEX1K FPGA. The NIOS (16-bit < 1000 logic elements) should fit into the larger members of the ACEX1K family. Check out: http://www.altera.com/products/devices/nios/overview/nio-overview.html Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 62476
"Peter Alfke" <peter@xilinx.com> ha scritto nel messaggio news:3F9FF64E.CD3D238B@xilinx.com... > This discussion has not mentioned the best protection in > any FPGA: > All Xilinx Virtex-II devices have an on-chip decryptor > that can decrypt > a triple-DES encoded bitstream, using an on-chip stored > 3x56-bit key. > This key is kept alive with a small external battery. Another solution (more suitable for smaller devices, even if slightly less secure) could be to use a private-public key algorithm, like PGP: you encrypt the bitfile with the public key, and the FPGA decrypts it with the private key. The private key would be the same for all the devices (or a "group" of devices), so you could "hardwire" the decode logic and save costs and space. -- LorenzoArticle: 62477
hmurray@suespammers.org (Hal Murray) wrote in message news:<vq0q8120q03379@corp.supernews.com>... > > That idea of shipping the SIM separately to the > >end-users, so that the (contract) manufacturer cannot sell units on > >the side, also has merit. > > How much of a problem is that? > > I'd think that major US based contract manufacturer would be > very careful. It would be a serious damage to their reputation > if something like that happened and word about it got out. No problem in the US. China is another story, where IP rip-off is business as usual. Cultural change doesn't happen overnight. If you boot from parallel EPROM, you usually need a CPLD. If the CPLD has a little logic left over, an authentication algorithm can be implemented between the CPLD and FPGA. Ship the manufacturer enough pre-programmed CPLDs for the build.Article: 62478
I am looking for new tools for FPGA development and wonder if someone has a comparison of different tools available (everything needed from source to bit configuration code) I like to combine schematics for rough block diagrams and macros for more schematics, VHDL and/or 'C' based language synthesis. I have mainly used the old Xilinx Foundation package (It is still OK but not longer supported) and I have tried the ISE tool but don't like the schematic drawing part. For Xilinx FPGA's, does there exist more than xilinx's own place & router? Are there any 3rd party more effective PAR tools? I also want to compare prices.Article: 62479
Jean-Francois, Use the DCM reset. It may be that the DCM is unable to use the input clock immediately after DONE goes high, and the DFS part of the DCM is unable to LOCK. This is a fairly common start up issue with many oscillators, and for that reason we recommend connecting the reset to the local chip logic reset, or to some other circuit that checks the LOCKED bit, the CLKFX_STOPPED bit, and the CLKIN_STOPPED status bits so you know when the DCM has had a hiccup (due to the external clock) and can restart it. Austin jean-francois hasson wrote: > Hi, > > In the design I am working on there is (for the moment) a DCM > generating a CLK0, CLK2X and CLKFX outputs with CLKIN being 40 MHz and > no reset on the RST pin of the DCM (tied to VCC). All seems fine > during functionnal simulation but on the board the CLKFX does not > toggle (STATUS<2> of DCM is high but the LOCK is high too !?!). What > is confusing among other things is that a previous version of this > design was previously working fine on the board regarding this clock > at 160 MHz (clkfx). The difference between this failing version and > the previous one that I can think of is the fact that a fair amount of > logic has been added otherwise same board, same fpga, same clocking > scheme, ... If anyone can give me a piece of advice that would be of > great help. I will do further inverstigation in the mean time. > > Thanks, > > JFArticle: 62480
> 2) Where do I get a free VHDL compiler? Does it come with the free > tools from Xilinx and/or Altera? Or do those free tools simply work > with other vendors' compilers? The whole tool situation is completely > confusing to me. All suggested Xilinx tools. However, Altera Quartus, the free web edition, also supports VHDL (now) and you can do the simulation after routing (a little bit different than VHDL simulation). > 4) I'd also like to find what I guess I'd call prototyping boards, > with my meaning of the difference being that an evaluation board would > have enough hardware to make for a reasonable development environment, > while a prototyping board would be a cheaper and smaller board using > the same FPGA for one-off or very low volume projects. You can find a long list of boards at http://www.fpga-faq.com/FPGA_Boards.shtml (where my Cyclone board is also listed ;-) > 6) Eventually I'd like to learn enough to be able to design a simple > CPU core. Is this a reasonable goal for an after-work "hobby"? How > big are e.g. 8-bit CPUs like the 6811, Z80, AVR, etc, in lines of > code, and FPGA real estate? (measured in gates? is that the standard > unit of chip real estate?) > Alter Nios 32-bit RISC or my Java processor are about 2000 LE (logic elements). A LE is usually a flip-flop with a 4 bit LUT. Estimating gate count in FPGAs is problematic. The mentioned 2000 LEs are about 30% from a low cost FPGA (about $ 30,- for single q.) EP1C6. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 62481
Robert, V2/2Pro TAP state doesn't get reset with the pulsing of the PROG pin. Please clock in 5 '1's on TMS to ensure the TAP state is properly reset. Regards, Wei RobertP wrote: > I know that for Virtex, Virtex-E, and Spartan-II devices, TAP controller > is held in reset state when PROG pin is low. This results that JTAG > chain cannot be used then. > This was not the case for older devices (Spartan). > Anybody knows how what's the situation in newer devices (I'm > particularly curious about Virtex II )? > Thanks. > > -- > Robert >Article: 62482
I wrote a VHDL program and loaded it into a Xilinx XC95108 chip , unfortunately , the chip's memory is unable to store the VHDL Program . The VHDL program size is too huge . I was wondering what's the maximum number of Flip-flops & Gates the XC95108 can store ? I need this information . Can anyone tell me ? Thanks for the help .Article: 62483
Kolja, let's maintain some common sense here.
I only commented on Uwe's doubt about availability (250 days), and I
countered with "250 minutes", actually much less than that, since the
3S1000J has been available for weeks.
BTW: "J"only refers to a of 3.3-V tolerance, to be fixed in the final release.
This whole discussion has really deteriorated because the time factor
("end of 2004") has been ignored.
'nuf said.
Peter Alfke
=======================
Kolja Sulimma wrote:
>
> Peter Alfke <peter@xilinx.com> wrote in message news:<3FA01AE9.BFCBD7A1@xilinx.com>...
> > Uwe Bonnes wrote:
> > > If everyone of this team of 250 could contribute one day of lead time we
> > > could also get in a time frame where the parts are really available on the
> > > market :-)
> > >
> > One minute per team member would be sufficient. :-)
> > Peter Alfke
>
> Which really is a contradiction to Austins post who essentially
> explained the price difference with a 6 Month delay before purchase.
>
> You are suggesting that in 250 Minutes the 250k price is going to drop
> to 12$ but I doubt that the Avnet price is going to drop today.
>
> So there would be a factor of 16 volume discount compared to a 1k
> price.
> I believe you agree that this is unusual?
>
> Kolja Sulimma
Article: 62484Markus Zingg wrote: > Hi Peter > > Thanks for your reply. This sounds like a good solution too. The > battery aproach is a bit two folded. On one hand it may adds security > in that if someone would tamper with the device and power would be > interupted the key is lost. On the other hand there are the added > costs of such a battery and also the not always so consistent > livespan. In other words the user would not even be able to replace > this battery or in other words, once the battery is low the product is > trash - right? > It's much better: The battery, including its holder is <$2. And you can remove the battery and exchange it for a new one anytime normal Vccint powers the chip. The battery comes into play only when Vccint is low or zero. Peter AlfkeArticle: 62485
>. The VHDL program size is too huge . I was wondering what's the >maximum number of Flip-flops & Gates the XC95108 can store ? Look in the data sheet. The number of FFs should be simple. The number of gates is (much) more complicated. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 62486
The 108 has 108 cells. Each has a FF. Steve "Bose" <blueforest2@yahoo.com> wrote in message news:a395f2ee.0310300837.15cfe2d6@posting.google.com... > I wrote a VHDL program and loaded it into a Xilinx XC95108 chip , > unfortunately , the chip's memory is unable to store the VHDL Program > . The VHDL program size is too huge . I was wondering what's the > maximum number of Flip-flops & Gates the XC95108 can store ? I need > this information . Can anyone tell me ? > > Thanks for the help .Article: 62487
"Valentin Tihomirov" <valentin@abelectron.com> wrote in message news:bnr8f1$154qe7$1@ID-212430.news.uni-berlin.de... > I need to check a vaue after AVAIL rises to '1'. But the following test > shows that simulator ignores ASSERT clauses placed between WAIT forever > statement. > > Rx <= '1'; wait for 1 * BIT_TIME; -- initialize a bit value > > wait until AVAIL = '1'; -- wait for condition > > > -- these assertions are ignored by simulator! > > assert (Rx = '0') -- fail if bit = '1' > report "Invalid data received1!" > severity failure; > > assert (Rx = '1') -- fail if bit = '0' > report "Invalid data received2!" > severity failure; > > wait; -- will wait forever Are you 100% sure that AVAIL is making a transition to '1' at some time after the previous wait has finished? Don't forget that "wait until" is EDGE triggered. It will wait forever if AVAIL is stuck at '1'. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 62488
Lorenzo Lutti wrote: > Another solution (more suitable for smaller devices, even if slightly less > secure) could be to use a private-public key algorithm, like PGP: you > encrypt the bitfile with the public key, and the FPGA decrypts it with the > private key. The private key would be the same for all the devices (or a > "group" of devices), so you could "hardwire" the decode logic and save costs > and space. Why would this be better for small devices, when the Virtex-II triple-DES decoder is free. It really is, since it is implemented in every device in a chip area you cannot use for anything else. That's what I call "free", you gain nothing by not using it. Well, you need a $1.00 watch battery... Peter AlfkeArticle: 62489
We have released two tutorials that show how to create FPGA designs
using Xilinx WebPACK 6.1:
http://www.xess.com/appnotes/webpack-6_1-xsa.pdf
This tutorial shows design examples for a SpartanII FPGA on an XESS
XSA Board.
http://www.xess.com/appnotes/webpack-6_1-xsb.pdf
This tutorial shows design examples for a SpartanIIE FPGA on an XESS
XSB Board.
At the risk of providing too much information, here is a list of topics
covered in these tutorials:
> This tutorial shows the use of the WebPACK tools on two simple design examples:
>
> § an LED decoder and
> § a counter which displays its current value on a seven-segment LED.
>
> Along the way, you will see:
> § How to start an FPGA project.
> § How to target a design to a particular type of FPGA.
> § How to describe a logic circuit using VHDL and/or schematics.
> § How to detect and fix VHDL syntactical errors.
> § How to synthesize a netlist from a circuit description.
> § How to fit the netlist into an FPGA.
> § How to check device utilization and timing for an FPGA.
> § How to generate a bitstream for an FPGA.
> § How to download a bitstream to program an FPGA.
> § How to test the programmed FPGA.
>
--
|| Dr. Dave Van den Bout XESS Corp. (919) 363-4695 ||
|| devb@xess.com PO Box 33091 ||
|| http://www.xess.com Raleigh NC 27636 USA FAX:(919) 367-2946 ||
Article: 62490
Mike Silva wrote:
> 1) I know I want to learn VHDL. I know this (or at least, I think I
> know this) because I've used C a whole lot, and Ada a little, and I
> vastly prefer Ada.
That gives you a leg up. VHDL is based on Ada.
> I read a comment here that while Verilog may be
> used more in the US for ASICs, VHDL is used more for FPGAs. If true,
> why is this?
History. ASICs and Verilog were first.
> 2) Where do I get a free VHDL compiler? Does it come with the free
> tools from Xilinx and/or Altera? Or do those free tools simply work
> with other vendors' compilers? The whole tool situation is completely
> confusing to me.
http://groups.google.com/groups?q=vhdl+modelsim+free+holz
> 3) For my situation, where ease of learning and a cheap but capable
> evaluation board are the important considerations, which company's
> free tools and which evaluation board should I get?
Consider waiting on picking a board until you've
learned the following using
google, a text editor, sim and synth tools:
1. Synchronous Design Techniques
2. VHDL language and testbench design.
3. VHDL subset for synchronous design.
> 5) Is it a fairly simple process to download VHDL modules floating
> about on the web and incorporate them? I am particularly fascinated
> by the notion of downloading a CPU core and building some goodies
> around it.
Free IP is not always well written or well documented.
Once you know how to design synth code, writing
your own may be faster than learning and fixing
the "free" code.
> 6) Eventually I'd like to learn enough to be able to design a simple
> CPU core. Is this a reasonable goal for an after-work "hobby"?
Yes, this is a common hobby project. Most VHDL texts have an example.
But consider that FPGAs are often designed in to do jobs that
CPUs can't handle efficiently.
-- Mike Treseler
Article: 62491"Peter Alfke" <peter@xilinx.com> wrote... > It's much better: > The battery, including its holder is <$2. > And you can remove the battery and exchange it for a new one anytime > normal Vccint powers the chip. The battery comes into play only when > Vccint is low or zero. We have been using a rechargeable lithium battery ($1.25 / 4mAh) that is soldered directly to the PCB. Add a low leakage diode and a current limiting resistor for a recharger circuit and you do not need to worry about replacement. The only requirement is that the board be powered up for a few hours every couple of years. The only issue that we have with this is that the batteries can't tolerate the oven, and must be hand soldered. Regards, Erik Widding. --- Birger Engineering, Inc. -------------------------------- 617.695.9233 100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.comArticle: 62492
In article <3FA06256.3B3F612B@xilinx.com>, Peter Alfke <peter@xilinx.com> wrote: >The simple answer is that it is impossible, since there is no >documentation about the function of the individual config bits. >The more sophisticated answer would be that is outrageously difficult >and time consuming. After all the detective work figuring out what >millions of individual bit are doing ( or not doing), you finally arrive >at a big unstructured circuit mess. Uh, sorry peter. Give me a normal bitfile and $200k to write the software the first time (overpay me) and I'll be able to back-annotate it at least to the placed EDIF netlist, as long as the architecture is supported by Jbits. Why reverse engineer the bitstream when Xilinx has already given a tool which can go from a bitstream to a model of the device at the PIP level, which can then be programmatically run back to the connection and LUT functionality level. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 62493
Here is a simple suggestion:
Your output frequency divided by your accumulator clock frequency is
0.0074327256 as displayed on my cheap calculator.
Just convert this decimal value into a binary fraction, and that gives
you the inputs to your accumulator. You can make the accumulator more
than 20 bits long to increase the average frequency accuracy, but you
will still get a jitter of one ~73 MHz clock period, which is roughly
0.7% of your output period.
If you absolutely need less jitter, there are tricks (like multiple
accumulators), but they get complicated and/or expensive.
Good luck.
Peter Alfke
===========================
Atif wrote:
>
> Hello all,
> I am generating the clock of frequency 548KHz from an input clock of
> 73.728MHz. I am using the Direct digital frequency synthesis DDFS
> technique from
> www.xilinx.com/xcell/xl31/xl31_32.pdf
> But I am getting the wrong output as;
> *************************************************
> Running...
> 929 929.134 t=0.000000
> 929.134period=929.134000
> 929.134t=929.134000
> freq=1076271.022264 HZ
> 2747 2746.71 t=929.134000
> 2746.71period=1817.576000
> 2746.71t=2746.710000
> freq=550183.321083 HZ
> 4578 4577.85 t=2746.710000
> 4577.85period=1831.140000
> 4577.85t=4577.850000
> freq=546107.889075 HZ
> Exiting VeriLogger Pro at simulation time 10000000
> 0 Errors, 0 Warnings
> Compile time = 0.00000, Load time = 0.04700, Execution time = 0.04700
>
> Normal exit
> ***********************************************************************
> Here is the code of my program:
> ***********************************************************************
> // Thanks to Jonathan Bromley for his valuable suggestions for the
> code.
> `timescale 1ns/1ps
> module fulladd28(out,clock,reset);
> parameter a=28'd1995207;
> parameter w = 28; // bit width of phase accumulator
> output out;
> input clock, reset;
> reg [w-1:0] sum;
> always @(posedge clock or posedge reset)
> if(reset)
> sum <= 0;
> else
> sum <= sum+a;
> assign out = sum[w-1];
> endmodule //end of module fulladd28
> module stimulus;
> wire OUT;
> reg CLOCK, RESET;
> fulladd28 myfulladd28(OUT, CLOCK, RESET);
> always@(posedge OUT)
> begin
> :freqmeter
> real t, period;
> period=$realtime - t;
> $display($time, " ", $realtime, "\t t=%f ",t);
> $display($realtime, "period=%f ",period);
> t=$realtime;
> $display($realtime, "t=%f ",t);
> $display("freq=%f HZ", 1000000000/period);
> end
> initial
> begin
> RESET=1'b1;
> #10 RESET=1'b0;
> end
> initial
> begin
> CLOCK=1'b0;
> forever #6.782 CLOCK=~CLOCK;
> end
> initial
> begin
> #10000 $finish;
> end
> endmodule //end of module stimulus
> ***********************************************************************
>
> Can anyone please guide me why is this deviation from the desired
> frequency and how to remove this? Is there any other accurate method
> of generating the desired frequency from the input one?
> I want the accuracy of 20ppm. The device to be used is
> Xc2s50-5PQ208-I.
>
> Thanks and Regards
> Atif Nadeem
> Research Associate
Article: 62494"Dave Vanden Bout" <devb@xess.com> wrote in message news:3FA148D7.FF7C45B4@xess.com... > We have released two tutorials that show how to create FPGA designs > using Xilinx WebPACK 6.1: (snip) > > Along the way, you will see: > > § How to start an FPGA project. > > § How to target a design to a particular type of FPGA. > > § How to describe a logic circuit using VHDL and/or schematics. > > § How to detect and fix VHDL syntactical errors. > > § How to synthesize a netlist from a circuit description. > > § How to fit the netlist into an FPGA. > > § How to check device utilization and timing for an FPGA. > > § How to generate a bitstream for an FPGA. > > § How to download a bitstream to program an FPGA. > > § How to test the programmed FPGA. I have downloaded it, but not tried it yet. I do wonder if there is any support for verilog? -- glenArticle: 62495
Hi all, Just wondering if anyone can clarify if TNMs propagate through the tristate control pin of a tristate buffer to any downstream flipflops/latches/RAMs/PAD. Or does the TNM path finish at the tristate control pin? Thanks KloadArticle: 62496
"Bose" <blueforest2@yahoo.com> wrote in message news:a395f2ee.0310300837.15cfe2d6@posting.google.com... > I wrote a VHDL program and loaded it into a Xilinx XC95108 chip , > unfortunately , the chip's memory is unable to store the VHDL Program One cannot load a VHDL program in a chip. What you load is a bitstream, which results from running first synthesis and then several implementation phases. If your design doesn't fit in a particular chip you know it when your implementation fails in one of the phases. When this happens you don't have a bitstream to load. So, I don't understand what and how you were trying to load?... /MikhailArticle: 62497
Glen Herrmannsfeldt wrote: > "Dave Vanden Bout" <devb@xess.com> wrote in message > news:3FA148D7.FF7C45B4@xess.com... > > We have released two tutorials that show how to create FPGA designs > > using Xilinx WebPACK 6.1: > > (snip) > > > > Along the way, you will see: > > > § How to start an FPGA project. > > > § How to target a design to a particular type of FPGA. > > > § How to describe a logic circuit using VHDL and/or schematics. > > > § How to detect and fix VHDL syntactical errors. > > > § How to synthesize a netlist from a circuit description. > > > § How to fit the netlist into an FPGA. > > > § How to check device utilization and timing for an FPGA. > > > § How to generate a bitstream for an FPGA. > > > § How to download a bitstream to program an FPGA. > > > § How to test the programmed FPGA. > > I have downloaded it, but not tried it yet. I do wonder if there is any > support for verilog? > > -- glen WebPACK supports Verilog. You will go through the same operations, dialogs, windows, etc whether you use Verilog or VHDL so the tutorial should still be applicable. The only added effort is to develop your own Verilog code to replace the VHDL already given for the LED decoder and the counter. -- || Dr. Dave Van den Bout XESS Corp. (919) 363-4695 || || devb@xess.com PO Box 33091 || || http://www.xess.com Raleigh NC 27636 USA FAX:(919) 367-2946 ||Article: 62498
"Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:bnrk3l$1pgu$1@agate.berkeley.edu... > In article <3FA06256.3B3F612B@xilinx.com>, > Peter Alfke <peter@xilinx.com> wrote: > >The simple answer is that it is impossible, since there is no > >documentation about the function of the individual config bits. > >The more sophisticated answer would be that is outrageously difficult > >and time consuming. After all the detective work figuring out what > >millions of individual bit are doing ( or not doing), you finally arrive > >at a big unstructured circuit mess. > > Uh, sorry peter. Give me a normal bitfile and $200k to write the > software the first time (overpay me) and I'll be able to back-annotate > it at least to the placed EDIF netlist, as long as the architecture is > supported by Jbits. Consider that, (from the Xilinx web site) there are Virtex2 devices with 125136 logic cells, and over 8 megabytes of configuration information. A hex dump of the configuration file, 80 characters per line, 60 lines per page, would be over 3000 pages long, and not readable by anyone. The netlist might be 100 times as long, or 300,000 pages. That is a stack of paper about 100feet (30m) tall. Now, say you print that out, and maybe wear out a few printers while doing it. Now you want to change one node. How long will it take to find that node? There are smaller devices, and maybe one could work their way through the netlist. I think, though, for anything bigger than an XC4002 it would be hard to get much useful information out of even a netlist. -- glenArticle: 62499
Well, I ran all the programs ( running fc2,design manager ... )and implementation and all phases were successful.It's only at the last stage where I have this problem,the chip's memory size is too small to store my vhdl program. By the way, the XC95108 has 108 cells , what are cells ? so the sc95108 can store 108 flip-flops ? Thanks for the help.
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