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Hi, Here is my question: Device: APEX EP20K1500 I use the on-chip PLL to convert 40MHz Xtal clock to 56MHz clock and want to watch this signal on oscilloscope. Can I bring the PLL's output directly to Pin_F1 of JP10 or indirectly to Pin_F1? I know I can bring the PLL's output to "clock output pin" (i.e. U31 or Y3), but, can I bring it to non-clock output pins? Thank you very much for your help! Yi Zhang ENQ Semi.Article: 63051
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:%gKsb.733$Nw.45922360@newssvr21.news.prodigy.com... > "Peter Alfke" wrote: > > > I like using BlockRAMs for unconventional applications > ... > > Is there an app note or techxclusives article listing unconventional uses of > BlockRAM's and multipliers? That could be useful to trigger some creative > thinking. The 234 character URL to the TechXclusives article is digested down to this: http://tinyurl.com/uvf1 The title of the article is "Using Leftover Multipliers and Block RAM in Your Design" - John_HArticle: 63052
Virtex-II supports "TBUFs", which behave like the tristate drivers on Longlines of the olden days. In physical implementation they actually are Mux structures that avoid the slowness of the classical TBUFs. So you could say that they are "virtual TBUFs". PeterAlfke ================ Vivek wrote: > > Hi, > > Does anybody know, whether Xilinx Virtex2 FPGA supports internal tristate? > (the tristate that can't be pushed towards the interface or pins). > > Thanks in advance, > > VivekArticle: 63053
Arash,
That won't work. Try drawing a timing diagram to see why!
cheers, Syms.
"Arash Salarian" <arash dot salarian at epfl dot ch> wrote in message
news:3fb3a9cf$1@epflnews.epfl.ch...
HI,
You didn't say anything about the frequency, so maybe for lower frequencies
one way is to cascade 2 of these 2f circuits to get a 4f frequency and then
using a simple flipflop to divide it by two, get a perfect 50% duty cycle 2f
signal.
Best Regards
Arash
"Gazelle" <wmu@pandora.be> wrote in message
news:S_vsb.20088$Q87.707719@phobos.telenet-ops.be...
Good day gents,
I am wondering if VHDL (or Verilog) code exists in
order to make a frequency doubler in a normal
CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric duty
cycle.
Below some code can be found which generates a by-2 multiplied frequency -
however the duty cycle
is very assymmetrical ...
Many thanks for your input !
Regards,
Michel
Article: 63054
Hey, i have this problem when i want to do the following thing:
I have this serial input (let's call it a) and i want to see the serial
input a through an IO provided on my evaluation board (let's call that pin
atest) and i did it like this
entity testmodule is
port(
a, clk: in std_logic;
b, atest: out std_logic
);
end testmodule;
architecture Behavioral of testmodule is
begin
-- the rest of the program to get a =>b
--with this process i want to feed the input a to and debug output atest
which it clocked on the clk (which is a lot
--faster than the serial clock so there should be no problem there
process(clk)
begin
if (clk'event and clk='1') then
atest<=a;
end if;
end process;
--OR can i just write the following;
atest<=a;
end Behavioral;
so i used a process to bring a => atest as a first method and then atest<=a
as a second method.
How come neither of these methods work??? did i miss something?
thanx in advance;
Yttrium
Article: 63055Doubling again and then dividing does not solve the problem. It just gets you back where you were. :-( Peter AlfkeArticle: 63056
We have here a very strange thing. Since the JTAG is a serial bus and since a jtag frame is complex (a big shifter register), you will have a JTAG chain working OK or KO, but not a result like your one. Also, this trouble is coming from software, at 99%. Make sure to use the last Xilinx software release and the last sp. Otherway, on hardware and if you have access, cut the jtag chain and connect the JTAG signals to have only the FPGA on and in seconde time only the EEPROM on. Laurent Gauch www.amontec.com Chen Wei Tseng wrote: > Kay, > > I assume that you were using initialize chain to detect the devices. I > also assume that you're using 6.1isp2 iMPACT to perform configuration. > When iMPACT performs chain initialization, only TMS and TCK are toggled. > Take a look at Xilinx soln 11857. > > So if the chain isn't detected correct, you'll want to probe the TMS, > TCK, and TDO pins of each device. (ie. are the pins connected correctly, > anything shorted, etc...) > > Other possible causes includes board SI, parallel port noise. You may > want to contact the Xilinx hotline support for further help. > > Regards, Wei > > Kay Schubert wrote: > >> Hi, >> >> I designed a FPGA prototyping board with a Spartan XC2S200E and a XC18V02 >> PROM. >> To configure these devices I put a JTAG header on the board and routed >> it as >> described in >> the following Xilinx datasheet: >> http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/designing7.html >> >> At the software-side I use impact and the PC3 from Xilinx. When I start >> impact in boundary-scan mode, >> the PC3 will be detected (as PC3@200kHz) and the boundary-scan chain >> will >> be identified. But there's the problem: >> impact always detects 11 devices in the chain, but there are only two. >> And: Even though the two devices are original Xilinx parts, no ID >> codes were >> returned (or better: the returned codes >> don't match with Xilinx parts). >> >> I checked the configuration connections and the power supply, but >> everything seems to be o.k. Has anybody of you an idea what the problem >> could be? >> >> thanks, Kay >> >> >Article: 63057
Tom <t_t_1232000@yahoo.com> wrote in message news:<jdm6rv8i170gr0kg12shcu5ljoimrg2hpp@4ax.com>...
> Hi,
>
> when using linker scripts, how can you check if the various sections
> actually fit into the specified memory regions ?
>
> Thanks,
>
> Tom
Define the memories:
MEMORY
{
rom (rx) : ORIGIN = 0x0000, LENGTH = 0x8000
ram : ORIGIN = 0x8000, LENGTH = 0x6000
}
Assign each section to a memory:
.rodata1 : { *(.rodata1) } > rom
Jon
Article: 63058
Martin, there is, and has been for over 2 years:
Using Leftover Multipliers and Block RAM in your Design
04/23/2001
By yours truly
BTW, the search engine in the upper left corner of the xilinx.com
website has recently been dramatically improved. (But it seems to need
single ( ' not " ) quotes to AND multiple words together).
Peter
===================
Martin Euredjian wrote:
> Is there an app note or techxclusives article listing unconventional uses of
> BlockRAM's and multipliers? That could be useful to trigger some creative
> thinking.
>
>
Article: 63059>I know I can bring the PLL's output to "clock output pin" (i.e. U31 or >Y3), but, can I bring it to non-clock output pins? I'm not familiar with the internals of the APEX EP20K1500. If it was a Xilinx chip, I would use the normal special clock distribution resources to route the clock to a FF next to the output pin, toggle that FF, and then connect that FF to the output pin. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 63061
> BTW, the search engine in the upper left corner of the xilinx.com > website has recently been dramatically improved. (But it seems to need > single ( ' not " ) quotes to AND multiple words together). Those hidden gems in the Xilinx website. It's kind of nice not being able to find anything with ease sometimes 'cause every so often you run across something interesting by sheer luck and it's like discovering a whole new world. :-) -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 63062
On a sunny day (Wed, 12 Nov 2003 18:34:09 -0000) it happened "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in <botufd$36$1$830fa79d@news.demon.co.uk>: >Random suggestions follow - you've probably thought about >most of these already, but I'll offer them anyway :-) Nice to get some suggestions! >Do you *know* where the ground reference is that's used for >the output pads that drive your R2R ladder? have you taken >care to use output pads all in the same bank for that? Yes, and today I used a separate bank for the DA output and the comparator, so I could use TTL like output to the DA (and not have to use the same input type). I also tried all other comparator input modes. >Could you consider adding a second R2R and digitizing the >video GROUND, also AC coupled in? Then subtract VideoGnd >from VideoHot, add a suitable offset (presumably you're >getting the offset by sampling the back porch somewhere?). Yes, this 'differential' but probably not really needed for what I want it for. >This *might* help if both R2R DACs are driven from buffers >that share a common ground, i.e. are very nearby on the chip. I disabled some other circuits on the board, that improved things. So, ground loops... >I've seen 7-bit SNR with very simply constructed R2R DACs >on the output of FPGAs before now, but that was at quite >low frequencies so the FPGA itself would have been much >quieter. I say this because 7-bit should be plenty to get >reasonably quiet-looking video. Yep, many, many years ago I was at a research institute in Amsterdam, You were allowed to spend 10% of the time on your own project / idea... Good place, was in the front of things. Anyways I designed a digitizer with 6 bits and digitized my first video there in 1979. Big eurocard full of chips, people standing around it ..oooh... Next day guy walks in, drops data sheet on my desk of 8 bit flash AD chip. hehe >Finally, are you sampling a composite NTSC or PAL video >signal? If so, what's happening about aliasing of the >colour subcarrier? Wouldn't it be a good idea to sample >at an exact multiple of Fsc? Good point, yes the idea is (if this works as expected) to digitize RGB from a DVD player, then store a line in block RAM in FPGA, read it out at twice the speed, and stick it in a normal VGA monitor (at 31kHz 50 Hz). I have a card from Philips that does exactly that (with normal logic), but it is an old ISA card...., not very good quality either (PCTV1000). So I want something like that.. Then of cause the mpeg2 coding, but alas, first the digitizer. > >Let us know how you progress - it sounds fun. If this code works the way I want, I will set up a webpage. Today I played some more, but have things to do, so it will take time. Anyways I slowed down the clock, to be better able to see what happend (100x slower), an it seems something strange happens in that input comparator. I can see my algo working, but about say 1 in a 100 times or so it gets 100% the wrong (just any) value. Simulation is OK, and using extra registers and delays makes no difference. What DOES make a difference is when I hold my finger on the reference input. This points to some oscillations perhaps... Maybe it it is picky about rise times.... these will by definition be slow on the last steps (just add or subtract a few mV). Then I tried to drive it with 50 Ohms, but no real difference. So, more play later. OK, this test is with a composite PAL signal, and if I was to use composite, then digitizing at 3 x 4.43 MHz PAL subcarrier would be good (so no moving interference etc..) That gives 13.29 MHz, 8 steps = 106.32 MHz clock. This could be a nice LC oscillator, divider in FPGA, lock to 4.43 source, use varicap to tune 100 MHz oscillator.. With all that color and TV stuff I am in my element, no problems there. I will try some more later, perhaps Saturday, sure I will post it here when it is usable. Actually I did watch part of a DVD with it... in color too. You can wonder, why not use the flash AD chips with 4 input mux... I have one... But this is just for fun. And 16 resistors are cheaper then that chip? I did DA in 1979 with 8 resistors, 1k 2k 4k 8k etc.. Ends connected together. >Jonathan Bromley, Consultant > >DOULOS - Developing Design Know-how >VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > >Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK >Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com >Fax: +44 (0)1425 471573 Web: http://www.doulos.com > >The contents of this message may contain personal views which >are not the views of Doulos Ltd., unless specifically stated. > > > >Article: 63063
Martin, When I first joined Xilinx, I spent hours going through the external web site. I was amazed at just how much "stuff" there was out there. Often I read a question here, and point people immediately to the online answer. I do have to remember that it is is not as easy for others to find these gems (hidden or not) as it is for me. My favorite pitch to a prospective new customer is to ask them to go to our website, and place a query for some kind of information (eg "Signal Integrity"), and then do the same for the competition. Not only do we have many more "hits" on just about any topic you can think of, the quality of the information is vastly superior. The only problem we seem to have is how to make it easier to get at all of it (which, as Peter points out, we are trying constantly to improve). Austin Martin Euredjian wrote: > > BTW, the search engine in the upper left corner of the xilinx.com > > website has recently been dramatically improved. (But it seems to need > > single ( ' not " ) quotes to AND multiple words together). > > Those hidden gems in the Xilinx website. It's kind of nice not being able > to find anything with ease sometimes 'cause every so often you run across > something interesting by sheer luck and it's like discovering a whole new > world. :-) > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu"Article: 63064
On a sunny day (Wed, 12 Nov 2003 13:55:30 -0800) it happened Peter Alfke <peter@xilinx.com> wrote in <3FB2AC53.76A5CA48@xilinx.com>: >Hal, >I like your line or thought, and I have been thinking along the same >lines, without good results. >Maybe this community can come up with a simple solution: >Use a few external components to adjust the duty cycle, and perhaps also >the alternate period problem. >For simplicity: accept a relatively low frequency ( <40 MHz). >Any takers out there? >I can promise publication, fame and glory... >Peter Alfke Well, the analog way was to make a coil with a center tap and 2 diodes. The double phase rectified wave you get is 2f ( like 120 Hz hum from 60 Hz supply). This works fine for analog (amplitude modulated) signals too, I have used it a 4.43 MHz to double color subcarrier. You will have to go off FPGA, drive a small ferrite transformer, slice it with a transistor, and back into FPGA. In these days many people are paranoid about discrete components perhaps. Not to mention a coil or transformer. But it is really simple. Of cause any non-linear component (MOSFET / FET / Transistor) can be used to double frequency, just bias it in the non linear region, and put a circuit tuned to 2f in its output, 3 f and 4f also works fine. Radio stuff.Article: 63065
enq_semi wrote:
> Device: APEX EP20K1500
>
> I use the on-chip PLL to convert 40MHz Xtal clock to 56MHz clock and
> want to watch this signal on oscilloscope.
>
> Can I bring the PLL's output directly to Pin_F1 of JP10 or indirectly
> to Pin_F1?
>
> I know I can bring the PLL's output to "clock output pin" (i.e. U31 or
> Y3), but, can I bring it to non-clock output pins?
Directly? I believe the answer is no. For all the excellent global
resources (better than Virtex II in some way) of the Apex 20K family,
this is one thing they appear to have left off (on purpose or accident,
I don't know).
And I recall it being painful to interface to the few clock outputs they
do provide (I think they provided a very small choice of driver types).
If you can use a second PLL to produce a 2x (112 MHz) clock, then
perhaps you could use the FF in the I/O cell to create the 56 MHz to
send off chip.
Marc
Article: 63066Having had an occasional hand at doing web work for myself I wholy appreciate how complex the problem can be. The quality of information on the Xilinx site is definetly up there. ...now, if you could only switch from eight menus per page (or whatever it is) to a more "linear" environment, that would be great. There's a little gem out there in the Web design world called "Typo3" (http://typo3.org/) that is, as I understand it, gaining momentum. The tool builds fully database driven websites with very powerful back-end authoring capabilities. The best thing is that the menu structure is maintained automagically. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message news:3FB3D288.1F64DA29@xilinx.com... > Martin, > > When I first joined Xilinx, I spent hours going through the external web > site. I was amazed at just how much "stuff" there was out there. Often I > read a question here, and point people immediately to the online answer. I do > have to remember that it is is not as easy for others to find these gems > (hidden or not) as it is for me. > > My favorite pitch to a prospective new customer is to ask them to go to our > website, and place a query for some kind of information (eg "Signal > Integrity"), and then do the same for the competition. Not only do we have > many more "hits" on just about any topic you can think of, the quality of the > information is vastly superior. The only problem we seem to have is how to > make it easier to get at all of it (which, as Peter points out, we are trying > constantly to improve). > > Austin > > Martin Euredjian wrote: > > > > BTW, the search engine in the upper left corner of the xilinx.com > > > website has recently been dramatically improved. (But it seems to need > > > single ( ' not " ) quotes to AND multiple words together). > > > > Those hidden gems in the Xilinx website. It's kind of nice not being able > > to find anything with ease sometimes 'cause every so often you run across > > something interesting by sheer luck and it's like discovering a whole new > > world. :-) > > > > -- > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > Martin Euredjian > > > > To send private email: > > 0_0_0_0_@pacbell.net > > where > > "0_0_0_0_" = "martineu" >Article: 63067
Hello, We have recently been using the free Xilinx UART macro with the 16-byte FIFO (from app note XAPP223) in a design, instantiated in a Virtex XC2V1000. We are using both the Rx and Tx macros (actually, 32 of each for a total of 32 UARTs in the device). Our actual setup looks like this: StrongArm SA-1100 <--> Virtex XC2V1000 <--> 32 serial devices where the UART FIFOs in the XC2V1000 are essentially memory-mapped into the StrongArm's memory space to read and write to the serial devices. Occassionally, we are seeing a MISSED byte being sent from a random serial device. We have scoped the serial lines between the serial devices and the XC2V1000 and know the serial data is showing up there. We put a high-speed logic analyzer on the interface between the SA-1100 and the XC2V1000, and know that the byte does not appear there. After three weeks of investigating this issue, we are starting to wonder if the lost byte may be due to the macro. Is there any condition with the macro where performing a read from the UARTs Rx FIFO to pull a byte out on the same clock edge where a stop-bit has been received and recognized, and the received byte added to the Rx FIFO, would cause the received byte to be lost? Specifically, it seems as though we see N bytes in the UART's Rx FIFO to be read, we perform N reads (actually, N+1 reads, because the N+1 read is what indicates to us that DATA_PRESENT is not asserted, and that byte should be thrown away...we do 16-bit reads: 8 bits data, and 8-bits of status, with the DATA_PRESENT part of the status). We only see the missing bytes when we eventually see DATA_PRESENT again, which interrupts us (the interrupt is actually delayed 4-byte times in our system), and we perform a read of the data in the Rx FIFO again. We should be able to read 4 valid data bytes. However, the first byte we read from the FIFO is actually the SECOND byte that should have been in the FIFO, and the first byte is gone forever (the remaining third and fourth byte are read just fine). Anyone out there ever seen this type of behavior with the macro before? Our baud rates are running at 38.4 KBps, and our FPGA is being clocked by the StrongArm at ~90 MHz, in case you're curious. Any help would be appreciated....thanks in advance! Regards, John O.Article: 63068
Hello, I had the same problem with the same two chips. There were 13 devices on the my board. I used long leads (20 cm) from the PC3 to the board. After shortening both the parallel port cable (I used a 1.5 M 1:1 extension cable between the parallel port and the PC3 cable) and the leads to the board (to 5 cm) the problem was solved. Mark "Kay Schubert" <kaytastroph@gmx.de> schreef in bericht news:3fb3a20d$1@news.uni-rostock.de... > Hi, > > I designed a FPGA prototyping board with a Spartan XC2S200E and a XC18V02 > PROM. > To configure these devices I put a JTAG header on the board and routed it as > described in > the following Xilinx datasheet: > http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/designing7.html > > At the software-side I use impact and the PC3 from Xilinx. When I start > impact in boundary-scan mode, > the PC3 will be detected (as PC3@200kHz) and the boundary-scan chain will > be identified. But there's the problem: > impact always detects 11 devices in the chain, but there are only two. > And: Even though the two devices are original Xilinx parts, no ID codes were > returned (or better: the returned codes > don't match with Xilinx parts). > > I checked the configuration connections and the power supply, but > everything seems to be o.k. Has anybody of you an idea what the problem > could be? > > thanks, Kay > > --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.538 / Virus Database: 333 - Release Date: 10-11-2003Article: 63069
Hello, I need to use a blockram as a FIFO to port data from one clock domain to another. I created a blockram with help of the language template. This blockram is recognised by the XST synthesiser. The dual clock is also recognised after a small modification. The next problem is to describe a databus width conversion. There is a 32 bit processor bus on one side and a 1 bit serial output on the other side. This is no problem with a library element or a blockram instance from the coregen. I don't like the coregen modules because it is not easy to back-up your sources or transport them to another PC. The library instances make the code less portable. Is there a way to describe the width conversion in VHDL without creating extra logic outside of the blockram? Thanks, Mark --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.538 / Virus Database: 333 - Release Date: 10-11-2003Article: 63070
Dave wrote: >Hi, >I have a design using a spartanIIE and a xcs02f configuration eeprom. The >eeprom is 89% full (apparently it will always be that way even if I have a >larger design). I wonder if the fpga can use the extra 11% to store and read >data. I only need to store something like 10 bytes of data before the fpga >is powered off, and reading it back upon power up. > > How will you erase what is in the EEPROM without erasing it all? Some EEPROMS have that capability, many don't. Any logic controlling this must be outside the FPGA so the FPGA can configure itself on power on. JonArticle: 63071
Well, this only works with a tuned circuit that filters out the subharmonics. The issue with a truly digital internal solution is the sensitivity to incoming non-50% duty cycle. No transformer and rectifier alone can help there, but a tuned circuit would. But LCs are not so fashionable anymore... Peter Alfke Jan Panteltje wrote: > > On a sunny day (Wed, 12 Nov 2003 13:55:30 -0800) it happened Peter Alfke > <peter@xilinx.com> wrote in <3FB2AC53.76A5CA48@xilinx.com>: > > >Hal, > >I like your line or thought, and I have been thinking along the same > >lines, without good results. > >Maybe this community can come up with a simple solution: > >Use a few external components to adjust the duty cycle, and perhaps also > >the alternate period problem. > >For simplicity: accept a relatively low frequency ( <40 MHz). > >Any takers out there? > >I can promise publication, fame and glory... > >Peter Alfke > Well, the analog way was to make a coil with a center tap and 2 diodes. > The double phase rectified wave you get is 2f ( like 120 Hz hum from 60 Hz > supply). > This works fine for analog (amplitude modulated) signals too, I have used it > a 4.43 MHz to double color subcarrier. > You will have to go off FPGA, drive a small ferrite transformer, slice it with a > transistor, and back into FPGA. > In these days many people are paranoid about discrete components perhaps. > Not to mention a coil or transformer. > But it is really simple. > Of cause any non-linear component (MOSFET / FET / Transistor) can be used > to double frequency, just bias it in the non linear region, and put a circuit tuned to > 2f in its output, 3 f and 4f also works fine. > Radio stuff.Article: 63072
Off topic: One of the nicest websites to navigate is the BBC's: http://news.bbc.co.uk/ (If you are interested in world news, like I am...) Peter AlfkeArticle: 63073
"mikegw" <mikegw20@hotmail.spammers.must.die.com> wrote in message news:bo4na0$5qk$1@tomahawk.unsw.edu.au... > Hello all, > > I have seen about the place add > on boards for PC's that act as co-processors. This is the interesting bit > to me. Our research group is looking into building a computer (cluster > perhaps) for calculation of particle dynamics, similar to CFD in > application. < snip > Hi, Been reading this thread. I wonder if instead of using an FPGA, DSP, general purpose processor or niche product it would be possible to use a graphics processor like the ones developed for 3D graphics boards. It seems that this particular application requires a lot of 3D processing (distance between particles, direction of interacting force, ...) and similar matrix calculations. Graphics processors are good at this. They have a huge memory bandwidth also, because they have a 64bit or 128bit bus width and DDR, and they support like 64Mbyte or 128Mbyte of memory, so they should be able to handle large data sets very well. But I'm not sure if you can program these like a 'normal' processor. And if it would be feasable for Mike's research group to design a system around such a graphics processor. Maybe it would be possible to 'hack' a graphics board and change its firmware to run simulations ? But are there any development environments available for these chips ? If so, they'd probably be all assembler. And they'd be very expensive I guess. Regards, Marc http://users.skynet.be/vanriet.marc/Article: 63074
Mark, I cannot help you with the VHDL, but recently having investigated a similar design, here are some issues: Asynchronous clocks mean that Empty and Full detection must cross the clock domain boundary, and simple comparators are bound to fail, unless you use Gray-coded addresses. The dual-width design, when going from narrow to wide, must deal with the issue of a partially assembled word still meaning "empty". All this becomes tricky at >200 MHz, but should be manageable at lower frequencies. Dual-clock FIFOs implemented in a dual-ported BlockRAM are trivial, until you have to detect Empty (Full is usually an avoidable situation that allows some cheating, but Empty can be tricky.) Peter Alfke Mark van de Belt wrote: > > Hello, > > I need to use a blockram as a FIFO to port data from one clock domain to > another. I created a blockram with help of the language template. This > blockram is recognised by the XST synthesiser. The dual clock is also > recognised after a small modification. The next problem is to describe a > databus width conversion. There is a 32 bit processor bus on one side and a > 1 bit serial output on the other side. This is no problem with a library > element or a blockram instance from the coregen. I don't like the coregen > modules because it is not easy to back-up your sources or transport them to > another PC. The library instances make the code less portable. Is there a > way to describe the width conversion in VHDL without creating extra logic > outside of the blockram? > > Thanks, > Mark > > --- > Outgoing mail is certified Virus Free. > Checked by AVG anti-virus system (http://www.grisoft.com). > Version: 6.0.538 / Virus Database: 333 - Release Date: 10-11-2003
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