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Austin Lesea <austin@xilinx.com> wrote in message news:<bvu1ml$7s71@cliff.xsj.xilinx.com>... > Steve, > > As for older parts, they do not get any less expensive to make. So the > price drops until the yields are stable, and then stops dropping. > Happens to everyone. At some point, they get more expensive to make as > their quantities go down, and the fab line equipment gets more expensive > to run (obsolete processes). So why are the prices *identical* to the cent, at different suppliers, in different countries, 4 years apart? > That is also why we then go to a new and less expensive technology as > soon as we can! If we can make an FPGA for less, our business increases > as the number of applications that can afford FPGAs increases. > > As for why things cost less in quantity, that is Econ 101 (for non majors). I must have missed Econ 101, so could you explain why there's such an enormous difference in price between the following?: From: http://www.ebnonline.com/showArticle.jhtml?articleID=4400089&_loopback=1 XC2S400E & XC2S600E for $27 and $45, respectively, in 250,000-unit quantities, end 2002, and from: http://www.plis.ru/price.html?ID=124 the cheapest you can get them for is $55.45 and $170.00 respectively, for <100 units. When we did accounts at uni we were taught that the larger the batch size the cheaper the product is because you spread the manufacturing setup charges across more units, but Xilinx aren't going to do a batch size of 100 for an order or 100 units. Distribution costs can't be much either because it only costs ~$9 to get a book sent to teh UK from amazon.com. The cost of wages for sales people is a fixed cost anyway, and the cost of the silicon itself is a variable cost which is independent of the batch size if you take the manufacturing setup costs separately. So why are your small quantity prices so inflated? -- SteveArticle: 65776
Hi, I want to interrupt MicroBlaze with the falling edge of a output port of my peripheral. I have linked this signal to one of the inputs of the Intc controller. I define the port as interrupt in the mpd file: PORT rx_interrupt = "", DIR = OUT, EDGE = FALLING, SIGIS = INTERRUPT, INTERRUPT_PRIORITY = HIGH The problem comes out when I reset o programm the FPGA. Even if the interrupt controller works fine during the execution of the program, something (don't know what yet) generates an interrupt when the FPGA is reseted. I've checked the functional behaviour simulation and the output of Intc controller (IRQ) is asserted a few clock cycles after the reset signal is disasserted. Does anybody know what can be the source of the problem? Thanks in advance, Arkaitz.Article: 65777
Hi John, > I am doing my thesis in artificial intelligence, and wish to create a > "proof > of concept". It has been a long time since I have been working with FPGAs > directly and wish to know the following: > > 1 - What software and hardware tools are available that operate well under > Windows (compilation, etc...)? If you are referring to FPGA synthesis, you need to check which software is offered by the FPGA manufacturer of your choice. Mostly they offer free software for the smaller devices. > 2 - Has anyone had any experience with programming AI's on FPGAa? Are > there tools available for FPGA development? I have none, and I doubt that there are any software tools available specifically for this purpose. You would need to describe your neurons/neural network in VHDL or so. Perhaps it's a good idea to google for vhdl neuron or something like that. Maybe someone already created some kind of framework that generates you synthesizable code from a more abstract specification. I remember that Siemens developed a neuro computer around 10 years before (called Synapse 1). That one basically consisted out of tons of Lattice CPLDs. > 3 - Are there any programmable logic devices out there that have a ADC > built in? If you refer to adders, yes, logic blocks of most FPGA series can be configured as adder/subtractor/counter/... > 4 - Are there any "tricks" that I would be able to use in order to > generate uniform, gaussian or Cauchy noise with a minimal of external > hardware? I don't know exactly what is "gaussian or Cauchy noise", but you can generate noise easily with shift registers with XOR-feedback. Perhaps this is what you need. Just stress google to find out more about that. I hope this gave you some starting points. Regards, MarioArticle: 65778
filippo wrote: > I' m having great troubles making a small project on FPGA in Verilog. > I have to do it for an exam at university, it shoul be simple but it's > becoming hell. > > facts: > > - FPGA SPARTAN II xc2s100-5pq208 > - Xilinx webpack ISE + modelsim > - uP: AVRmega163 > > problem: > > all simulations with modelsim are good, but it just doesn' t work on > the real FPGA and i don't know where to find a solution (or where is > the real problem). Did you simulate the pure Verilog code or the back-annotated code (i.e. after synthesis)? You know, not every formally valid code will be correctly synthesized. I don't know Verilog and so I cannot give comments to your code. So you should check whether you described your problem using the right coding conventions. Also check whether you got some timing problems. Regards, MarioArticle: 65779
Hi is there a FPGA database out there. The database would be used to fompare the fpga capabilitys (Gates, packages, pc core, special functions, ect) and pricing. This can be vendor spacific ie xilinx, actel, atmel... or an all in one. As it seems now you need to look at almost all the parts and variations then search vendors for pricing. A database would be a powerful tool.Article: 65780
Did you apply timing constraints to the design ... does your design meet the timing constraints. As a minimum you should have three bassic constraints applied ... FFS to FFS FFS to PADs PADs to FFS Mike "filippo" <filippdavid@yahoo.com> wrote in message news:18add487.0402060204.340e7b39@posting.google.com... > I' m having great troubles making a small project on FPGA in Verilog. > I have to do it for an exam at university, it shoul be simple but it's > becoming hell. > > facts: > > - FPGA SPARTAN II xc2s100-5pq208 > - Xilinx webpack ISE + modelsim > - uP: AVRmega163 > > problem: > > all simulations with modelsim are good, but it just doesn' t work on > the real FPGA and i don't know where to find a solution (or where is > the real problem). > > of the 10+ modules one seems to be the most troublesome, our > IO_control, here is the code ,please help. > > -------------------------------------------------------------------------- ------- > module IO_control(ALE,NWR,NRD,DIR,DA,MIN,MAX,SEL,TYPEFIL,AMPLIF,DIVFRQ,clk); > > input ALE; > > input NWR; > > input clk; > > input NRD; > > input DIR; > > input [7:0] MIN; > > input [7:0] MAX; > > inout [7:0] DA; > > output [7:0] SEL; > > output [7:0] TYPEFIL; > > output [7:0] AMPLIF; > > output [7:0] DIVFRQ; > > parameter uno = 8'b0000_0001; > > > > reg [7:0] ADDR_REG; > > reg [7:0] DO_REG; > > reg [7:0] SEL_REG=uno; > > reg [7:0] TYPEFIL_REG=uno; > > reg [7:0] AMPLIF_REG=uno; > > reg [7:0] DIVFRQ_REG=uno; > > > > > > assign SEL = SEL_REG; > > assign TYPEFIL = TYPEFIL_REG; > > assign AMPLIF = AMPLIF_REG; > > assign DIVFRQ = DIVFRQ_REG; > > > > assign DA = (DIR) ? 8'bzzzz_zzzz : DO_REG; > > > > always @ (posedge clk) > > begin > > if (ALE) ADDR_REG <= DA; > > if (~NWR) > > case (ADDR_REG) > > 8'b0000_0001 : SEL_REG <= DA; > > 8'b0000_0010 : TYPEFIL_REG <= DA; > > 8'b0000_0100 : AMPLIF_REG <= DA; > > 8'b0000_1000 : DIVFRQ_REG <=DA; > > default DO_REG <= 8'b1111_1111; > > endcase > > if (~NRD) > > case (ADDR_REG) > > 8'b0000_0001 : DO_REG <= SEL_REG; > > 8'b0000_0010 : DO_REG <= TYPEFIL_REG; > > 8'b0000_0100 : DO_REG <= AMPLIF_REG; > > 8'b0000_1000 : DO_REG <= DIVFRQ_REG; > > 8'b0001_0000 : DO_REG <= MIN; > > 8'b0010_0000 : DO_REG <= MAX; > > default DO_REG <= 8'b1111_1111; > > endcase > > end > > > > endmoduleArticle: 65781
Hello, I want to receive a seriell datastream at 20 x 142MHz = 2,84Gb/s with a Rocket I/O cell. Do I need to connect the external BREFCLK (142MHz) to RECEIVE data with a Rocket I/O cell or can I use the recovered clock RXRECCLK in the design? Thank you for answers, MatthiasArticle: 65782
"William Wallace" <msm30@yahoo.com> wrote in message news:7e4865b7.0402052324.1651ec26@posting.google.com... > "MM" <mbmsv@yahoo.com> wrote in message news:<bvmaua$u760t$1@ID-204311.news.uni-berlin.de>... > > Do a post PAR simulation. Note that xilinx uses the same times for > min/typ/max in their sdf files. (Do a search in their web database > for ways to get min sdf timing). Do min and max timing simulation. I did, although not the min/max... The problem with this is that I can only simulate a few data frame cycles as it takes very long. Surely the problem would have to manifest itself during the first frame, but I didn't see it... Perhaps I need to repeat the whole thing... > > some > > state machines, a bus interface and some Coregen memories. The bus runs at > > slower clock, but it is fully decoupled from the IP core (through the > > memories). > > What are the two clock rates? Are you using dual ported FIFOs? Are > they getting full? The clock rates are 38 MHz for the local bus and 50 MHz for the core and the state machine that controls it. > Take the device that works and use a hair dryer to warm it, see if it > fails. As soon as I get my hands on the hardware I will. At the moment my management is satisfied with the thing working reliably at 45 MHz and all the hardware went to software guys... > Look at using a DCM. Why? > Are you gating any clocks? No. /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca")Article: 65783
CALL FOR PAPERS: EXTENDED DEADLINE: Feb. 16, 2004 ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS (ERSA'04) ============================================================== http://www.scism.lsbu.ac.uk/ERA/ersa.html ARE YOU INTERESTED IN ORGANIZING SPECIAL SESSIONS AND DEMOS/EXHIBS ?? June 21 - 24, 2004 Monte Carlo Resort, Las Vegas, Nevada, USA Please forward this message to all interested colleagues. I apologize if you receive multiple copies. Yours sincerely, Toomas P. Plaks ERSA Chairman ==================================================================== ==================================================================== CALL FOR PAPERS =============== The 2004 International Conference on ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS --- ERSA'04 ================================================================ http://www.scism.lsbu.ac.uk/ERA/ersa.html a part of The 2004 International MultiConference in Computer Science and ============================================================== Compute Engineering =================== http://www.world-academy-of-science.org June 21--24, 2004 Monte Carlo Resort, Las Vegas, Nevada, USA Introduction ============ The recent years have shown a continuous interest in using reconfigurable computing platform for the design of application-specific computer systems. The advances in reconfigurable computing architecture, in algorithm implementation methods, and in automatic mapping methods of algorithms into hardware and processor spaces form together a new paradigm of computing and programming that has often been called `Computing in Space and Time'. This conference focuses on the different approaches in engineering of reconfigurable systems and implementing of algorithms, including theory, architecture, algorithms, design systems and applications that demonstrate the benefits of reconfigurable computing. ** Multiconference Keynote Talk from ERSA ========================================= Computer Architecture, the road ahead Prof. Michael J. Flynn, Stanford Univ., USA ** ERSA Keynote Talks (Preliminary) ===================== 1. Energy Efficient Computations Using FPGAs Prof. Viktor K. Prasanna, Univ. of Southern California, USA 2. From here to main-stream: The present and future of reconfigurable computing Prof. Walid A. Najjar, Univ. of California, Riverside, USA 3. >>>>> Dr. Wayne Luk, Imperial College, UK 4. Reconfigurable Systems, New Tools and New Math Richard Shoup, QuickSilver, Inc., USA 5. >>>>> Prof. Seth C. Goldstein, Carnegie Mellon University, USA ** General Topics ================= 1. Theory - Synthesis, Mapping, Parallelization, Partitioning ... 2. Software - CAD, Languages, Compilers, Operating Systems ... 3. Hardware - Adaptive and Dynamic Hardware, Reconfigurable Architectures ... 4. Applications - Wireless Communication, Software Radio, Smart Cameras ... ** Sessions =========== A number of Focus and Technical Sessions are planned to organize. If you are interested in, please contact with ERSA Chairman Toomas Plaks (ersa@lsbu.ac.uk) Focus sessions (Preliminary List) -------------- 1. Reconfigurable Systems for Energy-efficient Mobile Systems Chairman: Gerard J.M. Smit, Univ. of Twente, The Netherland 2. Operating System Approaches for Reconfigurable Hardware Chairman: Marco Platzner, ETH, Zurich, Switzerland 3. Reconfigurable Supercomputing Chairman: Maya B. Gokhale, Los Alamos National Laboratory, USA 4. HW/SW Codesign for Reconfigurable Hardware Systems Chairman: Miriam Leeser, Northeastern Univ., USA 5. Reconfigurable System-On A Chip (SOC) Architectures Chairman: Michael J. Wirthlin, Brigham Young Univ., USA Technical sessions (Preliminary List) ------------------ 1. CHAMELEON a reconfigurable platform for wireless multimedia terminals Chairman: Gerard J.M. Smit, Univ. of Twente, The Netherland ** Demos/Exhibs =============== A number of industrial demos/exhibs are planned for the duration of the MultiConferences. Interested parties should contact ERSA Chairman Toomas Plaks. * QuickSilver Tech., Inc., * Chameleon project * ... ** Best Papers ============== After the conference, authors of best papers will be invited to submit an extended version for publication in a Special Issue of an International Journal (The Journal of Supercomputing, Kluwer). ** Important Dates ================== EXTENDED DEADLINE: Feb. 16, 2004 -------------------------------- ** Full papers (max 10 pages, IEEE format): February 16, 2004 ** Notification of acceptance: March 22, 2004 ** Camera-ready papers and registration: April 21, 2004 ** Conference: June 21--24, 2004 ** Submission ============= Prospective authors are invited to submit a full paper that must be an original, unpublished work, not currently submitted for publication or for consideration elsewhere. Full details will be available on the ERSA Web-site: http://www.scism.lsbu.ac.uk/ERA/ersa.html ** Other Conferences of Interest ================================ Together with ERSA there will be other conferences of interest: *PDPTA - International Conference on Parallel and Distributed Processing Techniques and Applications *CISST - International Conference on Imaging Science, Systems and Technology *ICWN - International Conference on Wireless Networks *CIC - International Conference on Communications in Computing *ESA - International Conference on Embedded Systems and Applications *VLSI - International Conference on VLSI *IC - International Conference on Internet Computing For more details about other conferences, visit the Web-site: The 2003 International MultiConference in Computer Science and ============================================================== Compute Engineering =================== http://www.world-academy-of-science.org:8080/CSREA/ws/ ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ If you have any questions or problems, please do not hesitate to e-mail: ersa@lsbu.ac.uk or directly to conference chair Toomas Plaks: plakst@lsbu.ac.uk (postal address is given below). Conference Chairman =================== Dr. Toomas P. Plaks email: plakst@lsbu.ac.uk BCIM London South Bank University 103 Borough Road London SE1 0AA United Kingdom General Co-Chair ================ Prof. Cameron D. Patterson Virginia Tech., USA Industrial Co-Chair =================== John Watson QuickSilver Tech., Inc., USA Advisory Board ============== Prof. Michael J. Flynn Stanford Univ., USA Prof. Reiner W. Hartenstein Univ. of Kaiserslautern, Germany Prof. Viktor K. Prasanna Univ. of Southern California, USA Dr. Nick Tredennick Gilder Technology Report, USA Steering Committee ================== Peter Athanas, Virginia Tech., USA Carl Ebeling, University of Washington, USA Hossam ElGindy, Univ. of New South Wales, Australia Philip Leong, Chinese Univ. of Hong Kong, China Wayne Luk, Imperial College, UK Hartmut Schmeck, Univ. of Karlsruhe, Germany Lothar Thiele, ETH, Zurich, SwitzerlandArticle: 65784
Steve, Quite frankly, I am amazed at how folks think about this. You have obviously never thought about that computer on your desk, and how it can be sold for $499! Or even your car, just go price the parts individually some time. See below, Austin Steve wrote: > Austin Lesea <austin@xilinx.com> wrote in message news:<bvu1ml$7s71@cliff.xsj.xilinx.com>... > >>Steve, >> >>As for older parts, they do not get any less expensive to make. So the >>price drops until the yields are stable, and then stops dropping. >>Happens to everyone. At some point, they get more expensive to make as >>their quantities go down, and the fab line equipment gets more expensive >>to run (obsolete processes). > > > > So why are the prices *identical* to the cent, at different suppliers, > in different countries, 4 years apart? They use the "manufacturer's suggested retail price." As mentioned, these were very old parts, and the pricing was now stable. > > > >>That is also why we then go to a new and less expensive technology as >>soon as we can! If we can make an FPGA for less, our business increases >>as the number of applications that can afford FPGAs increases. >> >>As for why things cost less in quantity, that is Econ 101 (for non majors). > > > > I must have missed Econ 101, so could you explain why there's such an > enormous difference in price between the following?: > > From: > > http://www.ebnonline.com/showArticle.jhtml?articleID=4400089&_loopback=1 > > XC2S400E & XC2S600E for $27 and $45, respectively, in 250,000-unit > quantities, end 2002, and from: > > http://www.plis.ru/price.html?ID=124 > > the cheapest you can get them for is $55.45 and $170.00 respectively, > for <100 units. > > When we did accounts at uni we were taught that the larger the batch > size the cheaper the product is because you spread the manufacturing > setup charges across more units, but Xilinx aren't going to do a batch > size of 100 for an order or 100 units. You learned the right stuff. Still applies. If a disti orders 100 parts (and they do) we have to process just that many parts for that one order. Disti's don't want to stock anything anymore, so that makes costs go. Imagine Xilinx' dilemma: what do we build? and when do we build it? If we have an order for 100K parts spread out over a year, everything is trivial, and less costly. But if we have seemingly random orders popping in all of the time, we have to build ahead (risk) and sometimes scrap parts that are not moving. If you have any optimism about your business at all, it would be best to enter into a agreement and let the disti (and us) know where you think you are going, and how many you will need. Distribution costs can't be > much either because it only costs ~$9 to get a book sent to teh UK > from amazon.com. The cost of wages for sales people is a fixed cost > anyway, and the cost of the silicon itself is a variable cost which is > independent of the batch size if you take the manufacturing setup > costs separately. We can't seem to convince disti's to work for free, however, so they charge what they feel they need to in order to make a profit. Disti's also have 200+ FAEs of their own on their payrolls to support their products, as well as order entry systems, stocking(?), unsold inventory, stocking losses, uncollectable accounts (deadbeats), etc. As for the book business, I was an author, and if an author gets 1 cent on their book, they are lucky. Ruthless business, with all of the money going to the publisher and retailers. Like perfume, or music CDs, cost of book: $3, price of book $75...... the $9 shipping is a complete rip-off, they already made their profit, now they are icing their cake. > > So why are your small quantity prices so inflated? > Because they are a fair representation of the costs associated with small numbers of parts ordered through distribution to allow for a profitable business by the distis and reps. They also represent the unwillingness of a customer to enter into a contract which would allow a scheduled delivery of parts over the long term, which is where the real savings start to kick in. You commit, we commit. You do not commit, we supply product at a fair price based on the fact that you will go away after the one order. > > -- > SteveArticle: 65785
Matthias, If you want to have your received data aligned with the right clock, you use the received recovered clock (RXRECCLK). If the transmit clock source is the same as the receive clock source (say the 142 MHz is distributed to all cards on a backplane) then you can use the FIFO in the receiver to align the phase to the master clock source (RXRECCLK clock into FIFO, master OSC clock out of FIFO). If different transmit clock frequency is used, then the FIFO will overflow or underflow, and you should not be using the master clock for receive timing (as it is different from he transmit). Austin Matthias Müller wrote: > Hello, > I want to receive a seriell datastream at 20 x 142MHz = 2,84Gb/s with a > Rocket I/O cell. Do I need to connect the external BREFCLK (142MHz) to > RECEIVE data with a Rocket I/O cell or can I use the recovered clock > RXRECCLK in the design? > Thank you for answers, > Matthias >Article: 65786
John Williams wrote: > Steven K. Knapp wrote: > >> Just a clarification -- the Internal Configuration Access Port (ICAP) is >> available on some Xilinx FPGAs to aid reconfiguration from within the >> device. However, devices without ICAP can still be partially >> reconfigured >> from internal logic. > > > Did you mean to write "from external logic"? > > There's also another way it could be done, for non-ICAP devices. > Basically just feed some user IO back into the external SelectMAP pins, > and create bitstreams with the -g Persist:yes option to keep the > selectMAP interface alive after configuration. > > Your self-reconfig core then drives those user pins (and thus the > selectMAP interface) as required. > > This costs a few pins and requires planning at the board design stage, > but if you need self-reconfig that badly in a non-ICAP device, then it > seems a feasible approach. Have I missed anything? > > Regards, > > John > I believe the maximum speed of the external SelectMAP interface is also greater than that of the internal ICAP, for some reason, allowing for faster reconfiguration by looping off-chip than by staying on-chip... (working from memory, take it for what it's worth) -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 65787
The IEE (a UK-based professional engineering society) has organised an online technology debate on the relative merits of programmable logic, ASICs and gate arrays, with a panel of industry speakers. The event takes place on 24 February from 16.00 GMT - registration (free of charge) is required. Full details can be found at http://www.iee.tv/techdebateArticle: 65788
I have a problem with a xilinx virtex2 design, and specifying the timing constraints for a pair of clocks in the design. Most of the design is clocked by either a x1 clk, or a div2 clk (which is hence half the frequency). Both the x1 and div2 clock are generated in a dcm, locked to a x1 input clock. I select which clock to use via a global clock mux BUFGMUX. I have placed a TS on the ouptut clock of the BUFGMUX, which is x1 so that I can be sure the circuitry driven by this clock will run at the faster x1 clock rate. I also put timing constraints on the two clocks out of the dcm, and the input clock pin. The Post PAR timing analyser tells me that there are no timing errors. The design is fine most of the time, but occasionally I get problems where part of the design stops working correctly, but is fixed by a new par. I investigated the timing more carefully, and used the constraints interaction report from the timing analyzer to see what might be going on. What I find in that report is that my timing constraint on the BUFGMUX output clock is shown to be overridden by the div2 clock specification, which is half the frequency. This may explain why I'm having problems. Nearly 2 months ago I contacted european xilinx support, but the guy dealing with my case says he isn't an expert on timing, and keeps coming back (supposedly after discussion with a more expert engineer) with ideas to try, such as putting TIG on the clocks etc. None of these have worked. I'm not totally sure the guy understands my problem. Does anyone have experience with this type of problem, or have any ideas how I can escalate the problem with Xilinx, and speak to a more knowledgeable engineer ? Regards Tony Benham --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.576 / Virus Database: 365 - Release Date: 30/01/2004Article: 65789
Hi Filippo, I assume the clk signal in your code is the AVR clock. You should implement the interface asynchronously and when you have the data in the FPGA synchronize it to whatever clock you have there. This is an excerpt from the ATmega162L datasheet: "Note that the XMEM interface is asynchronous and that the waveforms in the figures below are related to the internal system clock. The skew between the internal and external clock (XTAL1) is not guaranteed (it varies between devices, temperature, and supply voltage). Consequently, the XMEM interface is not suited for synchronous operation." Regards, -- Georgi "filippo" <filippdavid@yahoo.com> wrote in message news:18add487.0402060204.340e7b39@posting.google.com... > I' m having great troubles making a small project on FPGA in Verilog. > I have to do it for an exam at university, it shoul be simple but it's > becoming hell. > > facts: > > - FPGA SPARTAN II xc2s100-5pq208 > - Xilinx webpack ISE + modelsim > - uP: AVRmega163 > > problem: > > all simulations with modelsim are good, but it just doesn' t work on > the real FPGA and i don't know where to find a solution (or where is > the real problem). > > of the 10+ modules one seems to be the most troublesome, our > IO_control, here is the code ,please help. > > -------------------------------------------------------------------------- ------- > module IO_control(ALE,NWR,NRD,DIR,DA,MIN,MAX,SEL,TYPEFIL,AMPLIF,DIVFRQ,clk); > > input ALE; > > input NWR; > > input clk; > > input NRD; > > input DIR; > > input [7:0] MIN; > > input [7:0] MAX; > > inout [7:0] DA; > > output [7:0] SEL; > > output [7:0] TYPEFIL; > > output [7:0] AMPLIF; > > output [7:0] DIVFRQ; > > parameter uno = 8'b0000_0001; > > > > reg [7:0] ADDR_REG; > > reg [7:0] DO_REG; > > reg [7:0] SEL_REG=uno; > > reg [7:0] TYPEFIL_REG=uno; > > reg [7:0] AMPLIF_REG=uno; > > reg [7:0] DIVFRQ_REG=uno; > > > > > > assign SEL = SEL_REG; > > assign TYPEFIL = TYPEFIL_REG; > > assign AMPLIF = AMPLIF_REG; > > assign DIVFRQ = DIVFRQ_REG; > > > > assign DA = (DIR) ? 8'bzzzz_zzzz : DO_REG; > > > > always @ (posedge clk) > > begin > > if (ALE) ADDR_REG <= DA; > > if (~NWR) > > case (ADDR_REG) > > 8'b0000_0001 : SEL_REG <= DA; > > 8'b0000_0010 : TYPEFIL_REG <= DA; > > 8'b0000_0100 : AMPLIF_REG <= DA; > > 8'b0000_1000 : DIVFRQ_REG <=DA; > > default DO_REG <= 8'b1111_1111; > > endcase > > if (~NRD) > > case (ADDR_REG) > > 8'b0000_0001 : DO_REG <= SEL_REG; > > 8'b0000_0010 : DO_REG <= TYPEFIL_REG; > > 8'b0000_0100 : DO_REG <= AMPLIF_REG; > > 8'b0000_1000 : DO_REG <= DIVFRQ_REG; > > 8'b0001_0000 : DO_REG <= MIN; > > 8'b0010_0000 : DO_REG <= MAX; > > default DO_REG <= 8'b1111_1111; > > endcase > > end > > > > endmoduleArticle: 65790
Tony, File a case with the hotline via the support.xilinx.com web page. Austin Tony Benham wrote: > I have a problem with a xilinx virtex2 design, and specifying the timing > constraints for a pair of clocks in the design. > Most of the design is clocked by either a x1 clk, or a div2 clk (which is > hence half the frequency). Both the x1 and div2 clock are generated in a > dcm, locked to a x1 input clock. I select which clock to use via a global > clock mux BUFGMUX. I have placed a TS on the ouptut clock of the BUFGMUX, > which is x1 so that I can be sure the circuitry driven by this clock will > run at the faster x1 clock rate. I also put timing constraints on the two > clocks out of the dcm, and the input clock pin. The Post PAR timing analyser > tells me that there are no timing errors. > The design is fine most of the time, but occasionally I get problems where > part of the design stops working correctly, but is fixed by a new par. > I investigated the timing more carefully, and used the constraints > interaction report from the timing analyzer to see what might be going on. > What I find in that report is that my timing constraint on the BUFGMUX > output clock is shown to be overridden by the div2 clock specification, > which is half the frequency. This may explain why I'm having problems. > Nearly 2 months ago I contacted european xilinx support, but the guy dealing > with my case says he isn't an expert on timing, and keeps coming back > (supposedly after discussion with a more expert engineer) with ideas to try, > such as putting TIG on the clocks etc. None of these have worked. I'm not > totally sure the guy understands my problem. > Does anyone have experience with this type of problem, or have any ideas how > I can escalate the problem with Xilinx, and speak to a more knowledgeable > engineer ? > Regards > Tony Benham > > > > --- > Outgoing mail is certified Virus Free. > Checked by AVG anti-virus system (http://www.grisoft.com). > Version: 6.0.576 / Virus Database: 365 - Release Date: 30/01/2004 > >Article: 65791
filippo wrote:
> all simulations with modelsim are good, but it just doesn' t work on
> the real FPGA and i don't know where to find a solution (or where is
> the real problem).
Here's one suspect:
> assign DA = (DIR) ? 8'bzzzz_zzzz : DO_REG;
You can drive a Z for synthesis, but you can't read one.
Consider adding an output enable signal.
-- Mike Treseler
Article: 65792
Tony Benham wrote:
> I have a problem with a xilinx virtex2 design, and specifying the timing
> constraints for a pair of clocks in the design.
> Most of the design is clocked by either a x1 clk, or a div2 clk (which is
> hence half the frequency).
Consider using div2 as a clock enable and clocking
everything with x1.
-- Mike Treseler
Article: 65793On Fri, 06 Feb 2004 17:07:33 +0000, Tony Benham wrote: > I have a problem with a xilinx virtex2 design, and specifying the timing > constraints for a pair of clocks in the design. > Most of the design is clocked by either a x1 clk, or a div2 clk (which is > hence half the frequency). Both the x1 and div2 clock are generated in a > dcm, locked to a x1 input clock. I select which clock to use via a global > clock mux BUFGMUX. I have placed a TS on the ouptut clock of the BUFGMUX, > which is x1 so that I can be sure the circuitry driven by this clock will > run at the faster x1 clock rate. I also put timing constraints on the two > clocks out of the dcm, and the input clock pin. The Post PAR timing analyser > tells me that there are no timing errors. > The design is fine most of the time, but occasionally I get problems where > part of the design stops working correctly, but is fixed by a new par. > I investigated the timing more carefully, and used the constraints > interaction report from the timing analyzer to see what might be going on. > What I find in that report is that my timing constraint on the BUFGMUX > output clock is shown to be overridden by the div2 clock specification, > which is half the frequency. This may explain why I'm having problems. > Nearly 2 months ago I contacted european xilinx support, but the guy dealing > with my case says he isn't an expert on timing, and keeps coming back > (supposedly after discussion with a more expert engineer) with ideas to try, > such as putting TIG on the clocks etc. None of these have worked. I'm not > totally sure the guy understands my problem. > Does anyone have experience with this type of problem, or have any ideas how > I can escalate the problem with Xilinx, and speak to a more knowledgeable > engineer ? > Regards > Tony Benham > > > > --- > Outgoing mail is certified Virus Free. > Checked by AVG anti-virus system (http://www.grisoft.com). > Version: 6.0.576 / Virus Database: 365 - Release Date: 30/01/2004 Put your timing constraint on the clkin of the DCM, don't put any constraints on the outputs of the DCM. The Xilinx tools will figure calculate the right constraints for the outputs and apply the worst case constraint. If that doesn't work then add a FFS to FFS constraint.Article: 65794
In article <c00e21$77m1@cliff.xsj.xilinx.com>, Austin Lesea <austin@xilinx.com> wrote: >Steve, > >Quite frankly, I am amazed at how folks think about this. You have >obviously never thought about that computer on your desk, and how it can >be sold for $499! Or even your car, just go price the parts >individually some time. I've often priced the parts for building a computer, and they add up to something within 15% of the price of buying the computer from Dell. Moreover, the price for Intel CPUs in the shop is the same to within about 15% as the price stated for thousand-unit quantities in their press releases. I believe FPGAs are comparably complicated to Intel CPUs, and I don't think there's as much as an order of magnitude difference in production quantity. Is the market volatility for FPGAs that much greater? > If you have any optimism about your business at all, it would be > best to enter into a agreement and let the disti (and us) know where > you think you are going, and how many you will need. I can understand that attitude for people buying ten thousand chips; but where do you expect people to get the experience with FPGAs that they have with microprocessors, when state-of-the-art FPGAs are two orders of magnitude more expensive and an order of magnitude less convenient to acquire? >Because they are a fair representation of the costs associated with >small numbers of parts ordered through distribution to allow for a >profitable business by the distis and reps. But, again, why doesn't the same argument apply to CPUs, for which there are half a dozen distributors in most towns, fairly happily distributing the things for a couple of percent profit margin. TomArticle: 65795
Please let me emphasize Mike's suggestion. There has been a series of problem reports in this ng, relating to clock manipulations. There is this simple general cure: Use a single global clock, and do the rest with selective clock enable. You save yourself a lot of headache and wasted time and effort. This should always be your first and obvious solution. Clock gating and other clock manipulation tricks should be the "solution of last resort" when CE cannot be used for some special reason. Think single clock domain, so that you become more efficient, and can sleep at night. :-) Peter Alfke, Xilinx ========================== Mike Treseler wrote: > > Tony Benham wrote: > > I have a problem with a xilinx virtex2 design, and specifying the timing > > constraints for a pair of clocks in the design. > > Most of the design is clocked by either a x1 clk, or a div2 clk (which is > > hence half the frequency). > > Consider using div2 as a clock enable and clocking > everything with x1. > > -- Mike TreselerArticle: 65796
As Larry points out correctly, the real battleground is for the new design-in. But that is not only over price, availability, and features. Whenever the two competitors ( it's mainly the X vs A battle) look equal or similar, then other factors come in: Previous good ar bad experience with pricing, quality, and support, both commercially and technically, hardware and software. That's why we at Xilinx put a lot of effort into technical support, and that's why we are so attentive in this ng. The hearts and minds of the user (customer) can only be won over and then kept by offering and maintaining a "positive experience". Nobody is perfect, but we really try... Peter Alfke ============ Larry Doolittle wrote: > > I> Where competition does kick in is for _new_ designs, which > (duh) involve _new_ parts. Here the competition is, as Peter > wrote, fierce. "Design wins" are a very big deal to both brand > A and X. After a brief period of (they hope) high volume, > high profile success -- part of which is leading-edge cost > effectiveness from the buyer's perspective -- the business system > settles down to the operating scenario of the previous paragraph. > - LarryArticle: 65797
filippdavid@yahoo.com (filippo) wrote in message news:<18add487.0402060204.340e7b39@posting.google.com>...
> I' m having great troubles making a small project on FPGA in Verilog.
> I have to do it for an exam at university, it shoul be simple but it's
> becoming hell.
>
> problem:
>
> all simulations with modelsim are good, but it just doesn' t work on
> the real FPGA and i don't know where to find a solution (or where is
> the real problem).
Did you perform both pre- and post-route simulations? What does your
test bench actually do? Is it a real bus-functional model of your
microcontroller? Or are you just setting and clearing signals in some
arbitrary fashion? I would imagine that this is the root of your
problem -- your simulation is bogus. As they say: garbage in, garbage
out?
What about your timing constraints?
> of the 10+ modules one seems to be the most troublesome, our
> IO_control, here is the code ,please help.
>
> ---------------------------------------------------------------------------------
> module IO_control(ALE,NWR,NRD,DIR,DA,MIN,MAX,SEL,TYPEFIL,AMPLIF,DIVFRQ,clk);
> input ALE;
> input NWR;
> input clk;
> input NRD;
> input DIR;
> input [7:0] MIN;
> input [7:0] MAX;
> inout [7:0] DA;
> output [7:0] SEL;
> output [7:0] TYPEFIL;
> output [7:0] AMPLIF;
> output [7:0] DIVFRQ;
>
> parameter uno = 8'b0000_0001;
>
> reg [7:0] ADDR_REG;
> reg [7:0] DO_REG;
> reg [7:0] SEL_REG=uno;
> reg [7:0] TYPEFIL_REG=uno;
> reg [7:0] AMPLIF_REG=uno;
> reg [7:0] DIVFRQ_REG=uno;
^^^^^^^^^^^
This initialization is illegal, or at least ignored by a synthesis
tool.
Use an external reset to actually initialize these registers.
> assign SEL = SEL_REG;
> assign TYPEFIL = TYPEFIL_REG;
> assign AMPLIF = AMPLIF_REG;
> assign DIVFRQ = DIVFRQ_REG;
Ummmmm...why not declare the SEL, TYPEFIL, AMPLIF and DIVFRQ outputs
as regs and not bother with this silly assign? Also: explicitly
declare whether your module outputs are wires or regs. It's a good
style habit.
> assign DA = (DIR) ? 8'bzzzz_zzzz : DO_REG;
>
> always @ (posedge clk)
> begin
> if (ALE) ADDR_REG <= DA;
>
> if (~NWR)
> case (ADDR_REG)
> 8'b0000_0001 : SEL_REG <= DA;
> 8'b0000_0010 : TYPEFIL_REG <= DA;
> 8'b0000_0100 : AMPLIF_REG <= DA;
> 8'b0000_1000 : DIVFRQ_REG <=DA;
> default DO_REG <= 8'b1111_1111;
> endcase
>
> if (~NRD)
> case (ADDR_REG)
> 8'b0000_0001 : DO_REG <= SEL_REG;
> 8'b0000_0010 : DO_REG <= TYPEFIL_REG;
> 8'b0000_0100 : DO_REG <= AMPLIF_REG;
> 8'b0000_1000 : DO_REG <= DIVFRQ_REG;
> 8'b0001_0000 : DO_REG <= MIN;
> 8'b0010_0000 : DO_REG <= MAX;
> default DO_REG <= 8'b1111_1111;
> endcase
> end
Umm, another style issue. Use more than one always statement for the
above. You have three separate registers; put 'em in their own always
blocks.
Also: are ALE, NRD, NWR, DA all synchronous to your clock?
Remember that ALE is a latch enable -- are you sure that your address
is actually valid when the latch enable is active and goes away?
--a
Article: 65798"Jean Nicolle" <j.nicolle@sbcglobal.net> wrote in message news:<YzeTb.20559$hv1.7139@newssvr25.news.prodigy.com>... > Hi all, > > I tried to summarize the differences in a table. > http://www.fpga4fun.com/table.html > > Sorry about the link, it wasn't easy to duplicate the table in text form for > this posting. > > Things I'd be interesting to hear about: > 1. is the info accurate? > 2. did I miss important features that differentiate the 2 software? (without > getting into details, these are big software...) > > The table is intended as a beginner's guide to FPGA's software. Ummmmmmmmmmmm...the most obvious, and perhaps most important difference, is that Quartus only supports Altera parts, and Xilinx ISE supports only Xilinx parts. In other words, you choose the device based on whatever parameters you care about, and then you get the software that lets you design the chip. If only a Xilinx device has a gotta-have feature, it doesn't matter if Altera's software is cheaper/better/gets-you-a-good-raise/gets-you-laid (all of which may or may not be true) because you can't use it for Xilinx parts. --aArticle: 65799
"Tungsten-W" <kelvin8157@hotmail.com> wrote in message news:<40232edf$1@news.starhub.net.sg>... > Hi, there: > > I am doing a design which only covers 10% of the slices...but after P&R, it > spreaded all over the FPGA. > How may I constrain it into, say, one corner... > > How may I "nail down the logic into a known location"(Somebody told me this > trick)? > > BTW, I am doing reconfigurable design, so the AREA_GROUP constraints can't > be used... > > Kelvin How about trying to constrain the design to NOT be placed in regions? Check the CONFIG PROHIBIT constraint in the online constraints guide. This could work for you.
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