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At least 6 layers. And 8 isn't unreasonable. -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) "Andre" <armcc@lycos.com> wrote in message news:ae5c06e9.0402120029.4ea5405d@posting.google.com... > How many layers are normally needed for PCBs using low cost FPGAs ?? > > I've just been told by a supposed board layout expert that the 256 pin > BGA version of a Cyclone EP1C6 would require an 8 layer board > (apparently having the entire underside of the device covered by balls > with no free space at the centre makes signal routing a big problem). > > Is this really true ??Article: 66076
Hi Sean, Thanks for your response. It confirmed a few things I was starting to think, but it's nice to know I'm not alone! Sean Durkin wrote: > > But enough rambling and let's get back to your problem: The error > message you get occured to me once. Basically it suggests that some > components of a module have been placed outside of module boundaries > somehow. I think this happened to me when I changed the area constraints > of my modules causing the bus macros to be completely inside one of the > modules. If that's not the problem in your case, I suggest you check the > .NCD-files for each of the modules in PACE or Floorplanner and see if > any components may have been misplaced. I found the problem - I had disobeyed golden rule #465 of having a non-module IOB "above" a module area location... I was secretly hoping there might be some edge-following routing resources that would let me get away with it, but it seems not... thanks again, JohnArticle: 66077
Dear experts in this area, I am trying to configure a PCI board plugged into my PC, running Windows 2000 sp3. This board is the Memec PCI development board, with a Spartan II-200 FPGA connected to the 32-bit PCI bus. I figured that either BIOS or Windows configures the PCI board at bootup, and assigns the BAR0 etc. I am using an FPGA with the Xilinx PCI32 LogiCore. Hence, the Command and Status Register bit 2 (Bus Master) is '0' at startup. How can I set it to '1' after startup? For those of you familiar with the Xilinx PCI32 LogiCore, I've thought about hard setting the CFG_SELF bit to '1', which will fool the core to initiate master transactions. But in simulation, I see that the ADIO bus does not get the date from the AD bus! A more tedious way is to self configure the PCI core to master, but I am seeking an easier way. My firmware colleague told me I have to make use of the "pci.sys" driver in Windows. I am not a programmer, and am not familiar with the "pci.sys" driver. Is there an easier way to do this? Thanks and regards, LCArticle: 66078
> I am trying to debug my application in sdram with use of the "xmdstub > method". After downloading the application with "dow", I can not single step > through my code. I even can't read from memory. Output in xmd: > > XMD% dow appl/appl.elf 0x80000000 > Unable to Open File : appl/appl.elf > XMD% pwd > c:/ > XMD% dow proj/ATM03001/example_7/appl/appl.elf 0x80000000 > start addr in the ELF program hdr is 0x80000000 > XMD% stp > Unable to Read register : R1 > Unable to Read register : R1 > Unable to Read register : R1 > Unable to Read register : R1 > Cannot read from target > > XMD% mrd 0x80000000 > Cannot read from target > > XMD% mrd 0 > Cannot read from target > > XMD% > > Any suggestions of what could be the reason for this behaviour?? BTW, my > final application (appl.elf) is compiled with option: > > LFLAGS = -Wl,-defsym -Wl,_TEXT_START_ADDR=0x80000000 > Okay, the solution is that I don't have to specify the address when downloading the .elf file. Just use: dow proj/ATM03001/example_7/appl/appl.elf Now I can step through my code. FrankArticle: 66079
prav wrote: > Hi all, > > I was studying some board schematics. In this there are some clocks > coming from external world . Before these clocks are connected to the > FPGA pins they pass through an opto isolator.Could any body help me > out why the opto isolators are really required . > They usually required when the signal source has the different ground potencial than FPGA has. Often it occurs when the signal source is far from FPGA and the signal and ground wires make a pair to prevent noise errors. In the medical installation it is the usual practice because of voltage shield of patients. But the opto isolator usually does not support the high clokck frequency. A.Ser.Article: 66080
Hi all, I am using Webpack ISE to do PAR for Coolrunner. How to get back all command line from VHDL and UCF parser to JEDEC generation (parser, synthesis and par works) The goal is to do a generic project (using webpack IDE interface) and to get back all ISE command line, and to re-run the ISE command line for an other VHDL file with minor changes. All the work would be via script for generating about 50 news configs of our Chameleon POD. Are there any command log files? Thanks for all advices, Regards, Laurent Gauch ------------ And now a word from our sponsor --------------------- For a secure high performance FTP using SSL/TLS encryption upgrade to SurgeFTP ---- See http://netwinsite.com/sponsor/sponsor_surgeftp.htm ----Article: 66081
There is a synthesisable sine wave generator on our website here : http://www.doulos.com/knowhow/vhdl_models/sine_wave_generator/ It includes a perl script to generate a sine wave lookup table of arbitrary dimensions/precision. The code will probably want modifying slightly so it uses LUT based ROM or BRAMs. If I have time, I might add an FPGA optimisd version... HTH Ian -- Ian Poole, Consultant The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. "SneakerNet" <nospam@nospam.org> wrote in message news:PdzWb.41614$9k7.859740@news.xtra.co.nz... > Hi all > > I need some help with regards to generating a sine wave. I thought abt this > problem and some thoughts that came to mind are as follows: > 1. Generate sine values using spreadsheet > 2. Store these values either in ROM or make a table withing VHDL > 3. Write VHDL code and output these values. > > My question is: > Is it better to store these values in ROM (eg. LUT) or directly hardcode the > values. > Is there a website that will explain or give more explanation in this area. > > Cheers > >Article: 66082
Amontec Team, Laurent Gauch wrote: > Hi all, > I am using Webpack ISE to do PAR for Coolrunner. > How to get back all command line from VHDL and UCF parser to JEDEC > generation (parser, synthesis and par works) > The goal is to do a generic project (using webpack IDE interface) and to > get back all ISE command line, and to re-run the ISE command line for an > other VHDL file with minor changes. All the work would be via script for > generating about 50 news configs of our Chameleon POD. Have a look at the chapter about "xflow" in the ISE Documentation. That's the command-line-tool to do the complete flow from synthesis to bitfile generation (I assume you can generate JEDEC-files as well). The options for each of the steps are set in *.opt-files, that reside in $XILINX/epld/data. You can copy those and modify the local copies, and run "xflow" with these instead of the globally available ones. "xflow" is really not that complicated, and is great for using inside scripts, so that should be what you need. -- Sean Durkin Fraunhofer Institute for Integrated Circuits (IIS) Am Wolfsmantel 33, 91058 Erlangen, Germany http://www.iis.fraunhofer.de mailto:23@iis.42.de ([23 , 42] <=> [durkinsn , fraunhofer])Article: 66083
Andre wrote: > How many layers are normally needed for PCBs using low cost FPGAs ?? > > I've just been told by a supposed board layout expert that the 256 pin > BGA version of a Cyclone EP1C6 would require an 8 layer board > (apparently having the entire underside of the device covered by balls > with no free space at the centre makes signal routing a big problem). > > Is this really true ?? A layout technique called "channel routing" can reduce the number of layers significantly. Leon -- Leon Heller, G1HSM Email: aqzf13@dsl.pipex.com My low-cost Philips LPC210x ARM development system: http://www.geocities.com/leon_heller/lpc2104.htmlArticle: 66084
Sean Durkin wrote: > Amontec Team, Laurent Gauch wrote: > >> Hi all, >> I am using Webpack ISE to do PAR for Coolrunner. >> How to get back all command line from VHDL and UCF parser to JEDEC >> generation (parser, synthesis and par works) >> The goal is to do a generic project (using webpack IDE interface) and >> to get back all ISE command line, and to re-run the ISE command line >> for an other VHDL file with minor changes. All the work would be via >> script for generating about 50 news configs of our Chameleon POD. > > Have a look at the chapter about "xflow" in the ISE Documentation. > That's the command-line-tool to do the complete flow from synthesis to > bitfile generation (I assume you can generate JEDEC-files as well). The > options for each of the steps are set in *.opt-files, that reside in > $XILINX/epld/data. You can copy those and modify the local copies, and > run "xflow" with these instead of the globally available ones. > > "xflow" is really not that complicated, and is great for using inside > scripts, so that should be what you need. > Sean, I will try the xflow way. many thanks LaurentArticle: 66085
John Adair <newsreply@loseinspace.co.uk> wrote: : If you were using Xilinx I would point you here : http://support.xilinx.com/bvdocs/appnotes/xapp157.pdf . The examples omit all decoupling capacitors in the layout... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 66086
Hi all, I have installed ISE 6.1.03i, and I can't get impact to program my development board, using the parallel port... in the cable setup all the options other than the serial interface is unavailable. the board and parallel interface work under windows.. and with VMWare... Thanks for your help FouadArticle: 66087
It looks like there are some troubles with debugging an application in sdram while caching is enabled (both instruction cache and data cache are enabled). If I remove the cache, I am able to debug my application from sdram. Could anyone confirm this (I saw a few postings at the xilinx microblaze forum, but I couldn't find an confirmation from xilinx about this behaviour)?! Frank "Ryan Laity" <ryan_dot_laity@x-i-l-i-n-x_pleasenospam_dot_com> wrote in message news:c0dod1$5kk1@cliff.xsj.xilinx.com... > Frank, > > Yes, you can do exactly what you have described. When you use the "dow" > command from the XMD command prompt (after an mbconnect), XMD will use > the available memory interface core to place the .elf at whatever > location has been specified in your linker script. Therefore, you want > to "dow" the final application, not the bootloader. You are essentially > letting MDM/XMD act as your bootloader in this case. > > Once the .elf is downloaded, you can then "con" to run or "stp" (step) > from the command line and see what instruction is causing the problem > you described in your previous post. If the system hangs on one of your > first steps then you probably have a problem with your hardware (likely > logical or timing issue with your memory interface and/or board). If > this is the case, try using the "mwr" and "mrd" commands from XMD to see > if you can get data in and out of your memory correctly. > > You can also try to "dow" your .elf file, do an object dump (mb-objdump) > of the .elf, then use "mrd" on a large block of the instruction memory, > and do a comparison between the dumped .elf and what's in the memory. > If there are any mismatches then there's likely a problem with the > memory interface hardware/timing. > > If it's many instructions into the run, and that instruction memory > location looks correct, then the software is likely at fault. Use that > dumped .elf file to figure out which instruction is causing the problem > and debug accordingly. > > Hopefully you are able to resolve the problem using this information. > If not then please contact our support hotline for more help. > > > Best regards, > Ryan Laity > Xilinx Applications > > Frank van Eijkelenburg wrote: > > Hi, > > > > Is it possible to debug an application which is in sdram by use of xmdstub? > > I have a small bootloader program which programs a final application into > > sdram (by use of xmodem). Now I want to debug this application, is that > > possible or should I use the opb mdm device?! If it's possible, I guess I > > have to build a bootloader with the xmdstub and make a connection. But how > > to get my application into the sdram? Can I use the "dow" command at the xmd > > command line or an option inside gdb to download the application into sdram > > (I'm asking this, because in the normal way the user has to give some input > > via the serial port, but that's the same port for debugging thus I can't > > give any input). And how to step through the code when the application is in > > the sdram?! > > > > TIA, > > Frank > > > > >Article: 66088
The OP did not mention the sample rate relative to clock rate, the phase
relationship of the sine to the sample interval if any, or the required
precision. Without these, it is not possible to offer a 'best' solution. ROM
is fine as long as the number of phase angles supported is small enough to fit
in the address space of the ROM. It may be more efficient however to compute
the sine on the fly using CORDIC, or to use a table plus correction (one design
I did a while back did a linear approx, that was corrected by a small table, and
then that result was corrected by a second small table).
"Gregory C. Read" wrote:
> If you need more than a few points, a ROM would be a better idea. I did this
> to generate a sine wave (via a D/A) for an all digital LVDT synchronous
> demodulation circuit. The beauty of using ROM is you can store many points,
> including multiple frequencies by using the upper address lines to select a
> different set of values.
>
> BTW, I used C and/or Visual Basic to generate the values, writing them
> directly to a binary file, then using the file to program the ROM.
>
> --
> Greg
> readgc.invalid@hotmail.com.invalid
> (Remove the '.invalid' twice to send Email)
>
> "SneakerNet" <nospam@nospam.org> wrote in message
> news:PdzWb.41614$9k7.859740@news.xtra.co.nz...
> > Hi all
> >
> > I need some help with regards to generating a sine wave. I thought abt
> this
> > problem and some thoughts that came to mind are as follows:
> > 1. Generate sine values using spreadsheet
> > 2. Store these values either in ROM or make a table withing VHDL
> > 3. Write VHDL code and output these values.
> >
> > My question is:
> > Is it better to store these values in ROM (eg. LUT) or directly hardcode
> the
> > values.
> > Is there a website that will explain or give more explanation in this
> area.
> >
> > Cheers
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 66089
Hi Folks,
The process below uses two enable signals ANDed together.
some_proc: process (CLK)
begin
if (CLK'event and CLK='1') then
if (CLKEN = '1') and (XYZ = '1') then
-- signal assignment
end if;
end if;
end process;
After synthesis and place and route (targetting XC2V3000-FG676-5) of a VHDL
design that uses this structure in several processes, the critical path
involves the CLKEN signal with the main delay being a net fanout of CLKEN of
52 taking 5.4 ns.
So, the question(s)
(Q1)
Is this style ok or should avoid ANDing enables just like I would avoid
ANDing a clock?
(Q2)
I think that the delay and fanout of CLKEN would be high anyway even if it
was not being ANDed with XYZ - agree?
(the critical path includes a tilo which I assume is the AND taking place
but this tilo is only 0.382 ns)
Many thanks for your time,
Ken
Article: 66090Hi Tal, A detailed reply which goes over the specifics for this solution along with a cof file that you will need will be mailed separately. In a nutshell the EPC16 device is not large enough to hold athe programming data for all three devices if you use the Bitslice PS mode. However a solution that uses compression will allow you to do so. The cof file will contain the settings that you can edit. - Subroto Datta Altera Corp. "tal_h" <tal_h@elbit.co.il> wrote in message news:7fc7c85.0402110014.4b712cdd@posting.google.com... > Hi, > I have a problem with configuration altera FPGA's on my board. > my configuration scheme is: > 1 EPC16 device connected in PPS mode to: > A stratix device on Data0 (EP1S20) & 2 cyclone devices (EP1C12) > connected Data1 & Data2 of the EPC16… > > when I power-up the board, the configuration cycle isn't started, > I can't find the DCLK (this signal stays LOW always!) > the nSTATUS signal goes HIGH ~85mSec after power-up > the CONF_DONE signal stays LOW always. > > I've tried to connect an external OSC to the EPC16 => I didn't work. > > Please advice, > > TalArticle: 66091
"Austin Lesea" <austin@xilinx.com> wrote in message news:c0eg9u$qs52@cliff.xsj.xilinx.com... > Rick, > > What part, and by whom? > I like to check on things when I see an issue such as yours, > Austin > > rickman wrote: > > Austin Lesea wrote: > > > >>Nial, > >> > >>FAEs have the documents, so I would suggest they put in the request to > >>find out from them. > > I can say that I was promised to have parts in my hand by November and I > > am still waiting. 6 week lead time was given to me also from Memec in September for S3, so it should have had shipped in November. I didnt even order because I did not believe that. As I see those who ordered have still not received the parts. Sorry Austin. But for all others - the industry is really really down, leadtimes are longer, parts that you expected to be off-stock are not anymore. I did part order yesterday (from digikey) and was terrified to see how many positions where not available any more :( Antti LukatsArticle: 66092
"ram" <ramntn@yahoo.com> wrote in message news:61c2cc9d.0402112133.75b65c0@posting.google.com... > Pete, > Have you looked at the schematic for the board,sometimes you might > get a way to access the PROM ;other than that,I dont think it is > possible to access PROM. be smart. IT IS POSSIBLE to access the (xilinx config) PROM after configuration if you need it. Antti xilinx.openchip.orgArticle: 66093
Hi there
I'm using the attached module for a dual 7-segment decoder.
It works fine except one thing: the segment should show "1" if the
BCD-code has got the value of 0, so the display shows numbers starting
from 1 up to 100 instead of 0 up to 99.
I gues the answer is pretty easy but I'm not very familar with ABEL
code.
So in my opinion the solution is to add 1 to the current BCD-value (=
Zahl) and then can very easily go through the truth table.
Can somebody help and tell me, where I have to change my code???
Timo
module bcd7_2seg
title 'seven segment display decoder'
" angepasst auf ein Ausgabe a-g und einer Ansteuerung für
" LowerSegment und HigherSegment
" The 5 -bit binary (0 - 64) score is converted into two BCD outputs.
" The integer division '/' and the modulus operator '%' are used to
" extract the individual digits from the two digit score.
" 'Score % 10' will yield the 'units' and
" 'Score / 10' will yield the 'tens'
" a
" ---
" f| g |b
" ---
" e| d |c
" ---
" Zwischengrössen
V7..V0 node;
EN,S5..S0,Clock pin; "Steuereingänge
a,b,c,d,e,f,g pin istype 'com'; "7Seg.Ausgänge Einer
Seg pin istype 'com';
Zahl=[S5..S0];
bcd1 =[V3..V0];
bcd2 =[V7..V4];
ON,OFF = 0,1; " for common anode LEDs
L,H,X,Z = 0,1,.X.,.Z.;
binary = 0; "scratch variable
clear macro (a) {@const ?a=0};
inc macro (a) {@const ?a=?a+1;};
equations
when !EN&Clock then Seg=ON
else when !EN&!Clock then Seg=OFF;
@dcset
truth_table ( Zahl -> [bcd2,bcd1])
clear(binary);
@repeat 64 {binary -> [binary/10,binary%10]; inc(binary);}
truth_table ([bcd2,bcd1,Seg] -> [ a , b , c , d, e , f , g ])
[X,0,ON] -> [ ON, ON, ON, ON, ON, ON, OFF];"
[X,1,ON] -> [OFF, ON, ON, OFF, OFF, OFF, OFF];
[X,2,ON] -> [ ON, ON, OFF, ON, ON, OFF, ON];
[X,3,ON] -> [ ON, ON, ON, ON, OFF, OFF, ON];
[X,4,ON] -> [OFF, ON, ON, OFF, OFF, ON, ON];
[X,5,ON] -> [ ON, OFF, ON, ON, OFF, ON, ON];
[X,6,ON] -> [ ON, OFF, ON, ON, ON, ON, ON];
[X,7,ON] -> [ ON, ON, ON, OFF, OFF, OFF, OFF];
[X,8,ON] -> [ ON, ON, ON, ON, ON, ON, ON];
[X,9,ON] -> [ ON, ON, ON, ON, OFF, ON, ON];
[0,X,OFF] -> [ OFF, OFF, OFF, OFF, OFF, OFF, OFF];
"führende Nullen aus
[1,X,OFF] -> [OFF, ON, ON, OFF, OFF, OFF, OFF];
[2,X,OFF] -> [ ON, ON, OFF, ON, ON, OFF, ON];
[3,X,OFF] -> [ ON, ON, ON, ON, OFF, OFF, ON];
[4,X,OFF] -> [OFF, ON, ON, OFF, OFF, ON, ON];
[5,X,OFF] -> [ ON, OFF, ON, ON, OFF, ON, ON];
[6,X,OFF] -> [ ON, OFF, ON, ON, ON, ON, ON];
[7,X,OFF] -> [ ON, ON, ON, OFF, OFF, OFF, OFF];
[8,X,OFF] -> [ ON, ON, ON, ON, ON, ON, ON];
[9,X,OFF] -> [ ON, ON, ON, ON, OFF, ON, ON];
end
Article: 66094Lasse Langwadt Christensen <langwadt@ieee.org> wrote in message news:<402AC930.2080307@ieee.org>... > > Should be straight forward, not much different from using two small > proms to configure one FPGA, except that one of the proms isn't > connected to the configuration pins of the FPGA. > > From the JTAG side it'll just be a chain of 2 proms and an FPGA, one > programmed with the fpga configuration the other with you general > purpose data. > > The prom connected to the configuration pins on the FPGA configures > the FPGA, the prom connected to I/O's does nothing unless you drive > the pins .. > > -Lasse That's pretty much what I was hoping I could do. Now I need to determine the data format necessary to get the prom configured using the xilinx supplied tools. PeteArticle: 66095
Escenario : Need a clock system with range from ~50Mhz to 150Mhz with as much granularity as possible to drive an FPGA. Could anyone please suggest options on how to better implement this clock system.? I've looked at programmable clocks from Cypress, Maxim-ic, but these require some I2C or 2-wire interface, and I don't have a microcontroller on board, just the FPGA so I'd need to put a I2C core... . I've looked at using the PLL core in the FPGA (Actel in this case), but I find the documentation about it to be extremely poor as to how to really implement it. By the way, if anybody has had experience using the PLL core in Actel, could you please give a simple example on how to use the core generated by "Actgen." I've read the document on "PLL dynamic reconfiguration using JTAG," and I still don't understand completely.... Thanks in advance, DavidArticle: 66096
John Williams wrote: > Hi Sean, > > Thanks for your response. It confirmed a few things I was starting to > think, but it's nice to know I'm not alone! Us partial reconfigurators sure are a rare species. We should stick together, or have some "RA" (Reconfigurators Anonymous) meetings some time... :) > I found the problem - I had disobeyed golden rule #465 of having a > non-module IOB "above" a module area location... I was secretly hoping > there might be some edge-following routing resources that would let me > get away with it, but it seems not... Yeah, should've thought about that, I think that must've been what caused it in my case, too... But I notice that this only produces errors when you use ISE6. ISE5 routes the thing without warning, which of course leaves you with a useless design. So did that solve the problem with the corrupt .NCD as well? -- Sean Durkin Fraunhofer Institute for Integrated Circuits (IIS) Am Wolfsmantel 33, 91058 Erlangen, Germany http://www.iis.fraunhofer.de mailto:23@iis.42.de ([23 , 42] <=> [durkinsn , fraunhofer])Article: 66097
Hi, I need to know where I have to include my .ucf file in XFLOW! Laurent Sean Durkin wrote: > Amontec Team, Laurent Gauch wrote: > >> Hi all, >> I am using Webpack ISE to do PAR for Coolrunner. >> How to get back all command line from VHDL and UCF parser to JEDEC >> generation (parser, synthesis and par works) >> The goal is to do a generic project (using webpack IDE interface) and >> to get back all ISE command line, and to re-run the ISE command line >> for an other VHDL file with minor changes. All the work would be via >> script for generating about 50 news configs of our Chameleon POD. > > Have a look at the chapter about "xflow" in the ISE Documentation. > That's the command-line-tool to do the complete flow from synthesis to > bitfile generation (I assume you can generate JEDEC-files as well). The > options for each of the steps are set in *.opt-files, that reside in > $XILINX/epld/data. You can copy those and modify the local copies, and > run "xflow" with these instead of the globally available ones. > > "xflow" is really not that complicated, and is great for using inside > scripts, so that should be what you need. > ------------ And now a word from our sponsor ------------------ For a quality usenet news server, try DNEWS, easy to install, fast, efficient and reliable. For home servers or carrier class installations with millions of users it will allow you to grow! ---- See http://netwinsite.com/sponsor/sponsor_dnews.htm ----Article: 66098
Tungsten-W wrote: > Hi, Sean: > > Have you seen this type of error or not? I call it Error Of Ghost... > > My design is simple, A+B and A+C...A has 3000+ slices, A's AREA_GROUP has 1 > DCM, 14 BUFG, plus A. > B & C uses two clocks from BUFG... > > A, B, C were implemented and published...A+C was assembled, HOWEVER! A+B > gave me this error...I have > seen this errors every now and then but I simply can't find an answer. > > ERROR:Place - The following 1 components are required to be placed in a > specific > relative placement form. The required relative coordinates in the RPM > grid > (that can be seen in the FPGA-editor) are shown in brackets next to the > component names. Due to placement constraints it is impossible to place > the > components in the required form. SLICE modulator/_n0030 (0, 0) > Constrained by statement: COMPGRP "MODULATE.SLICE" LOCATE = SITE > "SLICE_X0Y191:SLICE_X43Y0" LEVEL 4 ; > > Thank you for reading... I've seen this when I tried to place a MicroBlaze inside a too narrow module. There was plenty of free logic space, but MB just places some components relatively and needs a specific number of slices vertically and horizontally, and that I didn't provide. It looks like in your case module "B" is the problem, specifically the "MODULATE.SLICE"-group... I guess you use some pre-generated netlists in there... Do you have any special IP-cores inside that module? In my case it helped to disable some of MicroBlaze's features, hence the thing became small enough to fit. Maybe there's some things you can disable or something to make it shrink enough to fit reliably. As to way it sometimes works and sometimes doesn't: I find that the tools produce very different results, even if you run them with the same settings and on the same design files. It starts with synthesis, where net names and such vary from run to run, and in the end you sometimes get completely different placed and routed designs. So it's not really a surprise that something like that can happen... -- Sean Durkin Fraunhofer Institute for Integrated Circuits (IIS) Am Wolfsmantel 33, 91058 Erlangen, Germany http://www.iis.fraunhofer.de mailto:23@iis.42.de ([23 , 42] <=> [durkinsn , fraunhofer])Article: 66099
Steve, Question away. I think the thread has allowed folks to vent a little, and to learn why selling FPGAs is not as simple as they may have thought. Those that are paranoid, I am afraid we can not help. Regardless, others benefit from an open and frank discussion. I quite often take a mildly extreme position to help focus the discussion and to entertain (after all, why would anyone read this stuff if it wasn't somewhat entertaining?). Anything I have said is not to be taken as an accusation, but rather as a challenge to explain your views (which you did). If I offended, I apologize, as that was never my intent. Austin
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