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david@therogoffs.com (David Rogoff) writes:
> I'm looking for any numbers/benchmarks of various FPGA tools (Quartus,
Here's a couple numbers. In general it appears that going to an top of
the line AMD or Intel based platform would double your performance.
System
Solaris UltraSparc III 750MHz, 4GB RAM, Solaris 9
Linux Athlon AMD Athlon 1.2GHz, 1GB RAM, Red Hat 7.1
Linux Opteron AMD Opteron 1.8GHz, 2GB RAM, Red Hat AS3
Linux Intel Xeon 2.0GHz, 512MB, Red Hat 9
The Athlon system has lots of other stuff (multiple emacs, mozilla,
etc.) running. The Altera part is a small Cyclone design running
synthesis and place and route using a tcl quartus_sh script. The
Xilinx part is a congested XCV1000E place and route job (from an edif
file), Peak Memory Usage: 308 MB. The Yours column is assuming that
your UltraSparc system is 1.6 times faster than mine. The 3.2GHz Xeon
column is assuming that a 3.2HGz Xeon is 1.6 times faster than my
2.0GHz.
| estimated
Quartus Solaris Linux Athlon Linux Intel | Yours 3.2GHz Xeon
3.0SP2 9m51.495s 9m3.292s 7m12.304s | 6m20 4m30
| estimated
ISE par Solaris Linux Opteron Linux Intel | Yours 3.2GHz Xeon
6.2iSP1 40m24.562s 13m34.757s 17m44.777s | 25m16 11m5
A 2.2 GHz Athlon FX-51 would be almost identical to the 3.2GHz Xeon if
you scale my Opteron performance by 1.22. However, the Athlon FX has a
SpecInt2000 of 1447 and a Xeon scores 1289 (picking two numbers from
www.spec.org) so my scaling is probably not that realistic (I've
scaled across two different architectures/implementations). I haven't
checked what other processes are running on the machines so the
results might be distorted.
Petter
--
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Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Article: 67676I think you want to shrink the design. You can do this by (1) playing with switches in ISE. This could get you typically 10-15% if you get the right combinations. (2) Look at your HDL code and see if you can recode parts to make the design smaller. You might get typically another 10-15% if you get the right tweaks. You might find a piecemeal approach of incremental design might be useful. Have a look at our TechiTips for some ideas http://www.enterpoint.co.uk/techitips.html . If you are then really stuck get management authority to use our design rescue services http://www.enterpoint.co.uk/designrescue.html . It will cost but we do these things all the time for customers and achieve the above shrinkages or better in most cases. Apologies to everyone else for the commercial plugs. -- John Adair Enterpoint Ltd. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Sandi Posl" <tome@myhost.not> wrote in message news:WtD5c.6427$%x4.844057@news.siol.net... > Hello, > > I don't have much experience with RTL and implementing designs, but I > have encountered a strange problem. > > The design I am working on is rather large and I have been forced to > remove some RTL modules from the design to get the total LUT's used down > to 85% (during the synthesis phase, I'm using Synplify PRO) for the > XC2V6000-5FF1152 FPGA. I would prefer to have the complete design > implemented on the FPGA. > > As an experiment, I decided to synthesize my design by defining the > Xilinx Virtex-E XCV3200E-8FF1156 FPGA in Synplify Pro, and the total > LUT's used came to 95% (and the Virtex-II is almost twice the size!). > > Why is this happening, I thought that the Virtex-II is proportionally > 'larger' that the Virtex-E? > Am I not configuring options in Synplify correctly for the XC2V6000 FPGA > (Virtex-II)? > Could this be because the two FPGA's I have mentioned are so different, > that the design 'fits easier' into the Virtex-E? > > > The hardware platform I already have has the Virtex-II FPGA on it, so I > have to implement my design on this FPGA. > > Thank you in advance for any help. > > Regards > > Sandi > > P.S. I have not used my actual email address so that I don't get spam > sent to my email address. :-) If you would prefer to contact me > directly, my email address is sandip<at>flextronics<dot>si >Article: 67677
Le Tue, 16 Mar 2004 14:37:59 -0800, David Rogoff a écrit : [...] > I assume the floating licenses will share across - correct? Any [...] No, the net license for Linux is different from the one needed for Solaris or Windows. I am running Quartus on a RedHat9 box and I had to buy a specific license. If someone from Altera can explain why the license is different... -- Stéphane ACOUNIS "Oh le beau mur, il faut qu'je freine!" Ayrton SegaArticle: 67678
St?phane Acounis <Dans.le@reply.to> wrote: : Le Tue, 16 Mar 2004 14:37:59 -0800, David Rogoff a ?crit : : [...] : > I assume the floating licenses will share across - correct? Any : [...] : No, the net license for Linux is different from the one needed for Solaris : or Windows. : I am running Quartus on a RedHat9 box and I had to buy a specific license. : If someone from Altera can explain why the license is different... I have a Quartus 4.0 Linux test license and could run Windows Quartus 3 from the Webdownload on a remote machine with FLEXLM tunneld on Wine. Some wine hacks are still needed however, not yet in Wine CVS... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 67679
Le Wed, 17 Mar 2004 12:15:13 +0000, Uwe Bonnes a écrit : > I have a Quartus 4.0 Linux test license and could run Windows Quartus 3 from > the Webdownload on a remote machine with FLEXLM tunneld on Wine. Some wine > hacks are still needed however, not yet in Wine CVS... Well, my Linux license can't be used by a Solaris Quartus, I haven't tried with Windows. I am using Quartus2 v3. -- Stéphane ACOUNIS "Oh le beau mur, il faut qu'je freine!" Ayrton SegaArticle: 67680
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:c39fgh$m7$1@news.tu-darmstadt.de... > St?phane Acounis <Dans.le@reply.to> wrote: > : Le Tue, 16 Mar 2004 14:37:59 -0800, David Rogoff a ?crit : > > : [...] > : > I assume the floating licenses will share across - correct? Any > : [...] > > : No, the net license for Linux is different from the one needed for Solaris > : or Windows. > : I am running Quartus on a RedHat9 box and I had to buy a specific license. > > : If someone from Altera can explain why the license is different... > > I have a Quartus 4.0 Linux test license and could run Windows Quartus 3 from > the Webdownload on a remote machine with FLEXLM tunneld on Wine. Some wine > hacks are still needed however, not yet in Wine CVS... > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Due to contractual obligations with Mainsoft we are required to track Quartus Linux licenses separately. The Mainwin software is used to provide the "port" of the graphical applications in Quartus to the UNIX environment. The altera_mainwin_lnx entry in the flex license is required only for the Linux platform. The altera_mainwin entry is required for all UNIX (Solaris, HP and Linux) platforms. A quartus floating license entry is required for all platforms including PC. If you purchase a Quartus floating license for Solaris you will be able to use Quartus on Solaris and HP and Windows. If you buy a floating license for the Linux you will be able to use Quartus on all platforms. - Subroto Datta Altera Corp.Article: 67681
mike_treseler@comcast.net (Mike Treseler) wrote in message news:<865ab498.0403161137.2c4c5358@posting.google.com>... > "Kevin Neilson" wrote: > > The best of both worlds is to do all the design in HDL, and then use a tool > > like Synplify's "HDL Analyst" to look at a schematic version of the > > synthesized code. Using Synplify one can see either the RTL or structural > > schematic. > > I agree with Kevin. > It is a good thing to look at the rtl/netlist schematics. > But let the computer draw them for you. > Note that QuartusII ver 4.0 also includes an rtl viewer. > > -- Mike Treseler The only problem with that is that those schematics are total ____ for anything but the simpleste cells. If you have more than a dozen items, the tools have absolutely no sence of repetition. If a kid see a dozen identical items labeled 0 to n in a pile of others, they might place them in a straight line, but these idiot renderers will splat them any old place becuase they have no concept of regularitiy combining with control, they treat all instances as equals. I asked these tool vendors to allow the end user to accept edits at least for placement of instances and then to remember those as hints. But they always regenerate them from scratch. In the real world it is often neccesary to write HDL in a perverse way to find the best performance the synthesis will create, and that means creating awkward instance hierarchies. I am stuck with pen & paper. If I used the schematic tools, they write the crappiest HDL they can so its the lesser of 2 evils. FWIW, the best schematic tool I ever used was Compass tools for VLSI, very Macish, quite dated goin back 20yrs but truelly an awesome SW and very much gone. It allowed true edit in place of symbols in the context of a parent schematic making it 10x more productive than regular PCB oriented trash like Veriworst. The reason why they got it right is simple, the underlying code was exactly the same for all tools, edit in place mask editer, schematic. A mask editer written as badly as most schematic tools would be kicked out. I looked at "Electronics Workbench" at the DAC show years ago, the reps hadn't a clue what edit in place meant, they thought I was talking of edit, in the place you are, on yer bum, so by that def, they had it. The other issue I now see is that even the perfect schematic tool with perfect written Verilog netlist would now have nother problem, I would want it to write out the Verilog in a precise format and or to write out a cycle equivalent version in C line by line equivalent. Thats really asking too much. end of rantArticle: 67682
hi, does anybody knows where can i get techinical information about how a FPGA works, it's internal architecture, the internal matrix, etc? thanks, parisArticle: 67683
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:865ab498.0403161137.2c4c5358@posting.google.com... > "Kevin Neilson" wrote: > > The best of both worlds is to do all the design in HDL, and then use a tool > > like Synplify's "HDL Analyst" to look at a schematic version of the > > synthesized code. Using Synplify one can see either the RTL or structural > > schematic. > > I agree with Kevin. > It is a good thing to look at the rtl/netlist schematics. > But let the computer draw them for you. > Note that QuartusII ver 4.0 also includes an rtl viewer. > > -- Mike Treseler The original poster asked for a schematic editor, to enter schematics along with predefined symbols for ALU's registers etc. Just to make sure there is no confusion, the Quartus Schematic editor (aka Block Editor) is a different application from the RTL viewer. This is your classical schematic editor which allows you to place symbols which are predefined or created on the fly, in place editor node names, create busses and hook up the ports .... The purpose of the RTL viewer is to allow the user to get a visual description/understanding of the logic generated during RTL synthesis by Quartus. It requires that the design has been processed by quartus_map i.e. the synthesis application. The contents of the RTL viewer cannot be modified or saved into a file. The RTL viewer is not available in the Free Web Edition. - Subroto Datta Altera Corp.Article: 67684
John It would help if you could tell us where this quote comes from, and what device it refers to. Wouldn't you agree? Peter Alfke > From: John Black <black@eed.com> > Organization: EED > Newsgroups: comp.arch.fpga > Date: Tue, 16 Mar 2004 20:44:20 -0700 > Subject: clock rising edge alignment > > Hi, > I am having hard time in understanding the following paragraph, > > slave can run both faster and slower than the master, as long as > the rising edges for a specific clock( master as well as slave) aligns > with all rising edges of equal or higher frequency clocks. > > How to interprete "aligns" here? If the clock frequencies are > different, how come their rising edges ALL aligning? To me the only case > is one clock is 2^n times faster than the other, but from the larger > context of this paragraph, this is not true. > > > >Article: 67685
Does anyone know of any documentation on what the Xilinx bit-file (the one that is finally downloaded onto the FPGA to configure it) format is? A few hours spent searching the Xilinx website and the net have not yielded much useful information. I am trying to modify a configuration bitstream so that a simple circuit I am inplementing on the FPGA can be moved to different parts of the FPGA without having to go through Xilinx's tools. The ultimate goal is to modify the configuration on-the-fly using the Virtex IIP's ICAP (Internal Configuration Access Port) and embedded PowerPC cores. But to get started, I first need to figure out what the configuration bitstream looks like, and what parts I need to modify. Xilinx's xapp662 deals with using the ICAP, but their code only makes very simple changes to the configuration and they do not even say how they figured out precisely which bytes to change. Any help at all will be much appreciated. Thanks, MahimArticle: 67686
Hello, I'm trying to simulate a target memory write transaction with the PCI-X core V5_72. Therefore I use the procedures delivered with the example files with the core (Write_dword_x). In the cfg_x.vhd file I configured the BAR's like following: -- BAR0 cfg_int(95 downto 64) <= X"ff000000"; -- 16MB cfg_int(408) <= '1' ; -- Memory space -- BAR1 cfg_int(127 downto 96) <= X"ff000000"; -- 16MB cfg_int(409) <= '1' ; -- Memory space -- BAR2 cfg_int(159 downto 128) <= X"ff000000"; -- 16MB cfg_int(410) <= '1' ; -- Memory space -- BAR3 cfg_int(191 downto 160) <= X"ff000000"; -- 16MB cfg_int(411) <= '1' ; -- Memory space -- BAR4 cfg_int(223 downto 192) <= X"ff000000"; -- 16MB cfg_int(412) <= '1' ; -- Memory space -- BAR5 cfg_int(255 downto 224) <= X"ff000000"; -- 16MB cfg_int(413) <= '1' ; -- Memory space -- Expansion ROM BAR cfg_int(351 downto 320) <= X"00000000"; cfg_int(414) <= '0' ; -- Split Transaction Target cfg_int(415) <= '1' ; i.e. all BAR's are mapped into memory-space. But I can only write into the mapped BAR0-register, when I change the configuration to I/O space, i.e. cfg_int(408) <= '0' . Does anyone have an explanation for that behaviour? Thank you for answers, MatthiasArticle: 67687
This subject has been discussed multiple times on this newsgroup recently. You should be able to find these discussions in newsgroup archives either through www.fpga-faq.com/archives/, or through Google's usenet archives. Mahim Mishra wrote: > Does anyone know of any documentation on what the Xilinx bit-file (the > one that is finally downloaded onto the FPGA to configure it) format > is? A few hours spent searching the Xilinx website and the net have > not yielded much useful information. > > I am trying to modify a configuration bitstream so that a simple > circuit I am inplementing on the FPGA can be moved to different parts > of the FPGA without having to go through Xilinx's tools. The ultimate > goal is to modify the configuration on-the-fly using the Virtex IIP's > ICAP (Internal Configuration Access Port) and embedded PowerPC cores. > But to get started, I first need to figure out what the configuration > bitstream looks like, and what parts I need to modify. Xilinx's > xapp662 deals with using the ICAP, but their code only makes very > simple changes to the configuration and they do not even say how they > figured out precisely which bytes to change. > > Any help at all will be much appreciated. > > Thanks, > Mahim -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 67688
Hendra Gunawan wrote: > Hi folks, > I have Xilinx Webpack 6.2i and ModelSim Starter Edition 5.7g. I know that > ModelSim has 500 lines limitation, beyond that it still works but run > slower. So, can I overcome the limitation by using HDL Bencher? Does HDL > Bencher has any limitation? Can it do what ModelSim does? Mainly accepting > my own testbench and injecting the signal to the Unit Under Test but without > any line limitation? I think there is some confusion as to what HDL Bencher really is. HDL Bencher is a tool that allows you to enter input stimulus or expected output data for for design via a waveform editor and it will generate a VHDL and/or Verilog testbench based on the waveform that can be used with any HDL simulator like ModelSim. So HDL Bencher is not a simulator itself, it is a graphical testbench editor that can create a "relatively simple" testbench to drive stimulus and check outputs of your design under test. To answer your question, no, it will not get you around the 500 line limit in the Modelsim-XE Starter Edition. I see you have a SJ State e-mail address so my suggestion to you is if you are a student to see if you have access to a full ModelSim license through your University. It is my understnding that Mentor has a very good University program and perhaps you may have access to a faster simulator through that. Otherwise, ModelSim-XE Starter will continue to run if you have more than 500 lilnes but it might take a while to complete the simulation (but at least it is free). -- BrianArticle: 67689
ian wrote: > Hi, Folks, > > Where can I find a Xilinx RAMB16_Sm_Sn DPRAM's timing diagram? The timing diagrams for the Virtex-II RAM can be found in the Virtex-II Users Guide (http://direct.xilinx.com/bvdocs/userguides/ug002.pdf) in Chapter 3. See the section on "Using Block SelectRAM Memory." The actual timing numbers for the RAM can be found in the datasheets or better yet, the the timing analysis portion of the software after you target that component. -- BrianArticle: 67690
Hi, If you don't get a response from the newsgroup, I would encourage you to use the Xilinx support website for this question, and send your simulation files with it so that someone can debug the issue. Eric Matthias Müller wrote: > > Hello, > I'm trying to simulate a target memory write transaction with the PCI-X > core V5_72. Therefore I use the procedures delivered with the example > files with the core (Write_dword_x). In the cfg_x.vhd file I configured > the BAR's like following: > > -- BAR0 > cfg_int(95 downto 64) <= X"ff000000"; -- 16MB > cfg_int(408) <= '1' ; -- Memory space > -- BAR1 > cfg_int(127 downto 96) <= X"ff000000"; -- 16MB > cfg_int(409) <= '1' ; -- Memory space > -- BAR2 > cfg_int(159 downto 128) <= X"ff000000"; -- 16MB > cfg_int(410) <= '1' ; -- Memory space > -- BAR3 > cfg_int(191 downto 160) <= X"ff000000"; -- 16MB > cfg_int(411) <= '1' ; -- Memory space > -- BAR4 > cfg_int(223 downto 192) <= X"ff000000"; -- 16MB > cfg_int(412) <= '1' ; -- Memory space > -- BAR5 > cfg_int(255 downto 224) <= X"ff000000"; -- 16MB > cfg_int(413) <= '1' ; -- Memory space > -- Expansion ROM BAR > cfg_int(351 downto 320) <= X"00000000"; > cfg_int(414) <= '0' ; > -- Split Transaction Target > cfg_int(415) <= '1' ; > > i.e. all BAR's are mapped into memory-space. But I can only write into > the mapped BAR0-register, when I change the configuration to I/O space, > i.e. cfg_int(408) <= '0' . > Does anyone have an explanation for that behaviour? > Thank you for answers, > MatthiasArticle: 67691
J?rgen wrote: > Hi, > I invoke the Modelsim simulator from ISE Foundation (version 6.1). > After changing one or more vhdl source files in the ISE, how can I > hierarchically read in the modified vhdl sources ? Are all of the sources added to the project? In other words, do you see all of the files for your design listed in the "Sources in Project" window? If not, you need to add the files to the project by selecting the Project --> Add Source... pull down. > Background: While invoking Modelsim by double click on "Simulate > Behavioral Model" for the top-level testbench vhdl file, the vhdl > files used for simulation do not correspond to the actual ones. The only way I could understand this happening is if not all design files are added to the project. The way this works in Project Navigator is it will take all of the files in the hierarchy of the design and build a ModelSim DO file in the background in which compiles all of the files, invokes simulation, adds the proper debug and waveform windows, and runs the simulation. If not all of the design files are added to the project, the DO file will not contain corresponding vcom/vlog compilation commands for the missing files and you will likely see what you are describing. -- BrianArticle: 67692
I know this subject has been kicked around a lot here, but here we go again. Where can one get a small quantity of XC3S400s? I already have some on indefinite back order at Avnet. Maybe there is another source? Reminds me of John Cleese in the cheese shop: "Do you in fact have _any_ Spartan IIIs?" "Yes." "Really?" "No."Article: 67693
ReConFig'04 International Conference on Reconfigurable Computing and FPGAs September 20-21, 2004 Colima, Mexico Call for Papers The Mexican Society for Computer Science (SMCC) invites researchers from Mexico and other countries to submit research papers to the International Conference on Reconfigurable Computing and FPGAs 2004, ReConFig'04, to be held at the city of Colima, Mexico, on September 20-21, 2004. The conference will be held in parallel to the International Conference in Computer Science 2004, ENC'04. The aim of the conference is to bring together researchers, students, and industry working on all aspects of reconfigurable computing and FPGA devices. The conference seeks to promote the use of programmable logic for research and education in Iberoamerica, and also to create links among different research groups by offering a forum where results of their latest research work can be presented. Conference Topics. ReConFig'04 covers a broad spectrum of topics including, but not limited to: Architectures * Reconfigurable architectures * Custom computer systems * Systems on reconfigurable chip (SoRC) * Embedded systems * Fault tolerant systems * Hardware inspired on biologic structures, neural networks and genetic algorithms * Low power reconfigurable architectures Applications * Communications and network applications * Mobile applications * Digital signal processing applications * Algorithms implemented on FPGAs * Rapid prototyping Tools * Reconfiguration techniques, dynamic reconfiguration, support and applications * Languages and compiling techniques * Simulations and programming environments for FPGAs (CAD) * UML and HDLs * Hardware/software libraries * Verifications and test of reconfigurable circuits and systems * Hardware/software codesign and cosimulation Education * Courses and laboratories on programmable devices, FPGAs and reconfigurable computing * HDLs, FPGAs and reconfigurable computing tutorials * Interactive tutorials and on-line courses * Integrating reconfigurable systems into university curricula * Discussions about the potential of FPGAs and reconfigurable computing Paper Submission Instructions Electronic submissions of full papers are due on May 14th, 2004. Full papers should have a length of up to 10 pages and can be written in Spanish or English. They have to be submitted for evaluation as a PDF or PostScript file through the ReConFig04 web page. Further instructions for electronic submission and paper formatting will be published in the conference sites: http://ccc.inaoep.mx/fpgacentral/reconfig04 and http://enc.smcc.org.mx/?e=FP Conference Proceedings. The conference proceedings will be published by the Mexican Society for Computer Sciences. The best papers of the conference will be invited to submit a Spanish version of the document to the IEEE Transactions for Latin America. Important dates Paper Submission: May 31, 2004 Acceptance Notification: June 18, 2004 Camera-Ready Papers: July 2, 2004 Conference: September 20 - 21, 2004 Organization ReConFig'04 René Cumplido, INAOE Claudia Feregrino, INAOE Miguel Arias, INAOE SMCC Chair Jesus Favela, CICESE ENC'04 Chair Edgar Chavez, UMich More information: http://ccc.inaoep.mx/fpgacentral/reconfig04 http://enc.smcc.org.mx/?e=FPArticle: 67694
On a sunny day (Wed, 17 Mar 2004 02:37:55 GMT) it happened "Stephan Buchholz" <sbuchhol@sprynet.com> wrote in <7SO5c.6683$GQ3.4978@newsread3.news.atl.earthlink.net>: >Take a look at the new Virtex II Pro board from Insight Memec > >At about $200 it's seems to be a good buy > > >"jerome" <jm_contact2002@yahoo.fr> wrote in message >news:4056deca$0$282$626a14ce@news.free.fr... >> Hi everybody, >> >> I would like to get some dev. board with FPGA. I am now thinking about >> the Spartan 3, especially the one provided by Avnet. >> >> Could you please tell me following infos: >> - Are there some troubles by using this board on a 5V or 3.3V PCI bus? >> - What is the AvBus? How many pins on this bus? What are the signal >> provided (several reset, clk?...). >> - One of my aims is to manage video inputs or output with this device, >> and I plan to use some daughter boards I would use or design by my own. >> Has somebody tried it (including ADC, RAMDAC......)? With this kit or >> others? some feedback? I have 2 boards eurocard 160x100mm connected to the Digilent digilab2 (that is a Spartan 200). There is video ADC on it, LCD display, card reader, several xtal osc, video amps, sync processing stuff, all works. But it becomes a big thing, as the boards plug in the side. Also the leads are too long.... But for prototyping etc.. this works very well. To reduce on connectors I have one big D and then split that out via cables to R, G, B, Y, U, V etc.. Allows me to test a setup really quick. Regulators are also on the plug in boards. JPArticle: 67695
Have you bothered looking at the FPGA vendor's websites, particularly at the
data sheets???
paris wrote:
> hi,
>
> does anybody knows where can i get techinical information about how a FPGA
> works, it's internal architecture, the internal matrix, etc?
> thanks,
>
> paris
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 67696
That said, it would be nice if the RTL viewer had an edit option that would
allow the user to move the blocks around to make the output more presentable.
I'm not talking about reconnecting the wires or changing the logic at all, just
an editor that allowed the schematics to be rearranged so that they could be
used in the documentation of a design.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 67697John wrote: > > > First, you need to do more than just look at web pages. ISI is a > > company that you need to talk with to get info on just what they do and > > don't have. They have a full line of PGA adapters. It is unlikely that > > they can't fit another socket. > > I got a quote back from them and as I expected the CPU socket route will > cost a lot. They don't have anything already made so they say it will > have to be cutsom. The price would include: PCB Design, PCB Fabrication, > PCB Fabrication Test, Solder Stencils, and Setup. This is especially > not cost effective for small quantities. Here are the estimates (based > on board complexity): > > For 2 Boards: $10000-12000 > For 50 Boards: $14000-15000 > > As you can see, this is very expensive (especially for small quantities). That's too bad. But you can still try to find something that will fit the socket and then roll your own board to connect to that. You can do a board layout with free tools and get one made for under $50. But you need to find a way to plug it in. I think some of the connector people sell pins to use on a board to allow it to fit sockets. You have to layout the pins on your board and will likely have to hand solder them. But you can end up with a complete solution for around $100. > > If you plug into the CPU socket, you don't need to build any of the > > other stuff at all. I am sure you can get adequate info on socket 7. > > Intel had to document it for the chip makers. This would be part of the > > chip spec. If not Intel, then AMD likely has a spec. They made parts > > for it too, didn't they? Why do you need a socket that will be long > > lived? Changing your FPGA design for a different socket should be no > > big deal if you need to do that in a couple of years. Are you going to > > mass produce this thing? > > When I mentioned board components I didn't mean the socket interface but > the actual chips on the board (memory controller, bus controllers, etc). > I wondered how wwell this was documented in terms of interfacing with > the processor. I also worried that this would result in getting tied > into a specific motherboard because it would only work with that > specific chipset. As you can see from the costs mentioned above the cost > of moving to a new socket would be very high! I figured that if I used > PCI I could design a PCI-SBC that would interface with the other cards > on the bus. At minimum it would need an FPGA, memory, support chips > (bus, memory, configuration, etc), and a PCI interface. The rest could > be on PCI cards that I can get for $20 at any local electronics store. > I've seen FPGA PCI (busmaster) cards go for much less than $5000-$6000 > each and with those cards I don't have to order more than one at a time > (this is just prototyping, not mass production, at least for now). > Hopefully I can find something much cheaper than even that. The interface to the CPU *has* to be the same on all boards with that socket. The CPUs are not going to change depending on the chip set. Your software must be written to match the motherboard, but you will have that regardless of what approach you take. Even with PCI cards, your software will only support the card it is written for. If you go with a PCI approach, you are always limited to the slow bus speeds relative to the mobo CPU interface. For example, PCI is 133 MB max. USB2.0 is 60 MB max. How many USB 2.0 can you support while also talking to an IDE or SCSI controller via the PCI bus? The bandwidth runs out very quickly with modern devices. USB2.0 and IDE are built into the Northbridge on most boards now. If you like the XC3S400, maybe we can do something cooperatively and I can design and make the board? My board is very crowded, but adding PCI is something I am planning on in the next year. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67698
Hal Murray wrote: > > > No, in fact, I had not noticed that there are also some pure PCI > > backplanes, so that should be better for you. > > What's a "pure" PCI backplane? > > Where do the clocks come from and/or who does the bus arbitration? > > Got a sample URL? I just mean it is PCI without the PICMG slot. http://www.globalamericaninc.com/backplanes/pci_bp.php I don't know how they handle the bus master issues, but CPCI is designed for a passive backplane and the master is on the CPU card. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67699
1)I'm searching for an PC104 Evaluation Board (not PC104+ !!!) with a an Altera FPGA. 2)Where can I get a PC104 Core in VHDL ? Thanks, Manfred
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