Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 67725

Article: 67725
Subject: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
From: "Chris Cheung" <chris_cheung66@hotmail.com>
Date: Thu, 18 Mar 2004 01:44:36 GMT
Links: << >>  << T >>  << A >>
I think you have to check your code....the common mistake is signal
contention in this case...that means more than one process is driving the
same signal.

good luck

Chris

"Kirstie Wong" <csleunc@essex.ac.uk> wrote in message
news:5607e00d.0403171203.491de4e8@posting.google.com...
> Hello, guys, i am implementing a Finite State Machine using VHDL, and
> trying to get it synthesis, but i came up with the error with
>
> =========================================================================
> *                         Low Level Synthesis
>  *
> =========================================================================
> WARNING:Xst:528 - Multi-source in Unit <state_control_module> on
> signal <next_state<2>1> not replaced by logic
> Signal is stuck at GND
> WARNING:Xst:528 - Multi-source in Unit <state_control_module> on
> signal <next_state<3>1> not replaced by logic
> Signal is stuck at GND
> WARNING:Xst:528 - Multi-source in Unit <state_control_module> on
> signal <next_state<0>1> not replaced by logic
> Signal is stuck at GND
> WARNING:Xst:528 - Multi-source in Unit <state_control_module> on
> signal <next_state<1>1> not replaced by logic
> Signal is stuck at GND
> ERROR:Xst:415 - Synthesis failed
>
> from the XST
>
> what is the problem? and how can i solve it, it is very urgent, i am
> only a beginner, please help~ =(
>
> it seems that signal is stuck at ground in the schmetics from a MUX,,
>
> here is some of my code that i think the problem i had, the fsm, is 3
> process.
>
> next_state_logic: process (current_state, TS_EWFR, TS_NSLS,
> EW_TRAFFIC, NS_TRAFFIC)
> --TS_EWLS, TS_NSFR
> begin
> case current_state is
>
> when state0 =>
> next_state <= state1;       -- default assignment to avert latch
> SHORT_START <= '0';
> LONG_START <= '1';
> if ( EW_TRAFFIC = '1' and NS_TRAFFIC = '0') then
> if ( TS_EWFR = '0') then
> next_state <= state1;
> --SHORT_START <= '0';
> --LONG_START <= '1';
> else
> next_state <= state4;
> end if;
> elsif ( EW_TRAFFIC = '0' and NS_TRAFFIC = '1') then
> if ( TS_NSLS = '1') then
> next_state <= state7;
> else
> next_state <= stateA;
> end if;
> else
> next_state <= state1;
> end if;



Article: 67726
Subject: Re: PC104 Evaluation Board
From: johnjakson@yahoo.com (john jakson)
Date: 17 Mar 2004 17:54:32 -0800
Links: << >>  << T >>  << A >>
"Manfred Balik" <e8825130@stud4.tuwien.ac.at> wrote in message news:<40589aca$0$17706$3b214f66@tunews.univie.ac.at>...
> 1)I'm searching for an PC104 Evaluation Board (not PC104+ !!!) with a an
> Altera FPGA.
> 2)Where can I get a PC104 Core in VHDL ?
> Thanks, Manfred

http://www.fpga-faq.com/FPGA_Boards.shtml

or google <PC104 Evaluation Board altera>

might help

Article: 67727
Subject: Re: newbie question about fpga internals
From: Wing Fong Wong <wing@tartarusdontspamme.uwa.edu.au>
Date: Thu, 18 Mar 2004 02:15:16 +0000 (UTC)
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote:
> In this fast-moving field, any hardcover book would be hopelessly obsolete.
I've got one of those hopelessly obsolete books. Published in 1990
"Digital systems design using progammable logic devices" by Lala, P.K.
If you compare what was written in that book to what programmable logic
is like currently you can see just how far we've come.
> Most FPGAs are of the look-up-table-based reconfigurable flavor, commonly

> called "SRAM-based" although that is a misnomer.
> For that type, there are two dominant manufacturers, Altera and Xilinx (in
> alphabetical order!). Their websites are full of interesting information.
Thats probably the best source of current info. The manufacturers are always
proud to declare that they have the fasted and best technology of the time 
and it up to the consumer to evaluate what is really best for them. Although
with the amount of infomation out there, one can quite possiblly be over
loaded by the quantity.
> 
> Peter Alfke, Xilinx Applications
> ====================
> 
-- 
Wing Wong.
Webpage: http://wing.ucc.asn.au


Article: 67728
Subject: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
From: "Kirstie Wong" <csleunc@essex.ac.uk>
Date: Wed, 17 Mar 2004 18:54:27 -0800
Links: << >>  << T >>  << A >>
Thankx for you guys.i go and have a look at it. Thank you

Article: 67729
Subject: Re: Spartan III availability
From: "Bob" <nimby1_not_spmmm@earthlink.net>
Date: Thu, 18 Mar 2004 03:01:06 GMT
Links: << >>  << T >>  << A >>

"Brad Eckert" <nospaambrad1@tinyboot.com> wrote in message
news:7d4cc56.0403170952.6724372d@posting.google.com...
> I know this subject has been kicked around a lot here, but here we go
> again.
>
> Where can one get a small quantity of XC3S400s? I already have some on
> indefinite back order at Avnet. Maybe there is another source?
>
> Reminds me of John Cleese in the cheese shop:
> "Do you in fact have _any_ Spartan IIIs?"
> "Yes."
> "Really?"
> "No."

Too funny. Hopefully it won't end the same way as that skit did (violently,
as I recall).

Bob



Article: 67730
Subject: Re: Cyclone refuses quartusII bitfiles
From: "Subroto Datta" <sdatta@altera.com>
Date: Thu, 18 Mar 2004 03:21:23 GMT
Links: << >>  << T >>  << A >>

<eddy_reply@xs4all.nl> wrote in message
news:4058b425$0$129$e4fe514c@dreader4.news.xs4all.nl...
> Once in a while I have problem uploading quartusII bit file into cyclones.
The bitfiles are fully succesfull
> generated using QuartusII v3 SP1 or SP2 and uploaded using JTAG
byteblaster tools. Sometimes
> (lets say one in every thirty builds) the bit file is refused by the
cyclone (located on the NIOS development
> board).
> Only thing to get a new (working) bitfile is to make minor changes (add or
remove a FF) and try again.
>
> Is this a known problem? Does anyone have a clue how to work around this?
>
> Regard Eddy
>
>

Eddy, We have not had any reports of this before. When you encounter this
problem, please send me the sof so that we can find out the root cause.

Thanks,
- Subroto Datta
Altera Corp.



Article: 67731
Subject: logic Core: getting started(newbie)
From: wenghong <wenghong08@yahoo.com>
Date: Wed, 17 Mar 2004 20:02:01 -0800
Links: << >>  << T >>  << A >>
Hi all elites, 

I'm a newbie to Pci logicore. Anyone could offer some advice on how to implement 
the Ping example provided and which files to open? quite confused with too much 
professional info inn the design and implementation guide. ur help would be 
deeply appreciated. =) 



Article: 67732
Subject: Re: Device/Board Selection (CPU Design)
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 17 Mar 2004 23:45:27 -0500
Links: << >>  << T >>  << A >>
john jakson wrote:
> 
> that leaves one easy option left, how about the slot A format a PCB
> edge connector or perhaps the Intel slot design.
> 
> Only problem is its still a difficult spec to get hold of as its
> basically the Alpha EV bus licensed to AMD back when it was 100MHz
> double pumped IIRC.
> 
> There are always lots of older 500MHz Athlon systems out there that
> used this connector for which you could easily trash the cpu to
> examine the design. These mobos with Slot package are very cheap
> available but the boards probably won't have USB1.1 let alone 2.0.

There is also the Socket 1 design by Intel.  I had forgotten about
that.  The bus speed is definitely slower, but it would certainly be the
quickest and easiest way to get something up and running, possibly even
easier than PCI if you can get the info on the interface.  I bet if you
poke around the PC hobbiest newsgroups you can find someone who has info
on that or can point you to it.  I was posting for awhile when I wanted
to build my own machines and found some very knowledgeable people
there.  Socket 1 is also a good place to start in the sense of being
simpler than the newer double and quad data rate interfaces.  Your board
might still need on board power regulators though, since the PII and
PIII CPUs were not as low voltage as FPGAs are today.  I'm not sure how
low the regulator spec goes.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 67733
Subject: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
From: ramntn@yahoo.com (ram)
Date: 17 Mar 2004 21:51:49 -0800
Links: << >>  << T >>  << A >>
Hi 
Let me explain what is meant by Multisource,which will help you to
resove your issue easily.

Multi Source Unit - When a signal is driver by two sources, the signal
get stuck at unknown condition.
The following VHDL example will help you understand,


A <= C;
.......( more concurrent assignment statements )
......
......

A <= B;


when you have a situation described as above you get a Multisource
unit error.
you have to go thro your code and find out yourself.
bye

Ram

Article: 67734
Subject: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
From: ramntn@yahoo.com (ram)
Date: 17 Mar 2004 21:56:32 -0800
Links: << >>  << T >>  << A >>
hi
  your next state is a vector , what abt your state1 is that a vector too.
need you port and signal description to analyze your  code
ram

Article: 67735
Subject: Re: Altera Quartus II 4.0 won't talk to ByteBasterMV
From: "Simon Peacock" <nowhere@to.be.found>
Date: Thu, 18 Mar 2004 20:22:36 +1300
Links: << >>  << T >>  << A >>
How about making the patch available on the Altera web site.... its a farley
critical issue.  A bit of a no-go bug really... and the Altera service packs
are a bit big when they are released :-) you have to download the whole
Quartus again to get a service pack don't you ?

Simon


"Subroto Datta" <sdatta@altera.com> wrote in message
news:ca4d800d.0403171322.407da6c6@posting.google.com...
> george.martin@att.net (George) wrote in message
news:<e9d879fa.0403121402.2f50c71a@posting.google.com>...
> > I've just completes a design change to an Altera ACEX1K100 device.
> > It's running a NIOS processor and I added more serial ports.  Not a
> > big deal.
> >
> > While waiting for the new prototype boards I upgraded from Quartus II
> > 2.2 to Quartus II 4.0.
> >
> > When I connect the new boards using Altera ByteBlasterMV (PC parallel
> > to JTAG) and attempt to download this new configuration the
> > programming window just zips through (less than 1 sec).  It says it's
> > done but new configuration has NOT been loaded.
> >
> > If I revert to Quartus II Ver. 2.2 BOTH old and new boards can be
> > loaded with either old or new configuration.
> > If I upgrade to Quartus II 4.0 NEITHER old or new boards can't be
> > loaded with any configuration.
> >
> > Anyone seen this??
> >
> > Any suggestions??
> >
> > Thanks
> > George
>
> Hi George and Kari,
>
> The ACEX1K problem that you report has been verified. For the benefit
> of everyone here is the problem description:
>
> A problem in the Quartus II 4.0 full and web edition software prevents
> successful JTAG-based configuration of ACEX 1K devices. This problem
> only affects the Programmer and does not affect configuration file
> (SOF) generation. All Altera download cables including the USB
> Blaster, MasterBlaster, ByteBlaster II, and ByteBlasterMV are
> affected.
>
>
> Fix for the problem:
> Software patch 0.18 for the Quartus II software version 4.0 resolves
> this problem. To request this patch, please contact Altera Customer
> Applications at http:\\mysupport.altera.com. This fix will be included
> in Quartus II 4.0 Service Pack 1.
>
> - Subroto Datta
> Altera Corp.



Article: 67736
Subject: Re: newbie question about fpga internals
From: "paris" <malaka@email.it>
Date: Thu, 18 Mar 2004 08:22:55 +0100
Links: << >>  << T >>  << A >>

"Wing Fong Wong" <wing@tartarusdontspamme.uwa.edu.au> escribió en el mensaje
news:c3b0nk$nqn$1@enyo.uwa.edu.au...
> Peter Alfke <peter@xilinx.com> wrote:
> > In this fast-moving field, any hardcover book would be hopelessly
obsolete.
> I've got one of those hopelessly obsolete books. Published in 1990
> "Digital systems design using progammable logic devices" by Lala, P.K.
> If you compare what was written in that book to what programmable logic
> is like currently you can see just how far we've come.
> > Most FPGAs are of the look-up-table-based reconfigurable flavor,
commonly
>
> > called "SRAM-based" although that is a misnomer.
> > For that type, there are two dominant manufacturers, Altera and Xilinx
(in
> > alphabetical order!). Their websites are full of interesting
information.
> Thats probably the best source of current info. The manufacturers are
always
> proud to declare that they have the fasted and best technology of the time
> and it up to the consumer to evaluate what is really best for them.
Although
> with the amount of infomation out there, one can quite possiblly be over
> loaded by the quantity.
> >
> > Peter Alfke, Xilinx Applications
> > ====================
> >
> -- 
> Wing Wong.
> Webpage: http://wing.ucc.asn.au
>



thanks for your answers,
btw, sorry for the repeated posts, i dont know what's wrong with the news
server, it always says that it couldnt send the post, but it seems it does
:)



Article: 67737
Subject: Re: Dual-stack (Forth) processors
From: no@spam.com (jrh)
Date: Thu, 18 Mar 2004 07:32:57 GMT
Links: << >>  << T >>  << A >>
In article <5s66c.80$fL2.119280@news.uswest.net>, j2thomas@cavtel.net says...

>> It can be fun to use Forth or other interesting ideas in chips, but I
>> don't know of an application where this is a better way to go than an
>> off the shelf DSP or CPU.  

> It might be a way to maintain intellectual property.  If it's hard to 
> reverse-engineer your chip, it will definitely be hard to 
> reverse-engineer your code for it.  And anybody who wants to use it 
> has to get the hardware from you along with the software.

> Of course that makes your products harder to sell, too.  So there's a 
> tradeoff.  But if you have customers and competitors that you plain 
> don't trust, and if you've done work that deserves heavy-duty tarde 
> secrets, it's a possible way to go.

The processor resides in PLD in our motion control system.  It has
proven to be very secure and the I/O can be reconfigured for a wide 
range of applications.  (from data acquisition to plasma height control)   
So far there has been little interest in how it works, the focus is
on what it can do.

Hardware multiply was not implemented in the processor but it
wouldn't be difficult to do if it were necessary. In the world
of parallel logic and state-machines there are different ways
of doing things.  A lot of problems that appear to need a DSP
may be solved using simple logic, and FP is more of a programing
aid than a necessity.

jrh


Article: 67738
Subject: Re: Logiclock TCL flow for Quartus II
From: lyberis@isd.gr (Spyros Lyberis)
Date: 18 Mar 2004 00:08:13 -0800
Links: << >>  << T >>  << A >>
Hi Pete,

Thanks a lot for the hint for the virtual pins. I experimented a 
little bit, and found out the TCL part for them, which declares a 
virtual pin and sets a location on it. 

===========================================================================
== Bottom script modifications for virtual I/Os
===========================================================================

# [...]

execute_module -tool map

set_instance_assignment -to "pin_name" -name virtual_pin on 

# you have to execute again a mapping, so that Quartus recognises
# the virtual pins

execute_module -tool map

set_location_assignment -to "pin_name" LAB_X1_Y1

# ... and you have to close and open the project at this point, 
# otherwise the fitter crashes(!) with a weird error:
#
# > Internal Error: Sub-system: XRU, File: xru_hdb.cpp, Line: 1560
# > m_got_esf_writelock > 0
#
# I tried with export_assignments, but didn't work...

project_close
project_open bottom

# [...]

===========================================================================
== end bottom script modifications
===========================================================================


On another matter, I also managed to make the floating regions in the 
top script become again locked, by patching the top .esf file automatically 
in the script:

===========================================================================
== Top script modifications for regaining the LOCKED regions
===========================================================================

# [...]

logiclock_import -no_pins

project_close

# you have to catch the exit status, because it isn't 0...

catch {puts [exec printf ",s/FLOATING/LOCKED/g\nwq\n" | ed top.esf]} dummy

project_open top

# [...]

===========================================================================
== end top script modifications
===========================================================================


Any further comments, suggestions or info on official Altera 
information on TCL arguments/details will be greatly appreciated...

Cheers,
Spyros


> Hi Spyros,
> 
> I haven't done much Tcl scripting of LogicLock regions yet, so I can't
> help you there. I plan on converting my regions to Tcl-generated in
> the near future so I bet I'll run into the same issues as you have.
> 
> As for bottom-level design using physical pins, you can prevent this
> by enabling the Virtual Pin option for these I/Os in the Assignment
> Editor. You will see the I/Os mapped into LEs in the Floorplan Editor
> after the next compile.
> 
> -- Pete
>

Article: 67739
Subject: Re: UCF or XCF - which one to use ?
From: Stefan Frank <stefrank@gmx.net>
Date: Thu, 18 Mar 2004 09:58:24 +0100
Links: << >>  << T >>  << A >>
On 03/16/2004 02:15 AM, Sudhir Singh wrote:
> Hello,
> Would anyone be able to provide me with some info on which constraints
> file format to use for Xilinx designs - UCF or XCF? Do I need to use
> both or just one will do for a design?

Hello,

it seems to me that XCF is the succsessor of UCF.

See the following link:
<http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/xst/xst0054_8.html>

Bye,
Stefan

Article: 67740
Subject: Re: newbie question about fpga internals
From: johnjakson@yahoo.com (john jakson)
Date: 18 Mar 2004 03:41:14 -0800
Links: << >>  << T >>  << A >>
"paris" <malaka@email.it> wrote in message news:<c39rvu$tlo$1@avanie.enst.fr>...
> hi,
> 
> does anybody knows where can i get techinical information about how a FPGA
> works, it's internal architecture, the internal matrix, etc?
> thanks,
> 
> paris

Perhaps as a side note you could look up the conference procedings
about FPGAs, been a long time since I bought one but there are more
academic papers in those. Not sure if the conf still runs.

google <FPGA conference>

In fact I looked, FPGA 2004 Feb22-24 Monterey CA

I have 1 FPGA book, I think the 4000 series is the new & upcoming one
in that. There is a newer heavier book but for $100 I leave it, Virtex
probably gets a mention there.

Article: 67741
Subject: Re: Spartan III availability
From: johnjakson@yahoo.com (john jakson)
Date: 18 Mar 2004 03:56:30 -0800
Links: << >>  << T >>  << A >>
"Chris Cheung" <chris_cheung66@hotmail.com> wrote in message news:<a176c.241679$Hy3.223342@edtnps89>...
> Try Insight maybe...I just got my Spartan 3 LC board from them...it has a
> XC3S400 in it.
> 
> good luck.
> 

http://www.insight-electronics.com/

Looks like a good deal esp if you go the workshop route, discount is in effect,

Regular $175 or $150 with workshop included.

Their next board in June for $695 is offering a 1500 part.

But Boston or MA is not on the list, I guess nothing here.

Article: 67742
Subject: Printing from Altera SOPC Builder
From: "David Brown" <david@no.westcontrol.spam.com>
Date: Thu, 18 Mar 2004 13:25:49 +0100
Links: << >>  << T >>  << A >>
Is there any way to get a printout from Altera's SOPC Builder, showing the
components around an embedded processor?  It would be nice to have something
better than using a screen-capture program.


--
David

"I love deadlines.  I love the whooshing noise they make as they go past."
Douglas Adams



Article: 67743
Subject: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
From: "Kirstie Wong" <csleunc@essex.ac.uk>
Date: Thu, 18 Mar 2004 05:20:41 -0800
Links: << >>  << T >>  << A >>
Port ( CLOCK : in std_logic; 
           RESET : in std_logic; 
           input1 : in std_logic; 
           inputA : in std_logic; 
           inputB : in std_logic; 
           inputC : in std_logic; 
           inputD : in std_logic; 
           output1 : out std_logic; 
           output2 : out std_logic; 
           P_state : out std_logic_vector(3 downto 0)); 
end fsm; 
architecture Behavioral of fsm is 

--Encoded States in std_logic_vector 
signal C_state, next_state : std_logic_vector(3 downto 0); 
constant s0 : std_logic_vector(3 downto 0) := "0000"; 
constant s1 : std_logic_vector(3 downto 0) := "0001"; 
.. 
.. 
.. 

process 

begin 

next_state_logic: process (C_state,inputA, InputB, iunputC, inputD) 
begin 

case C_state is 

when s0 => 
next_state <= s1; 
output1<= '0'; 
output2 <= '1'; 
if ( inputC = '1' and inoutD = '0') then 
if ( inputA = '0') then 
next_state <= s1; 
else 
next_state <= s4; 
end if; 
elsif ( inputC = '0' and inputD = '1') then 
if ( inputB = '1') then 
next_state <= s7; 
else 
next_state <= s10; 
end if; 
else 
next_state <= s1; 
end if; 

.. 
.. 
rest of the states 
.. 
end case; 
end process; 

process(CLOCK, RESET, input1) 
begin 
if (RESET = '1') then 
next_state <= "0000"; 
elsif CLOCK'event and CLOCK='1' then 
if (input1 = '1') then 
C_state <= next_state; --- i think here is the problem that produce by XST, but how to resolve it? 
else 
C_state <= C_state; 
end if; 
end if; 
end process; 

process(C_state) 
begin 
P_STATE <= C_state; 
end process; 

end Behavioral; 

please help me, experienced experts. thank you even so much 





Article: 67744
Subject: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
From: "Kirstie Wong" <csleunc@essex.ac.uk>
Date: Thu, 18 Mar 2004 05:37:05 -0800
Links: << >>  << T >>  << A >>
the signal of c_state, and next_state, are declared as logic_vecftor (4 bit) 
and the state is also encoded in 4 bit too. 
1st process (C_state, and all other inputs except input 1 which input 1 is used in process 2) 
.. 
case c_state is 
when s0 
.. 
.. 
end case; 

2nd process (clock, reset , input 1) 
if (RESET = '1') then 
next_state <= "0000"; 
elsif CLOCK'EVENT and CLOCK='1' then 
if (input1 = '1') then 
c_state <= next_state; 
-- here is the problem that produce the XST 
else 
c_state <= c_state; 
end if; 
end if; 
end process; 
as long as the fsm is concern need to use the input1 , if input1 is '1', then the c_state <= next_state; 

#### in order to change states, but it complain about my c_state <= next_state; in the 2nd process. 

if i can do that, then 3rd process(c_state) 
begin 

p_state <= c_state; 

-- as the 4bit output as i desired. 




Article: 67745
Subject: Synopsys behavior compiler and Xilinx
From: Rene van Leuken <rene@dimes.tudelft.nl>
Date: Thu, 18 Mar 2004 14:48:16 +0100
Links: << >>  << T >>  << A >>

Subject: Synopsys behavior compiler and Xilinx

I am trying to use the Synopsys behavior compiler (2003.06)
and want to target Xilinx virtex devices.
I am using a simple example, which runs fine when using a standard
Synopsys libray.

When I want to generate code for a Xilinx virtex device, a need a number
of libraries, i.e. designware libs and synthetic libs.
I did find some older libraries on the Xilinx ftp site; i.e.
(a31i_9808_virtex.tar.gz, etc) but those seem to be for older versions
of the Synopsys behavior compiler.

After installing,
when I use the Xilinx libraries in my example I get the following error:

   Loading design 'fir'
Error: Error in building synthetic operators. (HLS-53)
Error: Design has not been timed for Behavioral Compiler (HLS-134)
(complete log below)

What is wrong? How/Where can I get new libraries?

Thanks,

Rene van Leuken.



Article: 67746
Subject: Synthesis algorithm - help needed
From: paulfr@dacafe.com (Paul Franklin)
Date: 18 Mar 2004 05:51:48 -0800
Links: << >>  << T >>  << A >>
Hi!

I would be grateful if anybody can help me with the following problem!

Consider a function 

    F = abcd + a'b'+ klr + r'p.
   ( A'= -A, etc)

Let C1= abcd, C2= a'b', C3= klr, C4= r'p..

We have bins which can implement any function of up to 5 inputs. The
function F needs to be packed into the minimum number of bins.

A partially-filled bin is one which contains a function of LESS than 5
inputs.

I want to bring in the concept of "support". "Support" is defined as
the number of variables that the function explicitly depends on.

I am writing a procedure to implement the concept of packing a large
"system" – much more complex than the above function – into the
minimum number of bins.

The procedure that I have in mind is as follows:

1.	Fill each bin to its maximum capacity where possible.
2.	Then, for partially-filled bins, OPTIMISE as follows 
      - Where there is a choice of which bin to pack a function into,
then we choose the bin with the minimum support of all the bins after
the function has been packed;
      - When there is a contention for bins, then choose the bin whose
support increases by the least amount when the function is put into
it.
So MINIMUM SUPPORT and MINIMUM INCREMENT.
      3. Otherwise choose a new bin.

Write a general procedure to implement the concept.
      
Thank you!

Paul Franklin

Article: 67747
Subject: Re: Synthesis algorithm - help needed
From: alfps@start.no (Alf P. Steinbach)
Date: Thu, 18 Mar 2004 14:03:22 GMT
Links: << >>  << T >>  << A >>
* paulfr@dacafe.com (Paul Franklin) schriebt:
> 
> Write a general procedure to implement the concept.

That sounds suspiciously like a homework assignment.

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 67748
Subject: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig>
From: Nicolas Matringe <matringe.nicolas@numeri-cable.fr>
Date: Thu, 18 Mar 2004 15:05:17 +0100
Links: << >>  << T >>  << A >>
Kirstie Wong a écrit:

> 2nd process (clock, reset , input 1)
> if (RESET = '1') then
> next_state <= "0000"; -- <------------------------ THERE!
> elsif CLOCK'EVENT and CLOCK='1' then
> if (input1 = '1') then
> c_state <= next_state;




-- 
  ____  _  __  ___
|  _  \_)/ _|/ _ \   Adresse de retour invalide: retirez le -
| | | | | (_| |_| |  Invalid return address: remove the -
|_| |_|_|\__|\___/


Article: 67749
Subject: Re: clock rising edge alignment
From: rrr@ieee.org (Rajeev)
Date: 18 Mar 2004 06:43:45 -0800
Links: << >>  << T >>  << A >>
John,

Out of context, my guess would be:

>        slave can run both faster and slower than the master, as long as
> all the rising edges for a specific clock( master as well as slave) aligns
  ^^^ inserted

> with --- rising edges of all equal or higher frequency clocks.
       ^^^ deleted all     ^^^ inserted

eg with 3 clocks
CLKA	000000111111000000111111000000111111	Freq=1
CLKB	111000111000111000111000111000111000	Freq=2
CLKC	101010101010101010101010101010101010	Freq=6
Any two of these could be Master and Slave.

The frequencies all need to be integer (not fraction) multiples, ie in
proportions 1:2:4 or 1:3:6 but not 2:3:6.  They do not need to be powers
of 2.

Do please let us know the context !

Regards,
-rajeev-
---------------
John Black <black@eed.com> wrote in message news:<4057C994.741EF48D@eed.com>...
> Hi,
>     I am having hard time in understanding the following paragraph,
> 
>        slave can run both faster and slower than the master, as long as
> the rising edges for a specific clock( master as well as slave) aligns
> with all rising edges of equal or higher frequency clocks.
> 
>      How to interprete "aligns" here? If the clock frequencies are
> different, how come their rising edges ALL aligning? To me the only case
> is one clock is 2^n times faster than the other, but from the larger
> context of this paragraph, this is not true.



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search