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Need the schematic for the adapter ADP-EPM7128-PL for ALL03 universal programmer!Article: 67926
1. How many peripherials can i attach to a single opb. Is there a limit? how is it defined? 2. If I reach this limit can i instantiate another opb bus? Thanks MattArticle: 67927
John, you can look at the System ACE CF chip as a JTAG command player. On the other side FPGA bitstreams and ELF files are programming information for the FPGA or the CPU, respectively. Now, you can use the Xilinx tools to convert the programming information into the ACE format. As you describe the ACE file is a concatenation of the bitstream(s) and the ELF file(s). When the System ACE CF chip plays the ACE file part of it programs the FPGA and part of it loads software through the PowerPC into any resources accessible from the CPU, i.e. external memory, internal BRAM, CPU registers, external registers, and CPU cache. In other words the JTAG debug interface of the PowerPC is used to program the software into the system. Loading the bitstream and the software into the system thus all happens throught the JTAG interface of the FPGA. Besides that System ACE CF also offers a MPU port that allows direct access to the CF card or MicroDrive in the slot, i.e. the device can be used as a hard disk. To illustrate the whole process here is how embedded Linux is booted on Virtex-II Pro as it ships on the ML300 board: - The board powers up - The System ACE CF chip looks on the first partition of the MicroDrive for the correct ACE file - The ACE file contains the FPGA bitstream and the Linux kernel ELF file. - System ACE CF starts playing this file and at first programs the FPGA and then loads the Linux kernel into main memory. - The same ACE file also includes information to set the PC of the PowerPC to the start address of the Linux kernel in main memory. - The PowerPC starts executing the Linux kernel - The Linux kernel loads the driver for the System ACE CF chip, mounts the third partion on the MicroDrive as root file system on, and continues booting to the login prompt. As you can see System ACE CF is used to - program the FPGA - load the Linux kernel - mount the root file system for Linux - Peter John Black wrote: > Hi, > I am amazed at how SysAce handles the hardware and software: the ACE > file should have 2 parts, FPGA programming bit file and the ELF file > which will be loaded into external memory. I know the trick is JTAG, but > I want to get a closer look what the underneath flow is. SysAce load the > bit file to program the FPGA, and then it ask PowerPC to load the ELF to > the external memory? What exactly happens? > I check out the data sheet of SysAce CF, but it does not mention this > flow. I wonder if somewhere else has this? > > Thanks. >Article: 67928
You might also want to have a look at MontaVista Linux running on our PowerPC based Virtex-II Pro parts. - Peter sree wrote: > Hi, > I am new to FPGA's. I am trying to implement a RISC processor with > some instruction set(arithmetic,logical) on VIRTEX-II FPGA,then I want > to program it using the serial port,for this i want to use c++.is > there any resources or any way i can change GCC compiler to work for > my processor.I also want to try to port linux on this to work as > RTOS,but i believe for this i first need the compiler for my CPU.so, i > need help in finding the resources,tutorials.If there is something you > know please let me know.I thank you in advance. > sreeram koneru > koneru.2@wright.eduArticle: 67929
Hi Matthew, Matthew E Rosenthal wrote: > 1. How many peripherials can i attach to a single opb. Is there a limit? > how is it defined? I can't answer definitively, however my impression is that there are no theoretical limits, only practical ones: 1. available logic resources 2. address map 3. the practical impact of having so many devices on the bus, and being able to keep them busy and doing meaningful work. 4. OPB is implemented as a wired-OR bus, not tristates. So, each new OPB device duplicates address, data, and control signals. These will eventually take their toll on the routability of the design. > 2. If I reach this limit can i instantiate another opb bus? Yes, there is an opb2opb bridge in the EDK, although you'll still meet the same practical limitations eventually. In an idle moment I once created a microblaze uClinux system with 10 serial ports (opb_uartlite), pluis the usual memory controllers, timers, interrupt controllers, ethernet MAC and so on. It works. If you like trying to break things (I know I do! :) it should be easy to write a script that generates pathological systems, with hundreds of instances of some tiny opb core, just increment the base address by the minimum address window size each time. You'll soon learn where the limits are. Regards, JohnArticle: 67930
It looks like ngdbuild is finding the wrong UCF. I think xps copies the UCF from the <proj>/data directory into <proj>/implementation directory. This wrong UCF contains "<INSERT ATTEMPTED PATH HERE>" in the hierarchy path. Tony wrote: >I am constructing a user aurora protocol core based on the PLB SSP1 >reference. It utilizes the MGT on a V2P-7. >I am having difficulty setting the "INST" parameters in the ucf file. >I do not know the path to the MGT parameters. >I've tried many locations... a subset of the attempts is: > >INST plb_gigacore_1/plb_gigacore_1/auroracore_i/aurora_lane_0_i >LOC=GT_X0Y1; >INST system/plb_gigacore_1/auroracore_i/aurora_lane_0_i >ALIGN_COMMA_MSB = ...; >INST "plb_gigacore_1/plb_gigacore_1/auroracore_i/aurora_lane_0_i" >CHAN_BOND_MODE = ...; >INST system/plb_gigacore_1/auroracore_i/aurora_lane_0_i >CHAN_BOND_ONE_SHOT = ...; >INST system/plb_gigacore_1/plb_gigacore_1/auroracore_i/aurora_lane_0_i >CHAN_BOND_SEQ_1_1 = ...; > > >My core is instantiated in the EDK as plb_gigacore_1. >the path to the aurora core in the VHDL files is as follows: > > >plb_core_ssp1_ref.vhd defines USER_LOGIC_I : user_logic >user_logic.vhd defines auroracore_i : auroracore >auroracore.vhd defines lane_0_mgt_i : GT_CUSTOM >and global_logic_i : GLOBAL_LOGIC > >The error I receive is always: >ERROR:NgdBuild:753 - Line 1074 in 'system.ucf': Could not find >instance(s) > '<INSERT ATTEMPTED PATH HERE>/auroracore_i/aurora_lane_0_i' in the >design. > To suppress this error specify the correct instance name or remove >the > constraint. > > > >Article: 67931
Matthew E Rosenthal wrote: >Antti, >Is there a limit to the number of GPIO instances I can create? > > This is limited by the bus implementation itself. There's a check that limits the PLB/OPB bus to 16 slaves. However, you can off-load the bus with a bridge. So opb bus -> opb2opb bridge -> opb bus, you can get 32 slaves: 16 on the first opb bus and 16 on the second opb bus, but this impacts bus/processor performance.Article: 67932
It's only easy if you don't set the security bit :-). vax,3900 wrote: > I am developing a small circuit with XC95288 and I am wondering whether it > is easy to read the content out. I guess since CPLDs are just a bunch of > GALs, and GALs are easy to crack, it might be as easy to crack an XC95288. > Am I right? Thank you. > > vax, 3900Article: 67933
I hear the V2Pro was known at various locations internally as the V3. To avoid the confusion they just skipped to V4. I don't understand the clock issue. Mine lookes like this all the way around: /^^\__/^^\__/^^\__/^^\........ And I assume they will add an Over-Score key about the time I get my clock looking smooth on top. "Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:c3n9pa$dqu$1$8302bc10@news.demon.co.uk... > The current XCell talks about the Virtex-4. Presumably > there will be no Virtex-3. And, sadly, no Virtex-IV. > We rather looked forward to the Virtex-MCMLXXIX - is it > an FPGA or is it the Pope? > > Scarcely less off-topic, why do decent clocks always show > the 4 o'clock as IIII? > >Article: 67934
I probably should have been more explicit... That <Insert attempted path here> is what i added in to indicate a wildcard that NONE of my attempted paths worked... I get a series of those exact messages containing the paths i tried. I.e. ERROR:NgdBuild:753 - Line 1074 in 'system.ucf': Could not find instance(s) 'plb_gigacore_1/plb_gigacore_1/auroracore_i/aurora_lane_0_i' in the design. To suppress this error specify the correct instance name or remove the constraint. ERROR:NgdBuild:753 - Line 1075 in 'system.ucf': Could not find instance(s) 'system/plb_gigacore_1/auroracore_i/aurora_lane_0_ii' in the design. To suppress this error specify the correct instance name or remove the constraint. ERROR:NgdBuild:753 - Line 1076 in 'system.ucf': Could not find instance(s) 'plb_gigacore_1/plb_gigacore_1/auroracore_i/aurora_lane_0_i' in the design. To suppress this error specify the correct instance name or remove the constraint. .... Thanks, Tony On Mon, 22 Mar 2004 18:49:05 -0800, Paulo Dutra <Paulo.Dutra@xilinx.com> wrote: >It looks like ngdbuild is finding the wrong UCF. I think xps copies the >UCF from the ><proj>/data directory into <proj>/implementation directory. This wrong UCF >contains "<INSERT ATTEMPTED PATH HERE>" in the hierarchy path. > >Tony wrote: > >>I am constructing a user aurora protocol core based on the PLB SSP1 >>reference. It utilizes the MGT on a V2P-7. >>I am having difficulty setting the "INST" parameters in the ucf file. >>I do not know the path to the MGT parameters. >>I've tried many locations... a subset of the attempts is: >> >>INST plb_gigacore_1/plb_gigacore_1/auroracore_i/aurora_lane_0_i >>LOC=GT_X0Y1; >>INST system/plb_gigacore_1/auroracore_i/aurora_lane_0_i >>ALIGN_COMMA_MSB = ...; >>INST "plb_gigacore_1/plb_gigacore_1/auroracore_i/aurora_lane_0_i" >>CHAN_BOND_MODE = ...; >>INST system/plb_gigacore_1/auroracore_i/aurora_lane_0_i >>CHAN_BOND_ONE_SHOT = ...; >>INST system/plb_gigacore_1/plb_gigacore_1/auroracore_i/aurora_lane_0_i >>CHAN_BOND_SEQ_1_1 = ...; >> >> >>My core is instantiated in the EDK as plb_gigacore_1. >>the path to the aurora core in the VHDL files is as follows: >> >> >>plb_core_ssp1_ref.vhd defines USER_LOGIC_I : user_logic >>user_logic.vhd defines auroracore_i : auroracore >>auroracore.vhd defines lane_0_mgt_i : GT_CUSTOM >>and global_logic_i : GLOBAL_LOGIC >> >>The error I receive is always: >>ERROR:NgdBuild:753 - Line 1074 in 'system.ucf': Could not find >>instance(s) >> '<INSERT ATTEMPTED PATH HERE>/auroracore_i/aurora_lane_0_i' in the >>design. >> To suppress this error specify the correct instance name or remove >>the >> constraint. >> >> >> >>Article: 67935
ALuPin wrote: > I want to synchronize 90MHz data which come from an external > 90MHz clock domain (GMII transceiver device) > to my internal FPGA 90MHz clock. > So I have two clocks with the same frequency > but they are asynchronous to each other. > > What possibilities can be used for synchronization? Consider running the fpga on the GMII clk. -- Mike TreselerArticle: 67936
Tommy Thorn <TommyAtNumba-Tu.Com--not@yahoo.com> wrote in message news:<4054D4B5.5040504@yahoo.com>... > Vaughn Betz wrote: > > You can directly instantiate any legal logic cell from within verilog > > code by instantiating "WYSIWYG" logic cells. This lets you do any > > amount of technology mapping you like, and mix it with HDL. > > > > The Verilog syntax that is used for instantiating a logic cell is > > described in QUIP (Quartus University Interface Program), in the > > document "stratix_wysuser_doc.pdf". You can instantiate logic cells > > from inside VHDL code by writing a verilog file with the logic cells > > you want, then instantiating that entity in your VHDL code. > > Thanks, that's useful and gets access to _everything_ but it's also a > rather radical. > > Is there a less direct way to achieve parts of this, eg. will Quartus > use the cascade chain for conjunctions when it could? Quartus will use the and-cascade chain in architectures that have it when it can, automatically. So yes, this stuff is used automatically. As for controlling synthesis, direct instantiation of WYSIWYGs (Lcells etc.) is the most powerful technique, since it lets you do anything. To use it, you'd normally only code up certain low-level primitives (e.g. ALUs) where you found you could beat the synthesis tool using WYSIWYGs. Then you'd use this low-level library as appropriate. If you don't want to do that, there are alternative techniques that are less radical. From least radical to most radical, I'd say these are: 1. Write in a "vanilla" HDL style and let the synthesis tool do all the work. Generally more straightforward code will result in better synthesis, since synthesis will recognize what you are doing more easily. For example, code muxes as binary muxes using a case or select statement to ensure the compiler recognizes them as muxes and gives you the best implementation. 2. Replace parts of your HDL with calls to Altera LPMs and megafunctions. Use the Megawizard plug-in manager in Quartus to create the megafunctions, then instantiate them in your code. Note that synthesis tools will automatically infer megafunctions where they think appropriate, so when you use technique #1 above you will still likely be making use of megafunctions & lpms. 3. Write portions of your HDL in a very structural manner, and use lcell, carry and (for APEX and the 10K, cascade) buffers in your HDL to force a certain mapping to logic cells. The Quartus on-line help will show you the syntax -- basically you pass a signal through an lcell buffer primitive when you want to ensure that signal will form the output of a logic cell. 4. Directly instantiate logic cells from your HDL using the techique described in QUIP. As for the question of why you never see cascade chains longer than 2, it is probably because the "Cascade Chain Length" is set to 2 (the default) in "Assignments->Settings->Analysis & Synthesis Settings->More Settings". Change it to a bigger number to enable longer cascade chains. Note that longer cascade chains will constrain the fitter more, so you can sometimes give up the speed you think you'll gain to reduced fitter flexibility. All the suggestions above definitely have the potential to hurt performance instead of helping -- it is definitely possible for a human to beat the synthesis tools, but it's not trivial. So it's best to always compare the results of your carefully optimized design against flow #1 -- fully automated implementation of your HDL -- to make sure you've really optimized the design, and not de-optimized it. Regards, Vaughn AlteraArticle: 67937
Hi folks, typically how many times can I burn/download an FPGA before it becomes unreliable. I read Xilinx FPGA datasheets and couldn't find the answer. I am asking because I am wondering if someone is going to make a commercial FPGA product that need to be frequently turned on and off, this can be an issue. Every time the device is turned on, the FPGA chip need to be redownloaded from an EPROM. If the device is turned on and off 3 or 4 times a day and the device is used every day, and if the device can only be reprogrammed 1000 times, then in less than a year the device can not be used anymore. Thanks! HendraArticle: 67938
Hi Hendra, Hendra Gunawan wrote: > typically how many times can I burn/download an FPGA before it becomes > unreliable. I read Xilinx FPGA datasheets and couldn't find the answer. > I am asking because I am wondering if someone is going to make a commercial > FPGA product that need to be frequently turned on and off, this can be an > issue. Every time the device is turned on, the FPGA chip need to be > redownloaded from an EPROM. If the device is turned on and off 3 or 4 times > a day and the device is used every day, and if the device can only be > reprogrammed 1000 times, then in less than a year the device can not be used > anymore. The reason you cannot find is number, is because that number is effectively infinite. Xilinx FPGA configuration cells are SRAM, and have no cycle limit that I am aware of. The configuration proms do have a limit, typically on the order of 10,000 erase/write cycles. I'm sure someone from Xilinx will be able to give you the definitive answer! Regards, JohnArticle: 67939
"bob" <bob@bob.com> wrote in message news:405F6DAD.2B7CDE60@bob.com... > We designed a board using the JTAG and passive serial download > procedures in AN250 a while back. In Sept of 2003 > Altera released their "Configuration Handbook" in which now apparently > the JTAG lines have to have pull ups and > downs on them (though the down is incorrectly stated as 10K should be 1K > apparently). It would seem, if i read > between the lines, that the JTAG pullup on the TCK pin within the device > can cause some sort of fault The fix for this is to pull the TCK pin > low with 1K. > > If this is so has anyone seen an errata they can point me to? I don't know about the Cyclone, but the FLEX10K which I used some years ago required 1k pullups on TDI and TMS, and a 1k pulldown on TCK. LeonArticle: 67940
"Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message news:Pine.LNX.4.58-035.0403221554300.25260@unix45.andrew.cmu.edu... > Hi, > I want to create a large number of PLB or OPB GPIO nets to connect to many > different parts of my own custom logic(on the order of 1000 nets). > > Does one type of bus do a better job at not using up routing resources? > Is one type of bus simplier to use? > Is there any limit on the number of GPIO pins I can use? if you really want to use GPIO then the PLB vs OPB doesnt really make a difference here single GPIO instane can have 128 outputs and 64 inputs if routed into ISE toplevel you can use _O and _T as separate output ports. but it would really be better to make your own peripheral its not complicated AnttiArticle: 67941
And avoid using Windows(TM). Current FPGAs are not yet equipped with Ctrl, Alt and Del keys.Article: 67942
"Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:c3n9pa$dqu$1$8302bc10@news.demon.co.uk... > The current XCell talks about the Virtex-4. Presumably > there will be no Virtex-3. And, sadly, no Virtex-IV. > We rather looked forward to the Virtex-MCMLXXIX - is it > an FPGA or is it the Pope? > > Scarcely less off-topic, why do decent clocks always show > the 4 o'clock as IIII? > I'm sure someone will correct me if this is just myth (usenet is so reliable for that), but AFAIK, it's because IIII is Roman Numerals for 4 - that's what the Romans used. The abbreviated form IV was intoduced later, for consistency with IX. The IX form was only used in circumstances where space was at a premium (such as on clocks :-), while the far more logical VIIII form was used otherwise.Article: 67943
Hi again Przemek, > Thats odd that you are not gettings an RCF created in your > atom_netlists directory. When you back annotated, did you select > "Routing" as part of the back annotation? I didn't specify that you > needed to, sorry for the confusion. To get the placement and routing > information into the ESF and RCF you must back annotate first. I've tried some variants in the script, but I never got a .rcf file. The general idea of the script is: =========================================================== # [define rgn_bottom region and run the fitter] logiclock_back_annotate -region rgn_bottom -routing logiclock_export -file_name test.txt -routing export_assignments qexec "quartus_cdb bottom --vqm=./bottom.vqm" =========================================================== Both -routing options seem to do nothing. It also seems that the logiclock_export command does nothing interesting, because it just creates a very similar file to the .esf of the project (same size, similar contents (possibly the same, but reordered)). I've also tried without the logiclock_export command, and I'm getting the same results. > 1) Unfortunately, the default is to make the regions floating > automatically. This is to make sure that the design fits in > situations where there are multiple back annotated instances of the > same entity. > > If you are trying to make a MAKEFILE type script, here is a > suggestion. You can use the -update option in Logiclock_import. What > this does is it tries to preserve the placement of the region (and the > parent region hierarchy) during import. > > So imagine that you imported a lower level entity, and you locked it > down, perhaps you even moved it somewhere else on the chip. Now you > want to modify the internal placement of that entity at a lower level > and re-import it. The -update option, basically keeps the top level > (already imported) region as it is, and just removes all of its > contents and updates it with the new contents from the lower level. > If the region was locked, then it will remain locked. Note: It is > important to leave the region name the same. Thanks for the explanation. I didn't try the -update option, but I managed to re-lock the regions using the set_global_assignment command, thanks to a tip from David. > 2) Great. > > 3) Try backannotating the routing first before you try to export. > That should work. > > 4) Again, here is what I see: > > tcl> set_logiclock -h > --------------------------------------------------------------------------- > > [...] > --------------------------------------------------------------------------- > > Perhaps there is something wrong with your installation of Quartus. > I'm not sure. > > I will check to see if there is a specific TCL guide that I can point > you to. That would be a blessing! Thanks again, SpyrosArticle: 67944
Hi David, > Looks like a bug :-( > > Your best bet may be to upgrade to V4.0. > > [...] > > I was trying to reproduce it on the PC (and I am sure Przemek too), so > it seems like the Linux installation may be missing some files. > > Again, if you can do it, try V4.0 Ok, I'm already trying to upgrade to V4.0. We purchased an Altera licence about two months ago. Do you know if we are going to receive the V4.0 automatically by Altera, or we have to order it specifcally? Currently, we're trying to find that out through our local vendor in Greece... > Yes, you can use set_global_assignment. You can use "-entity > <esf_file_name>" and "-section_id <logiclock_region_name>". At least > -section_id may be hidden in V3.0, but it will work fine. Yeah, that worked just fine! Thanks, SpyrosArticle: 67945
How embarracing! after reporting that XCV2000E survived 3.3V core voltage I now have a completly dead XC2S200E-PQ208 !!! The power supply is TPS72618 and it was 1.8V before the FPGA died! The software guy reported this morning random failures that the Microblaze did not start, then the board was left on the table (configured, microblaze working inside), after breakfest the FPGA and power supplies were hot. 1.8V supply when measured at power regulator is 0.57V at FPGA pins 0.3 .. 0.4V resistance when measured VCCINT to GND is <0.1 ohms so the FPGA seems to have real heavy complete short circuit on VCCINT inside. This is the second proto, first one has been up and running for a week, and its working just fine. Any ideas what could cause that kind of fatal failure? tnx, Antti LukatsArticle: 67946
Antti Lukats wrote: > How embarracing! > after reporting that XCV2000E survived 3.3V core voltage I now have a > completly dead XC2S200E-PQ208 !!! > > The power supply is TPS72618 and it was 1.8V before the FPGA died! > > The software guy reported this morning random failures that the > Microblaze did not start, then the board was left on the table > (configured, microblaze working inside), after breakfest the FPGA and > power supplies were hot. > > 1.8V supply when measured at power regulator is 0.57V at FPGA pins 0.3 > .. 0.4V resistance when measured VCCINT to GND is <0.1 ohms > > so the FPGA seems to have real heavy complete short circuit on VCCINT > inside. > > This is the second proto, first one has been up and running for a > week, and its working just fine. > > Any ideas what could cause that kind of fatal failure? Err... Device stress ? .... -jgArticle: 67947
Hi, Could anyone tell me roughly how many gates (i..e NAND2 equivalent) it takes to implement a slice in a Virtex 2? Cheers, JonBArticle: 67948
There is no limit to the reconfiguration on FPGAs. The configuration is held in
registers similar to the flip-flops in the design (although the registers are
designed to be slower and therefore more robust against unintended upsets).
They won't wear out. The only life limited item would be the EPROM you load the
FPGA from.
Hendra Gunawan wrote:
> Hi folks,
> typically how many times can I burn/download an FPGA before it becomes
> unreliable. I read Xilinx FPGA datasheets and couldn't find the answer.
> I am asking because I am wondering if someone is going to make a commercial
> FPGA product that need to be frequently turned on and off, this can be an
> issue. Every time the device is turned on, the FPGA chip need to be
> redownloaded from an EPROM. If the device is turned on and off 3 or 4 times
> a day and the device is used every day, and if the device can only be
> reprogrammed 1000 times, then in less than a year the device can not be used
> anymore.
>
> Thanks!
>
> Hendra
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 67949Jim Granville <no.spam@designtools.co.nz> wrote in message news:<XEU7c.3055$u%1.437958@news02.tsnz.net>... > Antti Lukats wrote: > > > How embarracing! > > after reporting that XCV2000E survived 3.3V core voltage I now have a > > completly dead XC2S200E-PQ208 !!! > > Any ideas what could cause that kind of fatal failure? > > Err... Device stress ? .... > -jg engineering stress I guess, there is cheap 5V to 3.3V level converter to accept 5V level external RS232 signal from MAX232, and... well if you use 5V6 TVS instead of 3V3 TVS then you get full 5V on FPGA pins. I still wonder it did damage the FPGA, there is a 2K7 series resistor but I guess the 5V on iopad overstressed the core somehow (even there was no current involved into iopad) that overstressed engineer has now to replace that PQ208 (after hand soldering 5 boards with 300 SMD per board) Antti
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