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Messages from 68050

Article: 68050
Subject: Clock divider preserving duty-cycle ?
From: cdufourfour@yahoo.ca (john)
Date: 25 Mar 2004 07:37:43 -0800
Links: << >>  << T >>  << A >>
Hi,

I'm looking for a way to divide a clock frequency with keeping the
duty-cycle of the input clock . Unfortunatly, the input duty-cycle is
unknown and I had to preserve it !

For example: 
input : 500MHz , x% duty-cycle
output : 50 MHz , x% duty-cycle

Article: 68051
Subject: Re: Bus width between registers in IIR
From: Ray Andraka <ray@andraka.com>
Date: Thu, 25 Mar 2004 10:49:40 -0500
Links: << >>  << T >>  << A >>
If the overflows are internal only, ie. if the added MSBs are not propagated all
the way to the output, then you don't need to add them provided your number
system is modular (2's complement is).   The arithmetic operations in the filter
are such that if you change one bit of an operand, only that bit and bits to the
left of it are affected.  Therefore, overflow bits internally do not affect
output bits with less significance.

Anatoli Sergienko wrote:

> > The only thing I would know is how many bits wide should I take for the
> > intermediate results when I use an IIR filter. The input data is 24 bit.
> > Should I use more than 24 bits to calculate the partial products, or not ?
>
> You need to add some MSBs.
> The number of them depends on the filter sharpness.
> If the filter is rather selectable you have to add even 8-12 MSBs.
> Therefore the best solution is to simulate the filter with real signals,
> investigate the overflows,
> and select the minimum bit number which does not make the overflow.
>
> A.Ser.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 68052
Subject: Re: How many times can I burn an FPGA?
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 25 Mar 2004 08:15:23 -0800
Links: << >>  << T >>  << A >>
Martin,

If we can't have fun, why bother.

Keep smiling.

Austin

Article: 68053
Subject: Re: Virtex-Fore
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 25 Mar 2004 08:16:59 -0800
Links: << >>  << T >>  << A >>
Rick,

Darn!  You get the prize!  You must have some marketing blood in those 
steely engineering veins.

Austin


Article: 68054
Subject: CPLD: assign pins first, or design content first?
From: "vax,3900" <vax3900@yahoo.com>
Date: Thu, 25 Mar 2004 11:28:21 -0500
Links: << >>  << T >>  << A >>
I am using a CPLD(XC95144) in my board and since it is my first time to play
CPLD, I have the question when to assign pins. The CPLD will have a 22 bit
parallelly loadable counter and two state machines. I need to know when is
the right time to assign pins. Do I assign pins after the content is
designed and tested, or before? How flexible are CPLDs about assigning
pins? Thank you.

vax, 3900

Article: 68055
Subject: Re: Clock divider preserving duty-cycle ?
From: "John_H" <johnhandwork@mail.com>
Date: Thu, 25 Mar 2004 16:38:50 GMT
Links: << >>  << T >>  << A >>
In my opinion your task is a superbly difficult one not achievable with
simple digital logic.  The only digital possibility I could imagine would
use high speed serial channels to average out what the duty cycle is for
your extremely high speed signal.

If your frequency and duty cycle are relatively fixed, an analog scheme
could be used to measure the duty cycle of both input and output clocks,
adjusting the falling edge of your output clock until the two duty cycles
match.

This task is not for the feint of heart !


"john" <cdufourfour@yahoo.ca> wrote in message
news:79cc958c.0403250737.5703e059@posting.google.com...
> Hi,
>
> I'm looking for a way to divide a clock frequency with keeping the
> duty-cycle of the input clock . Unfortunatly, the input duty-cycle is
> unknown and I had to preserve it !
>
> For example:
> input : 500MHz , x% duty-cycle
> output : 50 MHz , x% duty-cycle



Article: 68056
Subject: Re: Quartus with AMD64 processors?
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 25 Mar 2004 11:49:43 -0500
Links: << >>  << T >>  << A >>
Petter Gustad wrote:
> 
> "Nial Stewart" <nial@nialstewartdevelopments.co.uk> writes:
> 
> > > > with SSE instructions enabled.  This means that you need a Pentium III/4
> > > > or Athlon XP/MP/64 to run the code.
> >
> > ... it'll work on an XP, not on an old Althlon.
> 
> It's only under Linux, not Windows. I'm probably the only one in the
> world using Quartus II under Linux on an AMD Athlon :-)

No, not the only one, just the only one who admits it... ;) 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 68057
Subject: Re: Clock divider preserving duty-cycle ?
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 25 Mar 2004 09:11:40 -0800
Links: << >>  << T >>  << A >>
If your first frequency were lower, I would suggest measuring the average dc
value (after a low-pass filter), compare it to the average dc of the divided
signal, and then adjust the lower frequency's duty cycle by digital means,
e.g. the Virtex-II DCM Phase control.
But at 500 MHz, your period is only 2 ns, and rise and fall times will cause
big errors.
Peter Alfke, Xilinx Applications
==========================
> From: cdufourfour@yahoo.ca (john)
> Organization: http://groups.google.com
> Newsgroups: comp.arch.fpga
> Date: 25 Mar 2004 07:37:43 -0800
> Subject: Clock divider preserving duty-cycle ?
> 
> Hi,
> 
> I'm looking for a way to divide a clock frequency with keeping the
> duty-cycle of the input clock . Unfortunatly, the input duty-cycle is
> unknown and I had to preserve it !
> 
> For example: 
> input : 500MHz , x% duty-cycle
> output : 50 MHz , x% duty-cycle


Article: 68058
Subject: Re: How many times can I burn an FPGA?
From: mikeandmax@aol.com (Mikeandmax)
Date: 25 Mar 2004 17:20:54 GMT
Links: << >>  << T >>  << A >>
Austin - and other wrote >

>
>If we can't have fun, why bother.
>
>Keep smiling.
>
 the thread reminded me of a customer in the early days of multiple voltage
systems, he managed to latch up on of our devices, and got a nasty blister on
the tip of his "digital" probe.  Part of our resolution to the problem was to
provide a set of oven mitts, for 'hot socketed' pcbs :)

Mike T
LSC



Article: 68059
Subject: Re: study verilog or vhdl?
From: Jim Lewis <Jim@SynthWorks.com>
Date: Thu, 25 Mar 2004 09:58:11 -0800
Links: << >>  << T >>  << A >>

mdini@dinigroup.com wrote:
> 1. I don't know ANYBODY that is fluent in both VHDL and Verilog that
> prefers VHDL.  The only advantage of VHDL is the signed arithmetic. 
> That doesn't make up for the useless type-checking and lack of
> ifdef's. 

Useless type-checking?  Then why are Verilog experts recommending
that people use a lint tool to enforce type-checking on Verilog:

     At DVCon in 2003, Tensilica presented a paper that indicates
     that they impose these same rules on their Verilog coders by
     using a lint tool.  They found that in 65 to 70% of the time,
     a violation of these rules was an actual bug.

     At DesignCon 2004, Lionel Bening of HP and Adam Krolnik of LSI
     Logic also presented a paper that also recommends similar rules.


If initially you don't want to spend the extra money on a
lint tool, I would pick VHDL.  It already has a number of
lint features built into the compiler.


> 2. Remember the infamous Verilog vs. VHDL competition that Cooley did
> a few years back?  See this link:
> <http://www.deepchip.com/items/snug99-42.html>
> In this contest, not a single VHDL contestant was able to finish the
> problem.  Not one.

I attended that conference.  I went to that SNUG for
the value I got out of the papers.  I didn't have any
interest in any silly V vs. V competition.
On the other hand, the Verilog experts had an Axe to
grind because the marketing gurus of the time were
predicting that Verilog would die.


> 3. I hope the competition is using VHDL. 
Well, I hope they are using Verilog and are so confident
and passionate about Verilog and their ability that
they don't think they need a lint tool.

The good news for VHDL is that the verbosity issues that
some complain about can be fixed in future language
revisions (such as the on going VHDL-200X effort).

The bad news for Verilog is that even with SystemVerilog
the scheduling is such that you need to learn ad hoc
coding rules just to produce code that runs the same on
all simulators.

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


Article: 68060
Subject: Re: How many times can I burn an FPGA?
From: Dwayne Surdu-Miller <miller@SEDsystems.nospam.ca>
Date: Thu, 25 Mar 2004 12:17:25 -0600
Links: << >>  << T >>  << A >>
Recently, I've been burning CD-ROMs instead of PROMs.

The smell is far more putrid!

But destroying anything with AOL written on it is far more satisfying.

:-)


Article: 68061
Subject: Re: opb arbitrer
From: Paulo Dutra <paulo.dutra@xilinx.com>
Date: Thu, 25 Mar 2004 10:33:23 -0800
Links: << >>  << T >>  << A >>
Whenever, there are multiple masters/slaves on the opb_v20_v1_10_b
(parameter C_NUM_MASTERS/C_NUM_SLAVES are calculated by platgen),
the arbiter is automaticaly included into the bus logic. You can
not change C_NUM_MASTERS/C_NUM_SLAVES values through the MHS.

Debugging embedded systems are a complicated process. You should
debugg your design through hw simulation. On hw, you can use
xmd to talk to microblaze. Have you tried removing the microblaze
that go to the leds and isolating the system that talks to the
rs232? How did you come to conclusion that the arbiter is the issue?

Jonathan Debrouwere wrote:
> Hello,
> 
> Here is the context:
> I work on a Memec xc2vp7-fg456 and I try to make a reconfigurable
> multiprocessor architecture on it.
> 
> For now I'm trying to put two MicroBlazes on the same opb bus
> [On-Chip Peripheral Bus v2.0 with OPB Arbiter (v1.10b)].
> 
> One of the MicroBlaze is connected to 4 leds and the other one is connected
> to the RS232. When I program the fpga, only the leds are working. So I think
> that the arbitrer is the problem.
> I tryed to configure some parameters on the *.mhs:
> [
> PARAMETER C_NUM_MASTERS = 2
>  PARAMETER C_NUM_SLAVES = 16
> ]
> but it's not working.
> 
> Does anybody knows where I could find some answear? thanks a lot.
> 
> 


-- 
/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
\ \ `  Xilinx                              hotline@xilinx.com
/ /    2100 Logic Drive                    http://www.xilinx.com
\_\/.\ San Jose, California 95124-3450 USA


Article: 68062
Subject: Re: CPLD: assign pins first, or design content first?
From: thangkho <>
Date: Thu, 25 Mar 2004 10:46:34 -0800
Links: << >>  << T >>  << A >>
There're several things you need to consider: 
1) How complexity/how fast your cpld design is? 
2) How difficult your pcb layout will be? 

If your pcb layout is simple and easy to meet timing requirement, then I would 
like to let SW assign pins for you. Otherwise you need to be careful assign 
CPLDs pins and make sure the design still fit in target device and pass all 
timming constraint. This task sometime very difficult (sometime impossible) when 
your design is closed to edge of limitation for a particular target...(well, you 
can always jump to a bigger/faster device if you can afford...)

regard, 

Article: 68063
Subject: Re: CPLD: assign pins first, or design content first?
From: "vax,3900" <vax3900@yahoo.com>
Date: Thu, 25 Mar 2004 14:31:11 -0500
Links: << >>  << T >>  << A >>
thangkho <> wrote:

> There're several things you need to consider: <BR>
> 1) How complexity/how fast your cpld design is? <BR>
> 2) How difficult your pcb layout   <BR>
> will be? <BR>
> If your pcb layout is simple and easy to meet timing requirement, then I
> would like to let SW assign pins for you.  Otherwise you need to be
> careful assign CPLDs pins and make sure the design still fit in target
> device and pass all timming constraint. This task sometime very difficult
> (sometime impossible) when your design is closed to edge of limitation for
> a particular target...(well, you can always jump to a bigger/faster device
> if you can afford...) <p>regard,

Thank you. The timing is not important. It runs with 20MHz clock. Maybe
there is a PCB layout problem because It will be a two layer board. I will
try to let software to assign pins for me, then make some small adjustments
to make PCB easier.

regard,
vax, 3900

Article: 68064
Subject: Re: PWM, PLD programming ,(up/down ramp frequency)
From: stewart1r1@hotmail.com (Stewart Smith)
Date: 25 Mar 2004 11:57:21 -0800
Links: << >>  << T >>  << A >>
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<Vfx4c.1045$u%1.166062@news02.tsnz.net>...
> Stewart Smith wrote:
> <snip>
> >>Look into Rate Multipliers : These have  Fo = N/Base output, so
> >>a 4 bit binary one can start at 1/16 fi, and step thru 2/16,3/16
> >>up to 16/16 Fi, in linear frequency steps
> >>
> >>Rate Multiplier info is not easy to find, so here is one ref :
> >>http://focus.ti.com/docs/prod/folders/print/sn7497.html
> >>-jg
> > 
> > Thank you for taking time to respond
> > Have looked into the link you suggested and, no problem for me to use
> > this type of device, in fact they have them in stock at uni which is
> > handy. This definitely seems a step in the right direction.
> 
>   I was meaning that you use the device as a Logic example/Template,
> and code what you need in the PLDs...
> -jg

Hi 
I know its been some time since I last posted, had some very
intensive(well intensive for me)report writing to do.
Back to the matter at hand, I have managed to create the
up/hold-down/hold counter ( I achieved this by merely telling the last
up or down state to repeat itself until the direction input changes
from 1-0 or 0-1, seems to work ok)

I've tried to simulate the two PLD's together using "Cadence" and had
some success, I am achieving a variable frequency output on 1 single
pin,

This is done by taking the four outputs from the frequency divider in
PLD 1, feeding them as inputs to PLD 2 where there is another
counter(4-bit) and when the input matches a count this is output to
Pin 18.
If you can follow my explanation the last line of code reads
"Q4.D = (Q0&div16)#(Q1&div8)#(Q2&div4)#(Q3&div2);"
 I have also fed back the output from div16 which is my lowest
frequency back as the clock source for PLD 1 (which I think is what
was suggested)
This now utilises five bits of PLD 2 which leaves just the three for
the "phase engine"

What I think is needed now is to feed this back as an input so to use
this as trigger for the ramp.

Having a little trouble trying to incorporate the two programs into
PLD 2, do I need to declare or define that prog1 (counter) and prog2
should run concurrently or something like.
when I compiled the .doc file didn't show any equations for Q5..7 , so
this is as far as I've got I feel not too far away but far enough,
still got the control side to finalise as well as this incorporation
stuff then no doubt a mountain of bugs just for fun.
I know my explanations may be a bit vague and for this I ask you to
bear with me, if anyone would like to view the, what I call programs
(not sure anyone else would) please feel free to email me.
Thanks 
Stewart

Article: 68065
Subject: Re: Clock divider preserving duty-cycle ?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 25 Mar 2004 20:01:37 GMT
Links: << >>  << T >>  << A >>

(someone wrote)

 >>I'm looking for a way to divide a clock frequency with keeping the
 >>duty-cycle of the input clock . Unfortunatly, the input duty-cycle is
 >>unknown and I had to preserve it !

 >>For example:
 >>input : 500MHz , x% duty-cycle
 >>output : 50 MHz , x% duty-cycle

Peter Alfke wrote:
> If your first frequency were lower, I would suggest measuring the average dc
> value (after a low-pass filter), compare it to the average dc of the divided
> signal, and then adjust the lower frequency's duty cycle by digital means,
> e.g. the Virtex-II DCM Phase control.
> But at 500 MHz, your period is only 2 ns, and rise and fall times will cause
> big errors.

Well, it does say example, so consider the possibilities
at lower frequencies.   As for analog methods, PLLs
are commonly used for frequency converters, so one could
start with that.

I am trying to imaging a duty-cycle locked loop, though I
haven't quite done it yet.   If you low pass filter both
the input and output, and then use the difference as
a feedback term to a voltage controlled duty cycle oscillator,
I could at least imagine it working.

I would think you should normalize the voltage before the
filter, such that it isn't amplitude sensitive.

How hard is it to make a 500MHz PLL with discrete components?

-- glen


Article: 68066
Subject: Re: Clock divider preserving duty-cycle ?
From: "paris" <malaka@email.it>
Date: Thu, 25 Mar 2004 21:35:10 +0100
Links: << >>  << T >>  << A >>
then use analog :)
like in heterodyne reveivers, just choose a Local Oscilator Frequency 50MHz
less than your input frequency, say 450MHz, then multiply it with your input
frequency. The multiplier is analog, a non linear device, i made one with a
small 16 DIP CI a long LONG time ago and it was very cheap (though i dont
remember if it went so high in frequency, but TV circuits have them in the
receiver and TV uses frequencies about 400MHz or more)
at the output of the multiplier you'll get two signals (plus de ones you
injected, so a total of four), one at 50MHz (500-450) and another at 950MHz
(500+450), you can easily filter the 50MHz for your purposes.

something called a heterodyne receiver a quick search on google gave me:

http://www.ee.byu.edu/ee/class/ee444/ComBook/ComBook/node77.html

that'll give you some math to prove what i said (substracting -or negative-
frequencies seem a bit wild when you first use them, but the math is the
math :)

there are some other issues, like if you're planning to enter a digital
signal (which is very likely as you posted in an FPGA group :), then the
filter at the output should have enough bandwidth to not cut the harmonics
(the fourrier development of the input signal) of the input signal so that
you recover it more or less "digital" :) the more harmonics you cut, the
more "sinus" it will be. But again, you have till 450MHz (cause that's your
LO frequency and it'll go out the multiplier) to for the filter to cut down.
450MHz is 9times 50MHz, so that's it's 9th harmonic, for most purposes
conserving till the 9th harmonic is good enough. If it isnt, then you could
choose an OL frequency of 550MHz, it'll give you the same results, just
giving you one more harmonic, till 500MHz.

feel free to comment or to point out any errors, as it's has been a very
long time since i used this things.

Sebastian

ps: also i speak french not english so im sorry if i didnt make myself clear
or made mistakes

"John_H" <johnhandwork@mail.com> escribió en el mensaje
news:uWD8c.18$V4.150@news-west.eli.net...
> In my opinion your task is a superbly difficult one not achievable with
> simple digital logic.  The only digital possibility I could imagine would
> use high speed serial channels to average out what the duty cycle is for
> your extremely high speed signal.
>
> If your frequency and duty cycle are relatively fixed, an analog scheme
> could be used to measure the duty cycle of both input and output clocks,
> adjusting the falling edge of your output clock until the two duty cycles
> match.
>
> This task is not for the feint of heart !
>
>
> "john" <cdufourfour@yahoo.ca> wrote in message
> news:79cc958c.0403250737.5703e059@posting.google.com...
> > Hi,
> >
> > I'm looking for a way to divide a clock frequency with keeping the
> > duty-cycle of the input clock . Unfortunatly, the input duty-cycle is
> > unknown and I had to preserve it !
> >
> > For example:
> > input : 500MHz , x% duty-cycle
> > output : 50 MHz , x% duty-cycle
>
>



Article: 68067
Subject: Re: Altera NIOS SOPC Builder---- Can I edit a text file
From: petersommerfeld@hotmail.com (Peter Sommerfeld)
Date: 25 Mar 2004 12:42:43 -0800
Links: << >>  << T >>  << A >>
Hi George,

All SOPC builder info is stored in a single file with a PTF extension
and is easily editable. I do much of my editing this way as well. Just
be wary of your curly braces! Missing one will often not result in
SOPC Builder complaining, just strange behaviour.

A fairly complete description of the PTF file is at
http://www.altera.com/literature/manual/mnl_sopcptf.pdf.

-- Pete

> Hello:
> 
> I'm creating a design usine an Altera Cyclone and the NIOS processor. 
> The SOPC builder is the Altera graphical tool for entering system
> details and peripherals.  I have several memory devices (20) that I
> need to enter and probbly change diring the design progresses.
> 
> My questions is, can I get into a text file and do these same edits?
> This would be so much faster.
> 
> George

Article: 68068
Subject: Re: study verilog or vhdl?
From: Bassman59a@yahoo.com (Andy Peters)
Date: 25 Mar 2004 13:00:50 -0800
Links: << >>  << T >>  << A >>
dreamguy007@hotmail.com (Jack) wrote in message news:<b7c82826.0403232250.4e3fbf5e@posting.google.com>...
> hi. i'm just starting out with fpga. maybe this question has popped up
> many times. which one is more useful in the industry: verilog or vhdl?
> which one do you recommend for starter?

If you're a newbie and you use VHDL, your compiler will find your bugs.

If you're a newbie and you use Verilog, your customer will find your bugs.

-a

Article: 68069
Subject: Finding Triscend A7 Examples
From: "Jeong-Gun Lee" <eulia@kjist.ac.kr>
Date: Fri, 26 Mar 2004 06:01:27 +0900
Links: << >>  << T >>  << A >>
Hi~

Recently, I start an academic project on a Triscend A7 CSoC.
There are, unfortunately, only a few and very small-sized examples, which
are provided in the A7 CSoC manual, so I cannot find a way of designing even
a simple system.

If anyone knows some design examples on the Triscend A7 CSoC, please let me
know it.

Thanks.
Best regards

- Jeong-Gun Lee


--------------------------------------------------
Jeong-Gun Lee, http://async.kjist.ac.kr/~eulia
Concurrent System Research Lab. KJIST, South Korea



Article: 68070
Subject: Re: study verilog or vhdl?
From: Joe <joe_y@invalid_address.nospam.com>
Date: Thu, 25 Mar 2004 21:30:36 +0000
Links: << >>  << T >>  << A >>
Jack wrote:
> hi. i'm just starting out with fpga. maybe this question has popped up
> many times. which one is more useful in the industry: verilog or vhdl?
> which one do you recommend for starter?
> 
> i'm also learning with a goal to implement dsp in hardware.

As you mentioned you want to implement DSP in hardware,
I would suggest you to learn verilog.  Verilog simulation
is faster than VHDL (if you have access to Synopysy VCS),
so if you want to do a simulation of a complete DSP system
it is better to do it in verilog.

As far as I know most big companies design their CPUs
in verilog, not VHDL, because of simulation resources:
- Verilog simulate faster (if you have the right simulator)
   For VHDL due to strong type nature, it need to do
   a lot of checking during compile and simulation.
   Also VHDL have more detail timing model which requires
   more computation time.
- Smaller memory requirement. In VHDL a signal can have
   "1", "H", "0", "L", "Z", "X", "U", "W" and various
   attribute including last values, last event, etc.
   While in verilog you got only "1","0", "X" and "Z".

Joe

Article: 68071
Subject: Xilinx Virtex2Pro DDR output glitch free?
From: "Craig Conway" <usemyfirstname.usemylastname@ni.getridofthis.com>
Date: Thu, 25 Mar 2004 15:44:14 -0600
Links: << >>  << T >>  << A >>
Is the mux in a Xilinx Virtex2Pro DDR output pad glitch-free if the only
signal toggling is the select?  In other words, if I tie the D-inputs of the
two DDR flip-flops to '1', will the output always be '1', or could I get
glitches corresponding to the rising or falling edge of the clock?

  Thanks very much.

      Craig



Article: 68072
Subject: Re: PWM, PLD programming ,(up/down ramp frequency)
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 26 Mar 2004 10:06:29 +1200
Links: << >>  << T >>  << A >>
Stewart Smith wrote:

<snip>
> Hi 
> I know its been some time since I last posted, had some very
> intensive(well intensive for me)report writing to do.
> Back to the matter at hand, I have managed to create the
> up/hold-down/hold counter ( I achieved this by merely telling the last
> up or down state to repeat itself until the direction input changes
> from 1-0 or 0-1, seems to work ok)
> 
> I've tried to simulate the two PLD's together using "Cadence" and had
> some success, I am achieving a variable frequency output on 1 single
> pin,
> 
> This is done by taking the four outputs from the frequency divider in
> PLD 1, feeding them as inputs to PLD 2 where there is another
> counter(4-bit) and when the input matches a count this is output to
> Pin 18.
> If you can follow my explanation the last line of code reads
> "Q4.D = (Q0&div16)#(Q1&div8)#(Q2&div4)#(Q3&div2);"

That's good - a classic Rate Multiplier in PLD.

>  I have also fed back the output from div16 which is my lowest
> frequency back as the clock source for PLD 1 (which I think is what
> was suggested)
> This now utilises five bits of PLD 2 which leaves just the three for
> the "phase engine"
> 
> What I think is needed now is to feed this back as an input so to use
> this as trigger for the ramp.
> 
> Having a little trouble trying to incorporate the two programs into
> PLD 2, do I need to declare or define that prog1 (counter) and prog2
> should run concurrently or something like.
> when I compiled the .doc file didn't show any equations for Q5..7 , so
> this is as far as I've got I feel not too far away but far enough,
> still got the control side to finalise as well as this incorporation
> stuff then no doubt a mountain of bugs just for fun.
> I know my explanations may be a bit vague and for this I ask you to
> bear with me, if anyone would like to view the, what I call programs
> (not sure anyone else would) please feel free to email me.
> Thanks 
> Stewart

  Trying to fit it into a minimal no. of SPLD is possible, but it will
make the mental gymnastics tougher.
  With a single clock, but Ctrs/State engines you wish to advance at 
different rates, you will need a manually coded Clock Enable - which
you have done already in the up/hold-down/hold counter, so use that
for hints.
  Then, when you have done this, murphy says you'll find it will exceed 
the 8 PT limit of your SPLD :)
-jg



Article: 68073
Subject: Re: Altera NIOS SOPC Builder---- Can I edit a text file
From: kempaj@yahoo.com (Jesse Kempa)
Date: 25 Mar 2004 14:09:26 -0800
Links: << >>  << T >>  << A >>
george.martin@att.net (George) wrote in message news:<e9d879fa.0403250724.43df7ce7@posting.google.com>...
> Hello:
> 
> I'm creating a design usine an Altera Cyclone and the NIOS processor. 
> The SOPC builder is the Altera graphical tool for entering system
> details and peripherals.  I have several memory devices (20) that I
> need to enter and probbly change diring the design progresses.
> 
> My questions is, can I get into a text file and do these same edits?
> This would be so much faster.
> 
> George

Hi George,

Yes you can. SOPC Builder is really a fancy text editor itself. The
underlying files are of type ".ptf"; if you are making a system named
"foo", there will be a "foo.ptf" file generated by SOPC Builder
describing the system. Each peripheral in the system is described in a
"MODULE { ... }" section. I'd suggest that you add one or two of your
20 interfaces via the GUI and then close SOPC Builder to take a look
at the PTF and make edits (be sure to back up the file as you go).

Included with the Nios kit is a document, sopcptf.pdf, which describes
most of the many PTF file entries along with their meaning and syntax
-- please note that this is an engineering document and is definitely
for the more advanced user.

By the way, what is the application you're creating if you don't mind?

Regards,
Jesse Kempa
Altera Corp.
jkempa at altera dot com

Article: 68074
Subject: Re: Clock divider preserving duty-cycle ?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 26 Mar 2004 10:10:35 +1200
Links: << >>  << T >>  << A >>
john wrote:

> Hi,
> 
> I'm looking for a way to divide a clock frequency with keeping the
> duty-cycle of the input clock . Unfortunatly, the input duty-cycle is
> unknown and I had to preserve it !

Why ? You have not preserved the frequency, and it is a clock ?
-jg





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