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I get the impression that I can not simulate the gigabit ethernet mac IP from xilinx with modelsim xe starter or modelsim xe. Only modelsim se or pe are able to do this (if you have the swift license). Can anyone confirm this? TIA, FrankArticle: 68251
Hi, Is it possible to simulate Metastability? Not in the functional simulation. But in Gate level Netlist simulation. Regards, MuthuArticle: 68252
HI All I am desperately in search of some Xilinx CPLDs Part number XC2C256-7TQFP144I. I need a quantity of 25. Can anyone suggest where I can purchase them from. Thanks for any help. NaveedArticle: 68253
>Is it possible to simulate Metastability? Not in the functional >simulation. But in Gate level Netlist simulation. What are you trying to do? I doubt if you can do anything interesting at the gate level if your gates are boxes with binary inputs/outputs and delays. Metastability is rare enough that you can't usefully simulate it in a statistical sense. You might adjust the starting conditions to tickle the timing window. You can do interesting simulations at the transistor level with Spice. That might help you estimate or understand recovery times and things like that. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68254
I'm only an amateur when it comes to kluding RS-232 setups, but I've never seen an official RS-232 receiver chip that wouldn't receive a TTL/CMOS level signal. Yes, the transmit side needs to swing below ground to meet the specs. Yes a receiver that meets specs can switch at a level such that a TTL signal won't work, but I've never seen one. >The development board uses a Maxim RS232 transceiver (MAX3237). I >looked really quickly at the datasheet, and it seems like it should be >okay with a TTL input--input threshold low and high are 1.2/1.5 V. You >should probably check yourself to make sure. That chip (and all it's friends) are also an inverter. If you are directly connecting the PIC to the RS-232 connector pins, the signal will probably be upside down. If you are bit-banging rather than using an internal UART device, you can easily fix that in software. If you are using a UART, sanity suggests adding external inverters (one in each direction) until you have things working well enough to use as a reference. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68255
Insight Memec and Unique Memec are the distributors in the UK. Other international countries can be found here http://www.xilinx.com/company/sales/ww_disti.htm . John Adair Enterpoint Ltd. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "MNQ" <corlioni1976REMOVE@yahoo.co.uk> wrote in message news:c4ds0o$72o$1@rdel.co.uk... > HI All > > I am desperately in search of some Xilinx CPLDs Part number > XC2C256-7TQFP144I. I need a quantity of 25. Can anyone suggest where I can > purchase them from. > > Thanks for any help. > > Naveed > >Article: 68256
tmlo@networks.nera.no (Tomas) writes: > Hi, > > we are planning to upgrade our Linux cluster with new nodes. These > machines will be maily dedicated to run Place&Route and, as we are > mainly targetting Xilinx devices, the main performance criteria will > be P&R times. The thread with subject "Speed of Linux vs Solaris" will give you some indication. Altera posted some Quartus numbers in an earlier thread. SPECint (www.spec.org) will give you some indication of performance. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 68257
On Tue, 30 Mar 2004 16:43:17 -0500, Ray Andraka <ray@andraka.com> wrote: [...] >(signal processing was all analog before somewhere around 1960, and >predominantly analog all the way up to around 1980). Happy memories of building FIR filters with the Reticon TAD32 tapped analog delay line, with its frightening mess of bizarre supply voltages and unpredictable output offset currents... I was doing that kind of stuff around 1982/83, because there was no other *cheap* way of doing a 10MHz FIR. And doing DSP on the digitised output of linear CCD cameras using an 8-bit microprocessor clocked at about 4MHz, to get sub-pixel interpolated edge positions. Things have moved on. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 68258
On 30 Mar 2004 15:22:53 -0800, rrr@ieee.org (Rajeev) wrote: >Hello, > >I'm plugging away climbing the Altera DSP Builder >learning curve. Right now I'm struggling with a >problem that's beyond my level of VHDL knowhow -- >I'd sure appreciate some tips. Probably better to post on comp.lang.vhdl, but I'll bite anyhow. >Problem is I'm getting a ton of warnings like this one: > > Warning: VHDL Use Clause warning at DSPBUILDER.VHD(93): > more than one Use Clause imports a declaration of simple > name std_logic_2d -- none of the declarations are > directly visible > >There are a lot of entities that have Use clauses like >this: > > library dspbuilder; > use dspbuilder.dspbuilderblock.all; > > library lpm; > use lpm.lpm_components.all; > >And both packages lpm_components and dspbuilderblock >define: > > type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>)of std_logic; > >So I think I understand where the warnings are coming >from. (In fact the report file from Simulink>SystemBuilder >synthesis shows the same warnings.) OK. >What I don't have a clue about is > >1. What are the implications of "none of the declarations > are directly visible" ? VHDL insists that a given name have only one effective definition in any given scope. The two "use" clauses both try to import the same name. VHDL decrees that neither definition is visible. Consequently, if you try to make use of that definition in your code (for example, to declare some signal) you'll get "undefined identifier" or similar errors. On the other hand, if you don't ever use the double-defined identifier, there's no problem - the warning is just a warning. >2. Other than the large number of warnings, should I care > about them ? See above. >3. The Quartus Help talks about restricting the scope of > the type declarations. How do I do that ? Since it's unlikely that you can edit the offending packages (see below), you can't. However, there is a different approach which I've described later. >4. Is it a good or bad idea to edit the dspbuilder and > lpm_components file to take out the common definitions > and put them into, say, a PackageCommon ? Probably a bad idea, because the externally-created packages could (at least in principle) be reconstructed at any time by the external tool, trashing your edits. >5. Otherwise, what's the right approach for me to be taking ? Probably just bash on the way you're already doing. However, there IS another approach. It seems likely that you don't need very much from the dspbuilderblock and lpm_components packages - probably just one or two definitions of some large components. Let's suppose that the only definitions you need are component LPM1 from lpm_components and DSP1 from dspbuilderblock. Then you can modify your use clauses to import only the names you specifically need: library dspbuilder; use dspbuilder.dspbuilderblock.DSP1; library lpm; use lpm.lpm_components.LPM1; This approach will fail if you are using anything else from the packages, of course. Notoriously, if you "use" the definition of an enumeration type, then you must also "use" the definitions of each of its enumeration literals! Alternatively you can continue importing "all" the packages, accept the warnings, and if by any chance you need to make use of the type std_logic_2D then you can explicitly fetch it from the package... library lpm; use lpm.lpm_components; -- make package name visible use lpm.lpm_components.all; -- make package contents visible -- std_logic_2D from this pkg is invisible because it's also -- imported from another package [and then in your code] signal S: lpm_components.std_logic_2D; -- selected name Hope this helps. But it sounds as though it's not really a problem in your case. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 68259
On 30 Mar 2004 20:34:54 -0800, rrr@ieee.org (Rajeev) wrote: [...] >> It's also clear that the receiver will need some time >> to consume this backlog, so the idle time between bursts >> must be long enough; the minimum time is of course >> mop-up time = backlog/R2 = N.(R1-R2)/(R1.R2) > >This is well and good if you can enforce mop-up time back to >the transmitter. But you may not be able to. Then you'll want >some additional margin to allow for the probabilities of >additional bursts arriving before the first has been digested. >The statistical properties of the source are the key, wouldn't >you agree ? Yes, definitely. My grasp of "proper" statistics isn't adequate to do anything quantitative about it :-( Fortunately, in hardware (as opposed to mathematical models) it's often possible to appeal to specific properties of the system, such as the amount of storage it contains, to set limits on some of these questions and thus to make them tractable again. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 68260
On 30 Mar 2004 23:02:22 -0800, muthusnv@yahoo.co.in (Muthu) wrote: >Hi, > >Is it possible to simulate Metastability? Not in the functional >simulation. But in Gate level Netlist simulation. depends on what "feature" of metastability you want to simulate. as far as i am concerned there are two issues with metastability: 1) you get the wrong value, ie the output of the flop settles before your cycle time but to the wrong value, 2) the output of the flop doesn't settle in your cycle time. you can reduce the probability of the second case by adding extra synchronization flops and assume the output of the last flop will always settle in time. i think case 1) is interesting to simulate and one way to do it is to modify the gate level model of the flop to give random value or inverse of the input when a setup/hold violation happens instead of an x. this way you can test whether you design is tolerant of incorrect values coming out of the synchronization.Article: 68261
Yeah, as Hal says its important to know why you want to do this? If you are looking to observe the effect of timing violations, you could tweak the gate level models of all basic elements and insert checks for timing violations. You could also propagate unknowns on a timing violation. Beware, all this could be very time consuming. Muthu wrote: > Hi, > > Is it possible to simulate Metastability? Not in the functional > simulation. But in Gate level Netlist simulation. > > Regards, > MuthuArticle: 68262
Hi all, Maybe I'm another Jurasic dinousar. First I used AHDL, a vary good language (ten years ago), very ease to learn and connections-oriented, very suitable if you come from schematic tools. Later I learn VHDL. Hard, hard, hard. Ok, it is behavior-oriented and tool independent (not completelly at the very begining, but what you want for free?). I'm agree that is very redundant, so complex to use. Finally I have learn Verilog and as all you can supose, I'm a fun of it: as simple as AHDL and as powerful as VHDL (except about 'generate' before 2000). Anyway, I'm also fun of Xilinx (coming from Altera a few years ago), so I prefer a simple language, vendor independent, and C-like. When will we use C for circuit design? ;-) Cheers, Santiago (sanpab@eis.uva.es).Article: 68263
>depends on what "feature" of metastability you want to simulate. as >far as i am concerned there are two issues with metastability: 1) you >get the wrong value, ie the output of the flop settles before your >cycle time but to the wrong value, ... That seems strange. I'd call that a setup/hold time problem. I think of metastability when you have two totally different clocks. The classic example is a keyboard interrupt. I don't care if the interrupt happens on cycle N or cycle N+1. So the value during cycle N can't be "wrong". -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68264
Hi, Newsgrouper, I began to implement a SDRAM controller a few weeks ago. Of course I started with Xilinx Xapp134 sample code. Now I have problem to get the code synthesized. Xilinx ISE XST returns following error messages: *Synthesizing Unit <sdrm>. *Related source file is H:/proj/XilinxRef/xapp134/XinlinxDemo/sdrm.vhd. *FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com *ERROR: XST failed *Process "Synthesize" did not complete. I have no problem to get Verilog code running, but I am in Germany, I have to use VHDL. :) Any one has experience with this :) Thanks StevenArticle: 68265
Hi, I have a esf file with me that contains information about multi_cycle_paths and false paths. I want to know if there is a utility that will convert this esf file to a tcl format that can be used with synopsys primetime tool. Thanks for your time MadhuriArticle: 68266
Rene Tschaggelar <none@none.net> writes: <snip> > I'd assume a -4 can replace a -6 in all cases at all > temperatures. > Isn't that the other way around - a -6 will replace a -4 in all cases? -6s are faster than -4s aren't they? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 68267
if you post it to the comp.dsp, you will get more replies I guess... Kelvin YunghaoCheng <chen7398@ms32.hinet.net> wrote in message news:c1a3ad9.0403302140.72e1605e@posting.google.com... > Hi folks!! > Now ,I am designing a real-time visual tracking system based on FPGAs. > > > The images are captured by the CCD camera, and we do edge detection > by using (Sobel-mask) 2D convolver. > We also use two consecutive image > frames I(k) and I(k-1) to subtracted pixel by pixel ,in order to > find out the moving object. > > A "Moving Edge" is include by doing a logic AND operation between the > subtracted image and the edge image(obtained by Sobel-mask)of the > current frame. > > After finding out the "Moving Edge" we must to extract the object's > shape > by using Active Contour Model(or snake). > > Now I have implemented the "Moving Edge" detection function on > a Xilinx FPGA.The next step is to design the "Snake-Based Outline > Extraction" > function block. I've found a lot of reference papers on the Google > about the > "active contour model" and finally I want to choose two methods--> One > is Greedy algorithm based snake-model and the other one is Gradient > Vector Flow (GVF)based algorithm. > I wonder which one is more suitable for FPGA based architecture > design? > Could anyone can give me some recommendations or you have any other > good ideas > to design the object outline extraction function on FPGA..?? > > Thanks a lot!!Article: 68268
hmurray@suespammers.org (Hal Murray) writes: <snip someone else's (sorry missed the start of the thread!) Maxim RS232 chip description> > > That chip (and all it's friends) are also an inverter. Only in the sense that a TTL1 on the input resutls in a -ve voltage at the output. The is how RS232 works - a MARK (1) is defined as -3V to -15V (IIRC) and a SPACE(0) +3V to +15V. > If you are > directly connecting the PIC to the RS-232 connector pins, the signal will > probably be upside down. Compared with what your intuition might suggest, but its right :-) > If you are bit-banging rather than > using an internal UART device, you can easily fix that in software. > If you are using a UART, sanity suggests adding external inverters > (one in each direction) until you have things working well enough > to use as a reference. > Are you suggesting connecting a "real" RS232 device via some inverters directly to the UART of a processor? That sounds like a recipe for diasaster to me, if the external device is pumping out +-12V RS232 signals! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 68269
Steven wrote: > Xilinx ISE XST returns following error messages: > *FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13 > Any one has experience with this :) Not exactly, but have a look at this: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=17481 Maybe that will help. -- Best regards, Sean DurkinArticle: 68270
Martin Thompson wrote: > Rene Tschaggelar <none@none.net> writes: > > <snip> > >>I'd assume a -4 can replace a -6 in all cases at all >>temperatures. >> > > > Isn't that the other way around - a -6 will replace a -4 in all cases? > -6s are faster than -4s aren't they? I'm not familiar with the Virtex family. It could be that the -6 is faster. A look at the price is possibly faster than a look at the datasheet. ReneArticle: 68271
On Wed, 31 Mar 2004 10:08:20 +0200, Petter Gustad wrote: > tmlo@networks.nera.no (Tomas) writes: > >> Hi, >> >> we are planning to upgrade our Linux cluster with new nodes. These >> machines will be maily dedicated to run Place&Route and, as we are >> mainly targetting Xilinx devices, the main performance criteria will >> be P&R times. > > The thread with subject "Speed of Linux vs Solaris" will give you some > indication. Altera posted some Quartus numbers in an earlier thread. > SPECint (www.spec.org) will give you some indication of performance. > > Petter The spec marks aren't a good indicator because the Intel numbers are using the Intel compilers which are much better than any other compilers. The tools are probably compiled using GCC not Intels compilers.Article: 68272
Hi Jean, I know that the frequency synthesis shows is only estimated. The real problem is that I have a .xcf file in which I have defined clk freq constraint, and after PAR everything looks OK. ISE even reports that timing constraints are met. Later, when I run gate level simulation, using frequency which is close to the maximal, I do not get good results. BR, MarijaArticle: 68273
Hal, I ran a whole series of spice simulations, and compared them to the results from Peter's experiments. It is true that spice makes something that "looks" like metastability happen, but different versions of spice give radically different results, so I suspect that the simulator is not simulating the actual metastable process, but is an artifact of the simulator itself. Austin Hal Murray wrote: >>Is it possible to simulate Metastability? Not in the functional >>simulation. But in Gate level Netlist simulation. > > > What are you trying to do? > > I doubt if you can do anything interesting at the gate level > if your gates are boxes with binary inputs/outputs and delays. > > Metastability is rare enough that you can't usefully simulate > it in a statistical sense. You might adjust the starting > conditions to tickle the timing window. > > You can do interesting simulations at the transistor level with Spice. > That might help you estimate or understand recovery times and > things like that. >Article: 68274
Hi ! I am looking for a Virtex 2 PRO development platform. I found something that I really liked from AVNET (ADS-XLX-V2PRO-LX-EVLP7-6) with a V2P7-6 for $599. I can even get it bundled with Linux, EDK and a comm module for $1000 USD. I really wanted to buy it, but for some reason AVNET just refuses to get sell it to me ! I've been trying for over two weeks now ! Anyway, I was wondering if somebody could recommend a similar platform from another vendor. Specially if it is in the same price range. I'd also consider something with a V2P20 ... Any pointers (and offers ;*) appreciated ! Best Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA Tools
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